binutils-gdb

Commit Graph

Author	SHA1	Message	Date
Tsukasa OI	41d6ac5da6	RISC-V: Cache management instructions This commit adds 'Zicbom' / 'Zicboz' instructions. bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Add handling for new instruction classes. include/ChangeLog: * opcode/riscv-opc.h (MATCH_CBO_CLEAN, MASK_CBO_CLEAN, MATCH_CBO_FLUSH, MASK_CBO_FLUSH, MATCH_CBO_INVAL, MASK_CBO_INVAL, MATCH_CBO_ZERO, MASK_CBO_ZERO): New macros. * opcode/riscv.h (enum riscv_insn_class): Add new instruction classes INSN_CLASS_ZICBOM and INSN_CLASS_ZICBOZ. opcodes/ChangeLog: * riscv-opc.c (riscv_opcodes): Add cache-block management instructions.	5 years ago
Tsukasa OI	3b374308d3	RISC-V: Prefetch hint instructions and operand set This commit adds 'Zicbop' hint instructions. bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Add handling for new instruction class. gas/ChangeLog: * config/tc-riscv.c (riscv_ip): Add handling for new operand type 'f' (32-byte aligned pseudo S-type immediate for prefetch hints). (validate_riscv_insn): Likewise. include/ChangeLog: * opcode/riscv-opc.h (MATCH_PREFETCH_I, MASK_PREFETCH_I, MATCH_PREFETCH_R, MASK_PREFETCH_R, MATCH_PREFETCH_W, MASK_PREFETCH_W): New macros. * opcode/riscv.h (enum riscv_insn_class): Add new instruction class INSN_CLASS_ZICBOP. opcodes/ChangeLog: * riscv-dis.c (print_insn_args): Add handling for new operand type. * riscv-opc.c (riscv_opcodes): Add prefetch hint instructions.	5 years ago
Tsukasa OI	9a9dfb6880	RISC-V: Fix mask for some fcvt instructions This commit fixes incorrect uses of mask values in 'fcvt' instruction family. opcodes/ChangeLog: * riscv-opc.c (riscv_opcodes): Fix incorrect uses of mask values in 'fcvt' instruction family.	5 years ago
Alan Modra	a2c5833233	Update year range in copyright notice of binutils files The result of running etc/update-copyright.py --this-year, fixing all the files whose mode is changed by the script, plus a build with --enable-maintainer-mode --enable-cgen-maint=yes, then checking out /po/.pot which we don't update frequently. The copy of cgen was with commit d1dd5fcc38ead reverted as that commit breaks building of bfp opcodes files.	5 years ago
Vineet Gupta	a63375ac33	RISC-V: Hypervisor ext: support Privileged Spec 1.12 This is the Hypervisor Extension 1.0 - Hypervisor Memory-Management Instructions HFENCE.VVMA, HFENCE.GVMA, - Hypervisor Virtual Machine Load and Store Instructions HLV.B, HLV.BU, HSV.B, HLV.H, HLV.HU, HLVX.HU, HSB.H, HLV.W, HLV.WU, HLVX.WU, HSV.W, HLV.D, HSV.D - Hypervisor CSRs (some new, some address changed) hstatus, hedeleg, hideleg, hie, hcounteren, hgeie, htval, hip, hvip, htinst, hgeip, henvcfg, henvcfgh, hgatp, hcontext, htimedelta, htimedeltah, vsstatus, vsie, vstvec, vsscratch, vsepc, vscause, vstval, vsip, vsatp, Note that following were added already as part of svinval extension support: HINVAL.GVMA, HINVAL.VVMA Signed-off-by: Vineet Gupta <vineetg@rivosinc.com> Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com> Reviewed-by: Nelson Chu <nelson.chu@sifive.com> bfd/ * cpu-riscv.c (riscv_priv_specs): Added entry for 1.12. * cpu-riscv.h (enum riscv_spec_class): Added PRIV_SPEC_CLASS_1P12. gas/ * config/tc-riscv.c (abort_version): Updated comment. (validate_riscv_insn): Annotate switch-break. * testsuite/gas/riscv/h-ext-32.d: New testcase for hypervisor. * testsuite/gas/riscv/h-ext-32.s: Likewise. * testsuite/gas/riscv/h-ext-64.d: Likewise. * testsuite/gas/riscv/h-ext-64.s: Likewise. include/ * opcode/riscv-opc.h: Added encodings for hypervisor csrs and instrcutions. opcodes/ * riscv-opc.c (riscv_opcodes): Added hypervisor instrcutions.	5 years ago
Nelson Chu	23ff54c27d	RISC-V: Support svinval extension with frozen version 1.0. According to the privileged spec, there are five new instructions for svinval extension. Two of them (HINVAL.VVMA and HINVAL.GVMA) need to enable the hypervisor extension. But there is no implementation of hypervisor extension in mainline for now, so let's consider the related issues later. 31..25 24..20 19..15 14..12 11...7 6..2 1..0 sinval.vma 0001011 rs2 rs1 000 00000 11100 11 sfence.w.inval 0001100 00000 00000 000 00000 11100 11 sfence.inval.ir 0001100 00001 00000 000 00000 11100 11 hinval.vvma 0010011 rs2 rs1 000 00000 11100 11 hinval.gvma 0110011 rs2 rs1 000 00000 11100 11 This patch is cherry-picked from the riscv integration branch since the svinval extension is frozen for now. Besides, we fix the funct7 encodings of hinval.vvma and hinval.gvma, from 0x0011011 and 0x0111011 to 0x0010011 and 0x0110011. bfd/ * elfxx-riscv.c (riscv_supported_std_s_ext): Added svinval. (riscv_multi_subset_supports): Handle INSN_CLASS_SVINVAL. gas/ * testsuite/gas/riscv/svinval.d: New testcase. * testsuite/gas/riscv/svinval.s: Likewise. include/ * opcode/riscv-opc.h: Added encodings for svinval. * opcode/riscv.h (enum riscv_insn_class): Added INSN_CLASS_SVINVAL. opcodes/ * riscv-opc.c (riscv_opcodes): Added svinval instructions.	5 years ago
Nelson Chu	ee083a9e7c	RISC-V: Dump vset[i]vli immediate as numbers once vsew or vlmul is reserved. Consider the following case, vsetvli a0, a1, 0x4 # unrecognized vlmul vsetvli a0, a1, 0x20 # unrecognized vsew vsetivli a0, 0xb, 0x4 # unrecognized vlmul vsetivli a0, 0xb, 0x20 # unrecognized vsew For the current dis-assembler, we get the result, 0000000000000000 <.text>: 0: 0045f557 vsetvli a0,a1,e8,(null),tu,mu 4: 0205f557 vsetvli a0,a1,e128,m1,tu,mu 8: c045f557 vsetivli a0,11,e8,(null),tu,mu c: c205f557 vsetivli a0,11,e128,m1,tu,mu The vsew e128 and vlmul (null) are preserved according to the spec, so dump these fields looks wrong. Consider that we are used to dump the unrecognized csr as csr numbers directly, we should also dump the whole vset[i]vli immediates as numbers, once the vsew or vlmul is reserved. Therefore, following is what I expected, 0000000000000000 <.text>: 0: 0045f557 vsetvli a0,a1,4 4: 0205f557 vsetvli a0,a1,32 8: c045f557 vsetivli a0,11,4 c: c205f557 vsetivli a0,11,32 gas/ * testsuite/gas/riscv/vector-insns.d: Rewrite the vset[i]vli testcases since we should dump the immediate as numbers once the vsew or vlmul is reserved. * testsuite/gas/riscv/vector-insns.s: Likewise. opcodes/ * riscv-dis.c (print_insn_args): The reserved vsew and vlmul are NULL string in the riscv_vsew and riscv_vlmul, so dump the whole imm as numbers once one of them is NULL. * riscv-opc.c (riscv_vsew): Set the reserved vsew to NULL. (riscv_vlmul): Set the reserved vlmul to NULL.	5 years ago
jiawei	de83e5142d	RISC-V: Add instructions and operand set for z[fdq]inx Reuse float instructions in INSN_CLASS_F/D/Q, use riscv_subset_supports to verify if zinx enabled and use gpr instead of fpr when zinx is enable. bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Added support for zinx extension. gas/ChangeLog: config/tc-riscv.c (riscv_ip): Added register choice for zinx. include/ChangeLog: opcode/riscv.h (enum riscv_insn_class): Reused INSN_CLASS_* for zinx. opcodes/ChangeLog: riscv-dis.c (riscv_disassemble_insn): Added disassemble check for zinx. riscv-opc.c: Reused INSN_CLASS_* for z*inx. Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>	5 years ago
Nelson Chu	65e4a99a26	RISC-V: Support rvv extension with released version 1.0. 2021-11-17 Jim Wilson <jimw@sifive.com> Kito Cheng <kito.cheng@sifive.com> Nelson Chu <nelson.chu@sifive.com> This patch is porting from the following riscv github, https://github.com/riscv/riscv-binutils-gdb/tree/rvv-1.0.x And here is the vector spec, https://github.com/riscv/riscv-v-spec bfd/ * elfxx-riscv.c (riscv_implicit_subsets): Added imply rules of v, zve and zvl extensions. (riscv_supported_std_ext): Updated verison of v to 1.0. (riscv_supported_std_z_ext): Added zve and zvl extensions. (riscv_parse_check_conflicts): The zvl extensions need to enable either v or zve extension. (riscv_multi_subset_supports): Check the subset list to know if the INSN_CLASS_V and INSN_CLASS_ZVEF instructions are supported. gas/ * config/tc-riscv.c (enum riscv_csr_class): Added CSR_CLASS_V. (enum reg_class): Added RCLASS_VECR and RCLASS_VECM. (validate_riscv_insn): Check whether the rvv operands are valid. (md_begin): Initialize register hash for rvv registers. (macro_build): Added rvv operands when expanding rvv pseudoes. (vector_macro): Expand rvv macros into one or more instructions. (macro): Likewise. (my_getVsetvliExpression): Similar to my_getVsetvliExpression, but used for parsing vsetvli operands. (riscv_ip): Parse and encode rvv operands. Besides, The rvv loads and stores with EEW 64 cannot be used when zve32x is enabled. * testsuite/gas/riscv/priv-reg-fail-version-1p10.d: Updated -march to rv32ifv_zkr. * testsuite/gas/riscv/priv-reg-fail-version-1p11.d: Likewise. * testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d: Likewise. * testsuite/gas/riscv/priv-reg.s: Added rvv csr testcases. * testsuite/gas/riscv/priv-reg-version-1p10.d: Likewise. * testsuite/gas/riscv/priv-reg-version-1p11.d: Likewise. * testsuite/gas/riscv/priv-reg-version-1p9p1.d: Likewise. * testsuite/gas/riscv/march-imply-v.d: New testcase. * testsuite/gas/riscv/vector-insns-fail-zve32xf.d: Likewise. * testsuite/gas/riscv/vector-insns-fail-zve32xf.l: Likewise. * testsuite/gas/riscv/vector-insns-fail-zvl.d: Likewise. * testsuite/gas/riscv/vector-insns-fail-zvl.l: Likewise. * testsuite/gas/riscv/vector-insns-vmsgtvx.d: Likewise. * testsuite/gas/riscv/vector-insns-vmsgtvx.s: Likewise. * testsuite/gas/riscv/vector-insns-zero-imm.d: Likewise. * testsuite/gas/riscv/vector-insns-zero-imm.s: Likewise. * testsuite/gas/riscv/vector-insns.d: Likewise. * testsuite/gas/riscv/vector-insns.s: Likewise. include/ * opcode/riscv-opc.h: Defined mask/match encodings and csrs for rvv. * opcode/riscv.h: Defined rvv immediate encodings and fields. (enum riscv_insn_class): Added INSN_CLASS_V and INSN_CLASS_ZVEF. (INSN_V_EEW64): Defined. (M_VMSGE, M_VMSGEU): Added for the rvv pseudoes. opcodes/ * riscv-dis.c (print_insn_args): Dump the rvv operands. * riscv-opc.c (riscv_vecr_names_numeric): Defined rvv registers. (riscv_vecm_names_numeric): Likewise. (riscv_vsew): Likewise. (riscv_vlmul): Likewise. (riscv_vta): Likewise. (riscv_vma): Likewise. (match_vs1_eq_vs2): Added for rvv Vu operand. (match_vd_eq_vs1_eq_vs2): Added for rvv Vv operand. (riscv_opcodes): Added rvv v1.0 instructions.	5 years ago
jiawei	3d1cafa0c6	RISC-V: Scalar crypto instructions and operand set. Add instructions in k-ext, some instruction in zbkb, zbkc is reuse from zbb,zbc, we just change the class attribute to make them both support. The 'aes64ks1i' and 'aes64ks2' instructions are present in both the Zknd and Zkne extensions on rv64. Add new operand letter 'y' to present 'bs' symbol and 'Y' to present 'rnum' symbolc for zkn instructions. Also add a new Entropy Source CSR define 'seed' located at address 0x015. bfd/ * elfxx-riscv.c (riscv_multi_subset_supports): Added support for crypto extension. gas/ config/tc-riscv.c (enum riscv_csr_class): Added CSR_CLASS_ZKR. (riscv_csr_address): Checked for CSR_CLASS_ZKR. (validate_riscv_insn): Added y and Y for bs and rnum operands. (riscv_ip): Handle y and Y operands. include/ opcode/riscv-opc.h: Added encodings of crypto instructions. Also defined new csr seed, which address is 0x15. * opcode/riscv.h: Defined OP_* and INSN_CLASS_* for crypto. opcodes/ * riscv-dis.c (print_insn_args): Recognized new y and Y operands. * riscv-opc.c (riscv_opcodes): Added crypto instructions.	5 years ago
Philipp Tomsich	8baf3d0756	RISC-V: Support aliases for Zbs instructions Add aliases for the non-immediate mnemonics of b{set,clr,inv,ext} to yencode the respective immediate insn b{set,clr,inv,ext}i when the second source operand is an immediate. 2021-01-11 Philipp Tomsich <philipp.tomsich@vrull.eu> gas/ * testsuite/gas/riscv/b-ext.d: Add tests. * testsuite/gas/riscv/b-ext.s: Likewise. * testsuite/gas/riscv/b-ext-64.d: Likewise. * testsuite/gas/riscv/b-ext-64.s: Likewise. opcodes/ * riscv-opc.c (riscv_opcodes): Add aliases for Zbs. Suggested-by: Jan Beulich <jbeulich@suse.com> Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>	5 years ago
Philipp Tomsich	9455c91957	RISC-V: Add support for Zbs instructions This change adds the Zbs instructions from the Zbs 1.0.0 specification. See https://github.com/riscv/riscv-bitmanip/releases/tag/1.0.0 for the frozen specification. 2021-01-09 Philipp Tomsich <philipp.tomsich@vrull.eu> bfd/ * elfxx-riscv.c (riscv_supported_std_z_ext): Added zbs. gas/ * config/tc-riscv.c (riscv_multi_subset_supports): Handle INSN_CLASS_ZBS. * testsuite/gas/riscv/b-ext.d: Test Zbs instructions. * testsuite/gas/riscv/b-ext.s: Likewise. * testsuite/gas/riscv/b-ext-64.d: Likewise. * testsuite/gas/riscv/b-ext-64.s: Likewise. include/ * opcode/riscv-opc.h: Added MASK/MATCH/DECLARE_INSN for Zbs. * opcode/riscv.h (riscv_insn_class): Added INSN_CLASS_ZBS. opcodes/ * riscv-opc.c (riscv_supported_std_z_ext): Add zbs. Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>	5 years ago
Philipp Tomsich	cda0561f9e	RISC-V: Split Zb[abc] into commented sections The Zb[abc] opcodes are bundled just below the Privileged opcodes in riscv_opcodes, possibly giving the appearance that they are part of the Privileged spec for an uninitiated reader. This separates them out and adds comments above each section to clearly identify them as Zba, Zbb or Zbc opcodes. 2021-10-04 Philipp Tomsich <philipp.tomsich@vrull.eu> opcodes/ * riscv-opc.c: Split of Zb[abc] instructions and add comments. Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>	5 years ago
Lifang Xia	a8ab209320	RISC-V: compress "addi d,CV,z" to "c.mv d,CV" PR 27732 gas/ * testsuite/gas/riscv/c-zero-imm.d: Compress addi a4,a4,0 to c.mv a4,a4. * testsuite/gas/riscv/c-zero-imm.s: Likewise. opcodes/ * riscv-opc.c (riscv_opcodes): New insn alias for addi. Compress "addi d,CV,z" to "c.mv d,CV".	5 years ago
Kuan-Lin Chen	80d49d6a1b	RISC-V : Support bitmanip-0.93 ZBA/ZBB/ZBC instructions bfd/ * elfxx-riscv.c (riscv_std_z_ext_strtab): Add zba, zbb and zbc. gas/ * config/tc-riscv.c (ext_version_table): Add b, zba, zbb and zbc. (riscv_multi_subset_supports): Add INSN_CLASS_ZB. testsuite/gas/riscv/b-ext-64.s: Bitmanip test case. * testsuite/gas/riscv/b-ext-64.d: Likewise. * testsuite/gas/riscv/b-ext.s: Likewise. * testsuite/gas/riscv/b-ext.d: Likewise. include/ * opcode/riscv-opc.h: Support zba, zbb and zbc extensions. * opcode/riscv.h (riscv_insn_class): Add INSN_CLASS_ZB. opcodes/ riscv-opc.c (riscv_opcodes): Add zba, zbb and zbc instructions.	6 years ago
Nelson Chu	5a9f5403c7	RISC-V: PR27158, fixed UJ/SB types and added CSS/CL/CS types for .insn. * Renamed obsolete UJ/SB types and RVC types, also added CSS/CL(CS) types, [VALID/EXTRACT/ENCODE macros] BTYPE_IMM: Renamed from SBTYPE_IMM. JTYPE_IMM: Renamed from UJTYPE_IMM. CITYPE_IMM: Renamed from RVC_IMM. CITYPE_LUI_IMM: Renamed from RVC_LUI_IMM. CITYPE_ADDI16SP_IMM: Renamed from RVC_ADDI16SP_IMM. CITYPE_LWSP_IMM: Renamed from RVC_LWSP_IMM. CITYPE_LDSP_IMM: Renamed from RVC_LDSP_IMM. CIWTYPE_IMM: Renamed from RVC_UIMM8. CIWTYPE_ADDI4SPN_IMM: Renamed from RVC_ADDI4SPN_IMM. CSSTYPE_IMM: Added for .insn without special encoding. CSSTYPE_SWSP_IMM: Renamed from RVC_SWSP_IMM. CSSTYPE_SDSP_IMM: Renamed from RVC_SDSP_IMM. CLTYPE_IMM: Added for .insn without special encoding. CLTYPE_LW_IMM: Renamed from RVC_LW_IMM. CLTYPE_LD_IMM: Renamed from RVC_LD_IMM. RVC_SIMM3: Unused and removed. CBTYPE_IMM: Renamed from RVC_B_IMM. CJTYPE_IMM: Renamed from RVC_J_IMM. * Added new operands and removed the unused ones, C5: Unsigned CL(CS) immediate, added for .insn directive. C6: Unsigned CSS immediate, added for .insn directive. Ci: Unused and removed. C<: Unused and removed. bfd/ PR 27158 * elfnn-riscv.c (perform_relocation): Updated encoding macros. (_bfd_riscv_relax_call): Likewise. (_bfd_riscv_relax_lui): Likewise. * elfxx-riscv.c (howto_table): Likewise. gas/ PR 27158 * config/tc-riscv.c (riscv_ip): Updated encoding macros. (md_apply_fix): Likewise. (md_convert_frag_branch): Likewise. (validate_riscv_insn): Likewise. Also arranged operands, including added C5 and C6 operands, and removed unused Ci and C< operands. * doc/c-riscv.texi: Updated and added CSS/CL/CS types. * testsuite/gas/riscv/insn.d: Added CSS/CL/CS instructions. * testsuite/gas/riscv/insn.s: Likewise. gdb/ PR 27158 * riscv-tdep.c (decode_ci_type_insn): Updated encoding macros. (decode_j_type_insn): Likewise. (decode_cj_type_insn): Likewise. (decode_b_type_insn): Likewise. (decode): Likewise. include/ PR 27158 * opcode/riscv.h: Updated encoding macros. opcodes/ PR 27158 * riscv-dis.c (print_insn_args): Updated encoding macros. * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM. (match_c_addi16sp): Updated encoding macros. (match_c_lui): Likewise. (match_c_lui_with_hint): Likewise. (match_c_addi4spn): Likewise. (match_c_slli): Likewise. (match_slli_as_c_slli): Likewise. (match_c_slli64): Likewise. (match_srxi_as_c_srxi): Likewise. (riscv_insn_types): Added .insn css/cl/cs. sim/ PR 27158 * riscv/sim-main.c (execute_i): Updated encoding macros.	6 years ago
Nelson Chu	3d73d29e4e	RISC-V: Add bfd/cpu-riscv.h to support all spec versions controlling. Make the opcode/riscv-opc.c and include/opcode/riscv.h tidy, move the spec versions stuff to bfd/cpu-riscv.h. Also move the csr stuff and ext_version_table to gas/config/tc-riscv.c for internal use. To avoid too many repeated code, define general RISCV_GET_SPEC_NAME/SPEC_CLASS macros. Therefore, assembler/dis-assembler/linker/gdb can get all spec versions related stuff from cpu-riscv.h and cpu-riscv.c, since the stuff are defined there uniformly. bfd/ * Makefile.am: Added cpu-riscv.h. * Makefile.in: Regenerated. * po/SRC-POTFILES.in: Regenerated. * cpu-riscv.h: Added to support spec versions controlling. Also added extern arrays and functions for cpu-riscv.c. (enum riscv_spec_class): Define all spec classes here uniformly. (struct riscv_spec): Added for all specs. (RISCV_GET_SPEC_CLASS): Added to reduce repeated code. (RISCV_GET_SPEC_NAME): Likewise. (RISCV_GET_ISA_SPEC_CLASS): Added to get ISA spec class. (RISCV_GET_PRIV_SPEC_CLASS): Added to get privileged spec class. (RISCV_GET_PRIV_SPEC_NAME): Added to get privileged spec name. * cpu-riscv.c (struct priv_spec_t): Replaced with struct riscv_spec. (riscv_get_priv_spec_class): Replaced with RISCV_GET_PRIV_SPEC_CLASS. (riscv_get_priv_spec_name): Replaced with RISCV_GET_PRIV_SPEC_NAME. (riscv_priv_specs): Moved below. (riscv_get_priv_spec_class_from_numbers): Likewise, updated. (riscv_isa_specs): Moved from include/opcode/riscv.h. * elfnn-riscv.c: Included cpu-riscv.h. (riscv_merge_attributes): Initialize in_priv_spec and out_priv_spec. * elfxx-riscv.c: Included cpu-riscv.h and opcode/riscv.h. (RISCV_UNKNOWN_VERSION): Moved from include/opcode/riscv.h. * elfxx-riscv.h: Removed extern functions to cpu-riscv.h. gas/ * config/tc-riscv.c: Included cpu-riscv.h. (enum riscv_csr_clas): Moved from include/opcode/riscv.h. (struct riscv_csr_extra): Likewise. (struct riscv_ext_version): Likewise. (ext_version_table): Moved from opcodes/riscv-opc.c. (default_isa_spec): Updated type to riscv_spec_class. (default_priv_spec): Likewise. (riscv_set_default_isa_spec): Updated. (init_ext_version_hash): Likewise. (riscv_init_csr_hash): Likewise, also fixed indent. include/ * opcode/riscv.h: Moved stuff and make the file tidy. opcodes/ * riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h. (default_priv_spec): Updated type to riscv_spec_class. (parse_riscv_dis_option): Updated. * riscv-opc.c: Moved stuff and make the file tidy.	6 years ago
Nelson Chu	24075dcc85	RISC-V: Removed the v0.93 bitmanip ZBA/ZBB/ZBC instructions. bfd/ * elfxx-riscv.c (riscv_parse_prefixed_ext): Removed zb. gas/ config/tc-riscv.c (riscv_multi_subset_supports): Removed INSN_CLASS_ZB. testsuite/gas/riscv/bitmanip-insns-32.d: Removed. * testsuite/gas/riscv/bitmanip-insns-64.d: Removed. * testsuite/gas/riscv/bitmanip-insns.s: Removed. include/ * opcode/riscv-opc.h: Removed macros for zb* extensions. * opcode/riscv.h (riscv_insn_class): Removed INSN_CLASS_ZB. opcodes/ riscv-opc.c (MASK_RVB_IMM): Removed. (riscv_opcodes): Removed zb* instructions. (riscv_ext_version_table): Removed versions for zb*.	6 years ago
Nelson Chu	1942a04836	RISC-V: Indent and GNU coding standards tidy, also aligned the code. bfd/ * elfnn-riscv.c: Indent, labels and GNU coding standards tidy, also aligned the code. gas/ * config/tc-riscv.c: Indent and GNU coding standards tidy, also aligned the code. * config/tc-riscv.h: Likewise. include/ * opcode/riscv.h: Indent and GNU coding standards tidy, also aligned the code. opcodes/ * riscv-opc.c (riscv_gpr_names_abi): Aligned the code. (riscv_fpr_names_abi): Likewise. (riscv_opcodes): Likewise. (riscv_insn_types): Likewise.	6 years ago
Nelson Chu	dcd709e056	RISC-V: Comments tidy and improvement. The GNU coding standards said the comments should be complete sentences and end with a period and two spaces. But sometimes it should be more cleaner when the comments only include a word or codes. Therefore, I made the following changes after referring to other target/generic codes, * Try to write sentences in comments, must end with a period and two spaces. * End with two spaces without a period for codes/instructions only. * End with one space without a period for a single word/variable only. Besids, also rewrite/remove some comments which are obsolete or too long, and fix indents for comments. bfd/ * elfnn-riscv.c: Comments tidy and improvement. * elfxx-riscv.c: Likewise. * elfxx-riscv.h: Likewise. gas/ * config/tc-riscv.c: Comments tidy and improvement. Also update comment "fallthru" to "Fall through" that end with a period and two spaces. include/ * elf/riscv.h: Comments tidy and improvement. * opcode/riscv-opc.h: Likewise. * opcode/riscv.h: Likewise. opcodes/ * riscv-dis.c: Comments tidy and improvement. * riscv-opc.c: Likewise.	6 years ago
Philipp Tomsich	aa881ecde4	RISC-V: Add pause hint instruction. Add support for the pause hint instruction, as specified in the Zihintpause extension. The pause instruction is encoded as a special form of a memory fence (which is available as part of the base instruction set). The chosen encoding does not mandate any particular memory ordering and therefore is a true hint. bfd/ * elfxx-riscv.c (riscv_std_z_ext_strtab): Added zihintpause. gas/ * config/tc-riscv.c (riscv_multi_subset_supports): Added INSN_CLASS_ZIHINTPAUSE. * testsuite/gas/riscv/pause.d: New testcase. Adding coverage for the pause hint instruction. * testsuite/gas/riscv/pause.s: Likewise. include/ * opcode/riscv-opc.h: Added MATCH_PAUSE, MASK_PAUSE and DECLARE_INSN for pause hint instruction. * opcode/riscv.h (enum riscv_insn_class): Added INSN_CLASS_ZIHINTPAUSE. opcodes/ * riscv-opc.c (riscv_opcodes): Add pause hint instruction.	6 years ago
Claire Xenia Wolf	2652cfad8d	RISC-V: Support riscv bitmanip frozen ZBA/ZBB/ZBC instructions (v0.93). In fact rev8/orc.b/zext.h are the aliases of grevi/gorci/pack[w], so we should update them to INSN_ALIAS when we have supported their true instruction in the future. Though we still use the [MATCH\|MAKS]_[GREVI\|GORCI\|PACK\|PACKW] to encode them. Besides, the orc.b has the same encoding both in rv32 and rv64, so we just keep one of them in the opcode table. This patch is implemented according to the following link, https://github.com/riscv/riscv-bitmanip/pull/101 2021-01-07 Claire Xenia Wolf <claire@symbioticeda.com> Jim Wilson <jimw@sifive.com> Andrew Waterman <andrew@sifive.com> Maxim Blinov <maxim.blinov@embecosm.com> Kito Cheng <kito.cheng@sifive.com> Nelson Chu <nelson.chu@sifive.com> bfd/ * elfxx-riscv.c (riscv_std_z_ext_strtab): Added zba, zbb and zbc. gas/ * config/tc-riscv.c (riscv_multi_subset_supports): Handle INSN_CLASS_ZB. (riscv_get_default_ext_version): Do not check the default_isa_spec when the version defined in the riscv_opcodes table is ISA_SPEC_CLASS_DRAFT. testsuite/gas/riscv/bitmanip-insns-32.d: New testcase. * testsuite/gas/riscv/bitmanip-insns-64.d: Likewise. * testsuite/gas/riscv/bitmanip-insns.s: Likewise. include/ * opcode/riscv-opc.h: Added MASK/MATCH/DECLARE_INSN for ZBA/ZBB/ZBC. * opcode/riscv.h (riscv_insn_class): Added INSN_CLASS_ZB. (enum riscv_isa_spec_class): Added ISA_SPEC_CLASS_DRAFT for the frozen extensions. opcodes/ riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions. (MASK_RVB_IMM): Used for rev8 and orc.b encoding.	6 years ago
Alan Modra	250d07de5c	Update year range in copyright notice of binutils files	6 years ago
Nelson Chu	c2137f55ad	RISC-V: Add sext.[bh] and zext.[bhw] pseudo instructions. https://github.com/riscv/riscv-asm-manual/pull/61 We aleady have sext.w, so just add sext.b, sext.h, zext.b, zext.h and zext.w. In a certain sense, zext.b is not a pseudo - It is an alias of andi. Similarly, sext.b and sext.h are aliases of other rvb instructions, when we enable b extension; But they are pseudos when we just enable rvi. However, this patch does not consider the rvb cases. Besides, zext.w is only valid in rv64. gas/ * config/tc-riscv.c (riscv_ext): New function. Use md_assemblef to expand the zext and sext pseudos, to give them a chance to be expanded into c-ext instructions. (macro): Handle M_ZEXTH, M_ZEXTW, M_SEXTB and M_SEXTH. * testsuite/gas/riscv/ext.s: New testcase. * testsuite/gas/riscv/ext-32.d: Likewise. * testsuite/gas/riscv/ext-64.d: Likewise. include/ * opcode/riscv.h (M_ZEXTH, M_ZEXTW, M_SEXTB, M_SEXTH.): Added. opcodes/ * riscv-opc.c (riscv_opcodes): Add sext.[bh] and zext.[bhw].	6 years ago
Nelson Chu	729a53530e	RISC-V: Control fence.i and csr instructions by zifencei and zicsr. bfd/ * elfxx-riscv.c (riscv_ext_dont_care_version): New function. Return TRUE if we don't care the versions of the extensions. These extensions are added to the subset list for special purposes, with the explicit versions or the RISCV_UNKNOWN_VERSION versions. (riscv_parse_add_subset): If we do care the versions of the extension, and the versions are unknown, then report errors for the non-implicit extensions, and return directly for the implicit one. (riscv_arch_str1): Do not output i extension after e, and the extensions which versions are unknown. gas/ * config/tc-riscv.c (riscv_multi_subset_supports): Handle INSN_CLASS_ZICSR and INSN_CLASS_ZIFENCEI. * testsuite/gas/riscv/march-imply-i.s: New testcase. * testsuite/gas/riscv/march-imply-i2p0-01.d: New testcase. The version of i is less than 2.1, and zi* are supported in the chosen spec, so enable the fence.i and csr instructions, also output the implicit zi* to the arch string. * testsuite/gas/riscv/march-imply-i2p0-02.d: Likewise, but the zi* are not supported in the spec 2.2. Enable the related instructions since i's version is less than 2.1, but do not output them. * testsuite/gas/riscv/march-imply-i2p1-01.d: New testcase. The version of i is 2.1, so don't add it's implicit zi, and disable the related instructions. testsuite/gas/riscv/march-imply-i2p1-01.l: Likewise. * testsuite/gas/riscv/march-imply-i2p1-02.d: Likewise, and set the zi* explicitly, so enable the related instructions. * testsuite/gas/riscv/march-imply-i2p0.d: Removed. * testsuite/gas/riscv/march-imply-i2p1.d: Removed. include/ * opcode/riscv.h: Add INSN_CLASS_ZICSR and INSN_CLASS_ZIFENCEI. opcodes/ * riscv-opc.c (riscv_opcodes): Control fence.i and csr instructions by zifencei and zicsr.	6 years ago
Nelson Chu	27a46348cb	RISC-V: Remove the unimplemented extensions. Although spec had defined and ratified p, v and n extensions, but we don't have any related implementaitons so far, so keep them in the supported extension table looks weird. Remove them until we have the related implementations. opcodes/ * riscv-opc.c (riscv_ext_version_table): Remove the p, v, n and their versions.	6 years ago
Nelson Chu	5a1b31e1e1	RISC-V: Add zifencei and prefixed h class extensions. bfd/ * elfxx-riscv.c (riscv_parse_std_ext): Stop parsing standard extensions when parsed h keyword. (riscv_get_prefix_class): Support prefixed h class. (riscv_std_h_ext_strtab): Likewise. (riscv_ext_h_valid_p): Likewise. (parse_config): Likewise. (riscv_std_z_ext_strtab): Add zifencei. * elfxx-riscv.h (riscv_isa_ext_class): Add RV_ISA_CLASS_H. gas/ * testsuite/gas/riscv/march-fail-order-z.d: New testcase, check orders of prefixed z extensions. * testsuite/gas/riscv/march-fail-order-z.l: Likewise. * testsuite/gas/riscv/march-fail-single-char-h.d: New testcase. * testsuite/gas/riscv/march-fail-single-char.l: Updated. * testsuite/gas/riscv/march-fail-unknown-h.d: New testcase. * testsuite/gas/riscv/march-fail-unknown.l: Updated. opcodes/ * riscv-opc.c (riscv_ext_version_table): Add zifencei.	6 years ago
Nelson Chu	39ff0b8123	RISC-V: Report warning when linking the objects with different priv specs. We do know some conflicts among different privileged specs. For linker, the safest approach is that don't allow the object linked with others which may cause conflicts. But this may cause inconvenience since not all objects with conflicting priv specs are linked will cause problems. But it is hard to know the detailed conflict cases for linker, so we probably need a option to tell linker that we do know there are no conflicts, or we are willing to take risks to link the objects with conflicted priv specs. But the option is still under discussion. Therefore, we can report warnings rather than errors when linking the objects with conflicted priv specs. This not only makes the linker more flexible, but also warns people that the conflicts may happen. We also need to update the output priv spec version once the input priv spec is newer. bfd/ * elfxx-riscv.c (struct priv_spec_t priv_specs[]): Move them from opcodes/riscv-opc.c to bfd/elfxx-riscv.c, since we need it in linker. (riscv_get_priv_spec_class): Likewise. (riscv_get_priv_spec_name): Likewise. (riscv_get_priv_spec_class_from_numbers): New function, convert the version numbers into string, then call riscv_get_priv_spec_class to get the priv spec class. * elfxx-riscv.h (riscv_get_priv_spec_class): Move forward declaration from include/opcode/riscv.h to bfd/elfxx-riscv.h. (riscv_get_priv_spec_name): Likewise. (riscv_get_priv_spec_class_from_numbers): New forward declaration. (opcode/riscv.h): Include it in the header rather than elfxx-riscv.c. * elfnn-riscv.c (riscv_merge_attributes): Get the priv spec classes of input and output objects form their priv spec attributes by riscv_get_priv_spec_class_from_numbers. Report warning rather than errors when linking objects with differnet priv spec versions. We do know v1.9.1 may have conflicts to other versions, so report the warning, too. After that, update the output priv spec version to the newest one so far. gas/ * config/tc-riscv.c (buf_size, buf): Remove the unused variables. (riscv_set_default_priv_spec): Get the priv spec version from the priv spec attributes by riscv_get_priv_spec_class_from_numbers. include/ * opcode/riscv.h (riscv_get_priv_spec_class): Move the function forward declarations to bfd/elfxx-riscv.h. (riscv_get_priv_spec_name): Likewise. opcodes/ * riscv-opc.c: Move the structures and functions to bfd/elfxx-riscv.c. * riscv-dis.c: Include elfxx-riscv.h. ld/ * testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-01.d: Updated. * testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-02.d: Updated. * testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-03.d: Updated. * testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-04.d: Updated. * testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-05.d: Updated. * testsuite/ld-riscv-elf/attr-merge-priv-spec-failed-06.d: Updated.	6 years ago
Nelson Chu	d8af286fff	RISC-V: Drop the privileged spec v1.9 support. There is a conflict between v1.9 and v1.9.1 - CSR MISA address. MISA is 0xf10 in v1.9, but change to 0x301 in v1.9.1. The change made MISA writable, but may also cause risk of compatibility. Binutils already support the -mpriv-spec options and ELF priv attributes, which can used to choose what privileged spec you want, and then give a correponding CSR name and address to use. But Gdb and other tools don't have the simialr mechanism for now. However, there are two things can be confirmed, 1. If we don't have a way to control the priv specs, then the changes, like MISA, will cause risk and hard to maintain. 2. We get the guarantee that the CSR address won't be reused in the future specs, even if it is dropped. I'm not sure if Gdb needs to care about the priv spec versions, it is still discussing. But drop the priv spec v1.9, and make sure that we won't reuse the CSR address is a useful solution for now. Also, we might drop the v1.9.1 in a year or two. After that, specs above v1.10 should be compatible anyway. gas/ * testsuite/gas/riscv/priv-reg-fail-version-1p9.d: Removed. * testsuite/gas/riscv/priv-reg-fail-version-1p9.l: Likewise. * testsuite/gas/riscv/priv-reg-version-1p9.d: Likewise. include/ * opcode/riscv-opc.h: Update the defined versions of CSR from PRIV_SPEC_CLASS_1P9 to PRIV_SPEC_CLASS_1P9P1. Also, drop the MISA DECLARE_CSR_ALIAS since it's aborted version is v1.9. * opcode/riscv.h (enum riscv_priv_spec_class): Remove PRIV_SPEC_CLASS_1P9. opcodes/ * riscv-opc.c (priv_specs): Remove v1.9 and PRIV_SPEC_CLASS_1P9.	6 years ago
Nelson Chu	44730156af	RISC-V: Fix the error when building RISC-V linux native gdbserver. The original report is as follow, https://sourceware.org/pipermail/binutils/2020-June/111383.html Inlcude the bfd.h in the include/opcode/riscv.h may cause gdbserver fail to build. I just want to use the `bfd_boolean` in the opcodes/riscv-opc.c, but I didn't realize this cause the build failed. Fortunately, I can also use the `int` as the function return types just like others in the opcodes/riscv-opc.c. include/ * opcode/riscv.h: Remove #include "bfd.h". And change the return types of riscv_get_isa_spec_class and riscv_get_priv_spec_class from bfd_boolean to int. opcodes/ * riscv-opc.c (riscv_get_isa_spec_class): Change bfd_boolean to int. (riscv_get_priv_spec_class): Likewise.	6 years ago
Nelson Chu	8f595e9b4f	[PATCH v2 0/9] RISC-V: Support version controling for ISA standard extensions and CSR 1. Remove the -mriscv-isa-version and --with-riscv-isa-version options. We can still use -march to choose the version for each extensions, so there is no need to add these. 2. Change the arguments of options from [1p9\|1p9p1\|...] to [1.9\|1.9.1\|...]. Unlike the architecture string has specified by spec, ther is no need to do the same thing for options. 3. Spilt the patches to reduce the burdens of review. [PATCH 3/7] RISC-V: Support new GAS options and configure options to set ISA versions to [PATCH v2 3/9] RISC-V: Support GAS option -misa-spec to set ISA versions [PATCH v2 4/9] RISC-V: Support configure options to set ISA versions by default. [PATCH 4/7] RISC-V: Support version checking for CSR according to privilege version. to [PATCH v2 5/9] RISC-V: Support version checking for CSR according to privilege spec version. [PATCH v2 6/9] RISC-V: Support configure option to choose the privilege spec version. 4. Use enum class rather than string to compare the choosen ISA spec in opcodes/riscv-opc.c. The behavior is same as comparing the choosen privilege spec. include * opcode/riscv.h: Include "bfd.h" to support bfd_boolean. (enum riscv_isa_spec_class): New enum class. All supported ISA spec belong to one of the class (struct riscv_ext_version): New structure holds version information for the specific ISA. * opcode/riscv-opc.h (DECLARE_CSR): There are two version information, define_version and abort_version. The define_version means which privilege spec is started to define the CSR, and the abort_version means which privilege spec is started to abort the CSR. If the CSR is valid for the newest spec, then the abort_version should be PRIV_SPEC_CLASS_DRAFT. (DECLARE_CSR_ALIAS): Same as DECLARE_CSR, but only for the obselete CSR. * opcode/riscv.h (enum riscv_priv_spec_class): New enum class. Define the current supported privilege spec versions. (struct riscv_csr_extra): Add new fields to store more information about the CSR. We use these information to find the suitable CSR address when user choosing a specific privilege spec. binutils * dwarf.c: Updated since DECLARE_CSR is changed. opcodes * riscv-opc.c (riscv_ext_version_table): The table used to store all information about the supported spec and the corresponding ISA versions. Currently, only Zicsr is supported to verify the correctness of Z sub extension settings. Others will be supported in the future patches. (struct isa_spec_t, isa_specs): List for all supported ISA spec classes and the corresponding strings. (riscv_get_isa_spec_class): New function. Get the corresponding ISA spec class by giving a ISA spec string. * riscv-opc.c (struct priv_spec_t): New structure. (struct priv_spec_t priv_specs): List for all supported privilege spec classes and the corresponding strings. (riscv_get_priv_spec_class): New function. Get the corresponding privilege spec class by giving a spec string. (riscv_get_priv_spec_name): New function. Get the corresponding privilege spec string by giving a CSR version class. * riscv-dis.c: Updated since DECLARE_CSR is changed. * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR according to the chosen version. Build a hash table riscv_csr_hash to store the valid CSR for the chosen pirv verison. Dump the direct CSR address rather than it's name if it is invalid. (parse_riscv_dis_option_without_args): New function. Parse the options without arguments. (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to parse the options without arguments first, and then handle the options with arguments. Add the new option -Mpriv-spec, which has argument. * riscv-dis.c (print_riscv_disassembler_options): Add description about the new OBJDUMP option. ld * testsuite/ld-riscv-elf/attr-merge-arch-01.d: Updated priv attributes according to the -mpriv-spec option. * testsuite/ld-riscv-elf/attr-merge-arch-02.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-03.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-priv-spec-a.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-priv-spec-b.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-priv-spec.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-stack-align.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-strict-align-01.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-strict-align-02.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-strict-align-03.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-strict-align-04.d: Likewise. * testsuite/ld-riscv-elf/attr-merge-strict-align-05.d: Likewise. bfd * elfxx-riscv.h (riscv_parse_subset_t): Add new callback function get_default_version. It is used to find the default version for the specific extension. * elfxx-riscv.c (riscv_parsing_subset_version): Remove the parameters default_major_version and default_minor_version. Add new bfd_boolean parameter use_default_version. Set it to TRUE if we need to call the callback rps->get_default_version to find the default version. (riscv_parse_std_ext): Call rps->get_default_version if we fail to find the default version in riscv_parsing_subset_version, and then call riscv_add_subset to add the subset into subset list. (riscv_parse_prefixed_ext): Likewise. (riscv_std_z_ext_strtab): Support Zicsr extensions. elfnn-riscv.c (riscv_merge_std_ext): Use strcasecmp to compare the strings rather than characters. riscv_merge_arch_attr_info): The callback function get_default_version is only needed for assembler, so set it to NULL int the linker. * elfxx-riscv.c (riscv_estimate_digit): Remove the static. * elfxx-riscv.h: Updated. gas * testsuite/gas/riscv/priv-reg-fail-read-only-01.s: Updated. * config/tc-riscv.c (default_arch_with_ext, default_isa_spec): Static variables which are used to set the ISA extensions. You can use -march (or ELF build attributes) and -misa-spec to set them, respectively. (ext_version_hash): The hash table used to handle the extensions with versions. (init_ext_version_hash): Initialize the ext_version_hash according to riscv_ext_version_table. (riscv_get_default_ext_version): The callback function of riscv_parse_subset_t. According to the choosed ISA spec, get the default version for the specific extension. (riscv_set_arch): Set the callback function. (enum options, struct option md_longopts): Add new option -misa-spec. (md_parse_option): Do not call riscv_set_arch for -march. We will call it later in riscv_after_parse_args. Call riscv_get_isa_spec_class to set default_isa_spec class. (riscv_after_parse_args): Call init_ext_version_hash to initialize the ext_version_hash, and then call riscv_set_arch to set the architecture with versions according to default_arch_with_ext. * testsuite/gas/riscv/attribute-02.d: Set 0p0 as default version for x extensions. * testsuite/gas/riscv/attribute-03.d: Likewise. * testsuite/gas/riscv/attribute-09.d: New testcase. For i-ext, we already set it's version to 2p1 by march, so no need to use the default 2p2 version. For m-ext, we do not set the version by -march and ELF arch attribute, so set the default 2p0 to it. For zicsr, it is not defined in ISA spec 2p2, so set 0p0 to it. * testsuite/gas/riscv/attribute-10.d: New testcase. The version of zicsr is 2p0 according to ISA spec 20191213. * config/tc-riscv.c (DEFAULT_RISCV_ARCH_WITH_EXT) (DEFAULT_RISCV_ISA_SPEC): Default configure option settings. You can set them by configure options --with-arch and --with-isa-spec, respectively. (riscv_set_default_isa_spec): New function used to set the default ISA spec. (md_parse_option): Call riscv_set_default_isa_spec rather than call riscv_get_isa_spec_class directly. (riscv_after_parse_args): If the -isa-spec is not set, then we set the default ISA spec according to DEFAULT_RISCV_ISA_SPEC by calling riscv_set_default_isa_spec. * testsuite/gas/riscv/attribute-01.d: Add -misa-spec=2.2, since the --with-isa-spec may be set to different ISA spec. * testsuite/gas/riscv/attribute-02.d: Likewise. * testsuite/gas/riscv/attribute-03.d: Likewise. * testsuite/gas/riscv/attribute-04.d: Likewise. * testsuite/gas/riscv/attribute-05.d: Likewise. * testsuite/gas/riscv/attribute-06.d: Likewise. * testsuite/gas/riscv/attribute-07.d: Likewise. * configure.ac: Add configure options, --with-arch and --with-isa-spec. * configure: Regenerated. * config.in: Regenerated. * config/tc-riscv.c (default_priv_spec): Static variable which is used to check if the CSR is valid for the chosen privilege spec. You can use -mpriv-spec to set it. (enum reg_class): We now get the CSR address from csr_extra_hash rather than reg_names_hash. Therefore, move RCLASS_CSR behind RCLASS_MAX. (riscv_init_csr_hashes): Only need to initialize one hash table csr_extra_hash. (riscv_csr_class_check): Change the return type to void. Don't check the ISA dependency if -mcsr-check isn't set. (riscv_csr_version_check): New function. Check and find the CSR address from csr_extra_hash, according to default_priv_spec. Report warning for the invalid CSR if -mcsr-check is set. (reg_csr_lookup_internal): Updated. (reg_lookup_internal): Likewise. (md_begin): Updated since DECLARE_CSR and DECLARE_CSR_ALIAS are changed. (enum options, struct option md_longopts): Add new GAS option -mpriv-spec. (md_parse_option): Call riscv_set_default_priv_version to set default_priv_spec. (riscv_after_parse_args): If -mpriv-spec isn't set, then set the default privilege spec to the newest one. (enum riscv_csr_class, struct riscv_csr_extra): Move them to include/opcode/riscv.h. * testsuite/gas/riscv/priv-reg-fail-fext.d: This test case just want to check the ISA dependency for CSR, so fix the spec version by adding -mpriv-spec=1.11. * testsuite/gas/riscv/priv-reg-fail-fext.l: Likewise. There are some version warnings for the test case. * gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.d: Likewise. * gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.l: Likewise. * gas/testsuite/gas/riscv/priv-reg-fail-read-only-02.d: Likewise. * gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.d: Likewise. * gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.l: Likewise. * gas/testsuite/gas/riscv/priv-reg-fail-version-1p9.d: New test case. Check whether the CSR is valid when privilege version 1.9 is choosed. * gas/testsuite/gas/riscv/priv-reg-fail-version-1p9.l: Likewise. * gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d: New test case. Check whether the CSR is valid when privilege version 1.9.1 is choosed. * gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.l: Likewise. * gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.d: New test case. Check whether the CSR is valid when privilege version 1.10 is choosed. * gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.l: Likewise. * gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.d: New test case. Check whether the CSR is valid when privilege version 1.11 is choosed. * gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.l: Likewise. * config/tc-riscv.c (DEFAULT_RISCV_ISA_SPEC): Default configure option setting. You can set it by configure option --with-priv-spec. (riscv_set_default_priv_spec): New function used to set the default privilege spec. (md_parse_option): Call riscv_set_default_priv_spec rather than call riscv_get_priv_spec_class directly. (riscv_after_parse_args): If -mpriv-spec isn't set, then we set the default privilege spec according to DEFAULT_RISCV_PRIV_SPEC by calling riscv_set_default_priv_spec. * testsuite/gas/riscv/csr-dw-regnums.d: Add -mpriv-spec=1.11, since the --with-priv-spec may be set to different privilege spec. * testsuite/gas/riscv/priv-reg.d: Likewise. * configure.ac: Add configure option --with-priv-spec. * configure: Regenerated. * config.in: Regenerated. * config/tc-riscv.c (explicit_attr): Rename explicit_arch_attr to explicit_attr. Set it to TRUE if any ELF attribute is found. (riscv_set_default_priv_spec): Try to set the default_priv_spec if the priv attributes are set. (md_assemble): Set the default_priv_spec according to the priv attributes when we start to assemble instruction. (riscv_write_out_attrs): Rename riscv_write_out_arch_attr to riscv_write_out_attrs. Update the arch and priv attributes. If we don't set the corresponding ELF attributes, then try to output the default ones. (riscv_set_public_attributes): If any ELF attribute or -march-attr options is set (explicit_attr is TRUE), then call riscv_write_out_attrs to update the arch and priv attributes. (s_riscv_attribute): Make sure all arch and priv attributes are set before any instruction. * testsuite/gas/riscv/attribute-01.d: Update the priv attributes if any ELF attribute or -march-attr is set. If the priv attributes are not set, then try to update them by the default setting (-mpriv-spec or --with-priv-spec). * testsuite/gas/riscv/attribute-02.d: Likewise. * testsuite/gas/riscv/attribute-03.d: Likewise. * testsuite/gas/riscv/attribute-04.d: Likewise. * testsuite/gas/riscv/attribute-06.d: Likewise. * testsuite/gas/riscv/attribute-07.d: Likewise. * testsuite/gas/riscv/attribute-08.d: Likewise. * testsuite/gas/riscv/attribute-09.d: Likewise. * testsuite/gas/riscv/attribute-10.d: Likewise. * testsuite/gas/riscv/attribute-unknown.d: Likewise. * testsuite/gas/riscv/attribute-05.d: Likewise. Also, the priv spec set by priv attributes must be supported. * testsuite/gas/riscv/attribute-05.s: Likewise. * testsuite/gas/riscv/priv-reg-fail-version-1p9.d: Likewise. Updated priv attributes according to the -mpriv-spec option. * testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d: Likewise. * testsuite/gas/riscv/priv-reg-fail-version-1p10.d: Likewise. * testsuite/gas/riscv/priv-reg-fail-version-1p11.d: Likewise. * testsuite/gas/riscv/priv-reg.d: Removed. * testsuite/gas/riscv/priv-reg-version-1p9.d: New test case. Dump the CSR according to the priv spec 1.9. * testsuite/gas/riscv/priv-reg-version-1p9p1.d: New test case. Dump the CSR according to the priv spec 1.9.1. * testsuite/gas/riscv/priv-reg-version-1p10.d: New test case. Dump the CSR according to the priv spec 1.10. * testsuite/gas/riscv/priv-reg-version-1p11.d: New test case. Dump the CSR according to the priv spec 1.11. * config/tc-riscv.c (md_show_usage): Add descriptions about the new GAS options. * doc/c-riscv.texi: Likewise.	6 years ago
Jim Wilson	fa16423949	RISC-V: Convert the ADD/ADDI to the compressed MV/LI if RS1 is zero. 2020-02-19 Nelson Chu <nelson.chu@sifive.com> gas/ * testsuite/gas/riscv/c-add-addi.d: New testcase. * testsuite/gas/riscv/c-add-addi.s: Likewise. opcodes/ * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed c.mv/c.li if rs1 is zero. Change-Id: Id939b5e6db80d267a832545f3ffef7b9ba881f7d	7 years ago
Alan Modra	b3adc24a07	Update year range in copyright notice of binutils files	7 years ago
Jim Wilson	7722d40a9c	RISC-V: Support the INSN_CLASS.F. classes for .insn directive. We have to enable the f extension through -march or ELF attribute if we use the FPR in .insn directive. The behavior is same as the riscv_opcodes. 2019-11-12 Nelson Chu <nelson.chu@sifive.com> opcodes/ * riscv-opc.c (riscv_insn_types): Replace the INSN_CLASS_I with INSN_CLASS_F and the INSN_CLASS_C with INSN_CLASS_F_AND_C if we use the floating point register (FPR). gas/ * testsuite/gas/riscv/insn.d: Add the f extension to -march option. Change-Id: I4f59d04c82673ef84c56ecd2659ad8ce164dd626	7 years ago
Jim Wilson	7e9ad3a35c	RISC-V: Gate opcode tables by enum rather than string. Generalize opcode arch dependencies so that we can support the overlapping B extension Zb* subsets. 2019-09-17 Maxim Blinov <maxim.blinov@embecosm.com> gas/ * config/tc-riscv.c (riscv_multi_subset_supports): Handle insn_class enum rather than subset char string. (riscv_ip): Update call to riscv_multi_subset_supports. include/ * opcode/riscv.h (riscv_insn_class): New enum. * opcode/riscv.h (struct riscv_opcode): Change subset field to insn_class field. opcodes/ * riscv-opc.c (riscv_opcodes): Change subset field to insn_class field for all instructions. (riscv_insn_types): Likewise.	7 years ago
Jim Wilson	c0d6f62fce	RISC-V: Fix minor issues with FP csr instructions. Mel Chen <mel.chen@sifive.com> gas/ * testsuite/gas/riscv/alias-csr.s: Add testcase for CSR-access alias instructions. * testsuite/gas/riscv/no-aliases-csr.d: Run testcase alias-csr.s with -Mno-aliases. * testsuite/gas/riscv/alias-csr.d: Run testcase alias-csr.s. * testsuite/gas/riscv/priv-reg.d: Update. opcodes/ * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm, fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions. * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr, fscsr.	7 years ago
Jim Wilson	98602811d8	Kito's 5-part patch set to improve .insn support. From Kito Cheng <kito.cheng@sifive.com> gas/ChangeLog * doc/c-riscv.texi (Instruction Formats): Add r4 type. * testsuite/gas/riscv/insn.d: Add testcase for r4 type. * testsuite/gas/riscv/insn.s: Ditto. * doc/c-riscv.texi (Instruction Formats): Add b and j type. * testsuite/gas/riscv/insn.d: Add test case for b and j type. * testsuite/gas/riscv/insn.s: Ditto. * testsuite/gas/riscv/insn.s: Correct instruction type for load and store. * testsuite/gas/riscv/insn.d: Using regular expression to match address. * doc/c-riscv.texi (Instruction Formats): Fix encoding table for SB type and fix typo. opcode/ChangeLog * riscv-opc.c (riscv_insn_types): Add r4 type. * riscv-opc.c (riscv_insn_types): Add b and j type. * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect format for sb type and correct s type.	7 years ago
Jim Wilson	ca0bc15098	RISC-V: Compress 3-operand beq/bne against x0. This lets us accept an instruction like beq a2,x0,.Label and generate a compressed beqz. This will allow some future simplications to the gcc support, e.g. eliminating some duplicate patterns, and avoiding adding new duplicate patterns, since currently we have to handle signed and equality compares against zero specially. Tested with rv{32,64}-{elf,linux} cross builds and make checks for binutils and gcc. There were no regressions. gas/ * config/tc-riscv.c (validate_riscv_insn) <'C'>: Add 'z' support. (riscv_ip) <'C'>: Add 'z' support. opcodes/ * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form. <bne>: Likewise.	8 years ago
Alan Modra	827041555a	Update year range in copyright notice of binutils files	8 years ago
Jim Wilson	f50fabe4f6	RISC-V: Fix 4-arg add parsing. PR gas/23956 gas/ * config/tc-riscv.c (validate_riscv_insn) <'1'>: New case. (percent_op_null): New. (riscv_ip) <'j'>: Set imm_reloc before p. <'1'>: New case. <'0'>: Use percent_op_null and don't set imm_reloc. <alu_op>: Handle args == '1'. testsuite/gas/riscv/tprel-add.d: New. * testsuite/gas/riscv/tprel-add.l: New. * testsuite/gas/riscv/tprel-add.s: New. opcodes/ * riscv-opc.c (riscv_opcodes) <"add">: Use 1 not 0 for fourth arg.	8 years ago
Jim Wilson	12951a2f08	RISC-V: Add missing c.unimp instruction. opcodes/ * riscv-opc.c (unimp): Mark compressed unimp as INSN_ALIAS. (c.unimp): New.	8 years ago
Jim Wilson	4765cd6119	RISC-V: Add .insn CA support. gas/ * config/tc-riscv.c (validate_riscv_insn) <'F'>: Add support for CF6 and CF2 operands. (riscv_ip) <'F'>: Likewise. * doc/c-riscv.texi (RISC-V-Formats): Add func6 abbreviation. Use rs2 instead of rs1 in CR description. Add CA docs. * gas/testsuite/riscv/insn.s: Add use of .insn ca. * gas/testsuite/riscv/insn.d: Update to match. include/ * opcode/riscv.h (OP_MASK_CFUNCT6, OP_SH_CFUNCT6): New. (OP_MASK_CFUNCT2, OP_SH_CFUNCT2): New. opcodes/ * riscv-opc.c (ciw): Fix whitespace to align columns. (ca): New.	8 years ago
Palmer Dabbelt	64a336ac13	RISC-V: Add fence.tso instruction The RISC-V memory model has been ratified, and it includes an additional fence: "fence.tso". This pseudo instruction extends one of the previously reserved full fence patterns to be less restrictive, and therefor will execute correctly on all existing microarchitectures. Thus there is no reason to allow this instruction to be disabled (or unconverted to a full fence), so it's just unconditionally allowed. I've added a test case for GAS to check that "fence.tso" correctly assembles on rv32i-based targets. I checked to see that "fence.tso" appears in "gas.log", but that's the only testing I've done. gas/ChangeLog 2018-10-02 Palmer Dabbelt <palmer@sifive.com> * testsuite/gas/riscv/fence-tso.d: New file. * testsuite/gas/riscv/fence-tso.s: Likewise. include/ChangeLog 2018-10-02 Palmer Dabbelt <palmer@sifive.com> * opcode/riscv-opc.h (MATCH_FENCE_TSO): New define. (MASK_FENCE_TSO): Likewise. opcodes/ChangeLog 2018-10-02 Palmer Dabbelt <palmer@sifive.com> * riscv-opc.c (riscv_opcodes) <fence.tso>: New opcode.	8 years ago
Jim Wilson	4e2b18982a	RISC-V: bge[u] should get higher priority than ble[u]. 2018-09-17 Kito Cheng <kito@andestech.com> gas/ * testsuite/gas/riscv/bge.d: New. * testsuite/gas/riscv/bge.s: Likewise. opcodes/ * riscv-opc.c (riscv_opcodes): Adjust the order of ble and bleu.	8 years ago
Jim Wilson	be192bc284	RISC-V: Correct the requirement of compressed floating point instructions 2018-08-31 Kito Cheng <kito@andestech.com> gas/ * testsuite/gas/riscv/c-fld-fsd-fail.d: New. * testsuite/gas/riscv/c-fld-fsd-fail.l: Likewise. * testsuite/gas/riscv/c-fld-fsd-fail.s: Likewise. opcodes/ * riscv-opc.c (riscv_opcodes): Fix incorrect subset info for compressed floating point instructions.	8 years ago
Jim Wilson	43135d3b15	RISC-V: Allow instruction require more than one extension 2018-08-29 Kito Cheng <kito@andestech.com> gas/ * config/tc-riscv.c (riscv_subset_supports): New argument: xlen_required. (riscv_multi_subset_supports): New function, able to check more than one extension. (riscv_ip): Use riscv_multi_subset_supports instead of riscv_subset_supports. (riscv_set_arch): Update call-site for riscv_subset_supports. (riscv_after_parse_args): Likewise. include/ opcode/riscv.h (MAX_SUBSET_NUM): New. (riscv_opcode): Add xlen_requirement field and change type of subset. opcodes/ riscv-dis.c (riscv_disassemble_insn): Check XLEN by riscv_opcode.xlen_requirement. * riscv-opc.c (riscv_opcodes): Update for struct change.	8 years ago
Jim Wilson	eb41b24898	RISC-V: Set insn info fields correctly when disassembling. include/ * opcode/riscv.h (INSN_TYPE, INSN_BRANCH, INSN_CONDBRANCH, INSN_JSR) (INSN_DREF, INSN_DATA_SIZE, INSN_DATA_SIZE_SHIFT, INSN_1_BYTE) (INSN_2_BYTE, INSN_4_BYTE, INSN_8_BYTE, INSN_16_BYTE): New. opcodes/ * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size fields. * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.	8 years ago
Sebastian Huber	160d1b3d74	RISC-V: Accept constant operands in la and lla opcodes/ PR gas/23305 * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for la and lla. gas/ PR gas/23305 * config/tc-riscv.c (riscv_ip): Add format specifier 'B' for constants and symbols. * testsuite/gas/riscv/lla32.d: New file. * testsuite/gas/riscv/lla32.s: Likewise. * testsuite/gas/riscv/lla64-fail.d: Likewise. * testsuite/gas/riscv/lla64-fail.l: Likewise. * testsuite/gas/riscv/lla64-fail.s: Likewise. * testsuite/gas/riscv/lla64.d: Likewise. * testsuite/gas/riscv/lla64.s: Likewise.	8 years ago
Jim Wilson	e6f372ba66	RISC-V: Add missing hint instructions from RV128I. gas/ * testsuite/gas/riscv/c-zero-imm.d: Add more tests. * testsuite/gas/riscv/c-zero-imm.s: Likewise. * testsuite/gas/riscv/c-zero-reg.d: Fix typo in test. Add disabled future test for RV128 support. * testsuite/gas/riscv/c-zero-reg.s: Likewise. include/ * opcode/riscv-opc.h (MATCH_C_SRLI64, MASK_C_SRLI64): New. (MATCH_C_SRAI64, MASK_C_SRAI64): New. (MATCH_C_SLLI64, MASK_C_SLLI64): New. opcodes/ * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New. (match_c_slli64, match_srxi_as_c_srxi): New. (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli. <srli, srl, srai, sra>: Use match_srxi_as_c_srxi. <c.slli, c.srli, c.srai>: Use match_s_slli. <c.slli64, c.srli64, c.srai64>: New.	8 years ago
Jim Wilson	0e35537d75	RISC-V: Add .insn support. gas/ChangeLog 2018-03-07 Kito Cheng <kito.cheng@gmail.com> * config/tc-riscv.c (opcode_name_list): New. (opcode_names_hash): Likewise. (init_opcode_names_hash): Likewise. (opcode_name_lookup): Likewise. (validate_riscv_insn): New argument length, and add new format which used in .insn directive. (md_begin): Refine hash table initialization logic into init_opcode_hash. (init_opcode_hash): New. (my_getOpcodeExpression): Parse opcode name for .insn. (riscv_ip): New argument hash, able to handle .insn directive. (s_riscv_insn): Handler for .insn directive. (riscv_pseudo_table): New entry for .insn. * doc/c-riscv.texi: Add documentation for .insn directive. * testsuite/gas/riscv/insn.d: Add testcase for .insn directive. * testsuite/gas/riscv/insn.s: Likewise. include/ChangeLog 2018-03-07 Kito Cheng <kito.cheng@gmail.com> * opcode/riscv.h (OP_MASK_FUNCT3): New. (OP_SH_FUNCT3): Likewise. (OP_MASK_FUNCT7): Likewise. (OP_SH_FUNCT7): Likewise. (OP_MASK_OP2): Likewise. (OP_SH_OP2): Likewise. (OP_MASK_CFUNCT4): Likewise. (OP_SH_CFUNCT4): Likewise. (OP_MASK_CFUNCT3): Likewise. (OP_SH_CFUNCT3): Likewise. (riscv_insn_types): Likewise. opcodes/ChangeLog 2018-03-07 Kito Cheng <kito.cheng@gmail.com> * riscv-opc.c (riscv_insn_types): New.	9 years ago

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72 Commits (41d6ac5da655a2e78109848f2db47e53552fd61a)