binutils-gdb

Tree: 3fcb85483c

Author	SHA1	Message	Date
Stan Shebs	c906108c21	Initial creation of sourceware repository	28 years ago
Stan Shebs	071ea11e85	Initial creation of sourceware repository	28 years ago
Frank Ch. Eigler	cc9bc93202	* Updates to tx3904 peripheral simulations for ECC. Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com> * dv-tx3904cpu.c (deliver__interrupt,_port_event): Set the CAUSE register upon non-zero interrupt event level, clear upon zero event value. * dv-tx3904irc.c (_port_event): Handle deactivated interrupt signal by passing zero event value. (_io_{read,write}_buffer): Endianness fixes. * dv-tx3904tmr.c (_io_{read,write}_buffer): Endianness fixes. (deliver__tick): Reduce sim event interval to 75% of count interval. * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based serial I/O and timer module at base address 0xFFFF0000.	29 years ago
Frank Ch. Eigler	da040f2a6c	* Early check-in of tx3904 timer sim implementation for ECC. It is not yet properly tested. Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com> * dv-tx3904tmr.c: New file - implements tx3904 timer. * dv-tx3904{irc,cpu}.c: Mild reformatting. * configure.in: Include tx3904tmr in hw_device list. * configure: Rebuilt. * interp.c (sim_open): Instantiate three timer instances. Fix address typo of tx3904irc instance.	29 years ago
Frank Ch. Eigler	3fa454e95f	* Monster patch - may destablize MIPS sims for a little while. * Followup patch for SCEI PR 15853 * First check-in of TX3904 interrupt controller devices for ECC. [sanitized] * First implementation of MIPS hardware interrupt emulation. Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com> * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware modules. Recognize TX39 target with "mipstx39" pattern. configure: Rebuilt. * sim-main.h (): Added many macros defining bits in TX39 control registers. (SignalInterrupt): Send actual PC instead of NULL. (SignalNMIReset): New exception type. interp.c (board): New variable for future use to identify a particular board being simulated. (mips_option_handler,mips_options): Added "--board" option. (interrupt_event): Send actual PC. (sim_open): Make memory layout conditional on board setting. (signal_exception): Initial implementation of hardware interrupt handling. Accept another break instruction variant for simulator exit. (decode_coproc): Implement RFE instruction for TX39. (mips.igen): Decode RFE instruction as such. start-sanitize-tx3904 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904. * interp.c: Define "jmr3904" and "jmr3904debug" board types and bbegin to implement memory map. * dv-tx3904cpu.c: New file. * dv-tx3904irc.c: New file. end-sanitize-tx3904	29 years ago

5 Commits (3fcb85483c84be99135979216566fdb1dc1e2ae2)