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add-fakeroots-dir
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gdb-9-branch
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gdb-csl-available-20060303-branch
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gdb-premipsmulti-2000-06-06-branch
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users/aburgess/try-mips-disasm-styling
users/ahajkova/try-frob
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added-to-binutils
arc-20081103-branchpoint
arc-insight_6_8-branchpoint
arc-sim-20090309
binu_ss_19990502
binu_ss_19990602
binu_ss_19990721
binutils-2_10
binutils-2_10-branchpoint
binutils-2_10_1
binutils-2_11
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binutils-2_12
binutils-2_12-branchpoint
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binutils-2_35_1
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binutils-2_36_1
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1 Commits (3ad6c19423eedf84dfd5ea83bc03933dff8a4579)
| Author | SHA1 | Message | Date |
|---|---|---|---|
Stafford Horne
|
fa8b7c2128 |
sim: or1k: add or1k target to sim
This adds the OpenRISC 32-bit sim target. The OpenRISC sim is a CGEN based sim so the bulk of the code is generated from the .cpu files by CGEN. The engine decode and execute logic in mloop uses scache with pseudo-basic-block extraction and supports both full and fast (switch) modes. The sim does not implement an mmu at the moment. The sim does implement fpu instructions via the common sim-fpu implementation. sim/ChangeLog: 2017-12-12 Stafford Horne <shorne@gmail.com> Peter Gavin <pgavin@gmail.com> * configure.tgt: Add or1k sim. * or1k/README: New file. * or1k/Makefile.in: New file. * or1k/configure.ac: New file. * or1k/mloop.in: New file. * or1k/or1k-sim.h: New file. * or1k/or1k.c: New file. * or1k/sim-if.c: New file. * or1k/sim-main.h: New file. * or1k/traps.c: New file. |
8 years ago |