* cpustate.h: Include config.h.
(union GRegisterValue): Add WORDS_BIGENDIAN check. For big endian code
use anonymous structs to align members.
* simulator.c (aarch64_step): Use sim_core_read_buffer and
endian_le2h_4 to read instruction from pc.
sim/sh/
* interp.c (dmul): Split into dmul_s and dmul_u. Use explicit integer
width types and simplify implementation.
* gencode.c (dmuls.l, dmulu.l): Use new functions dmul_s and dmul_u.
PR 19872
bfd * dwarf2.c (parse_comp_unit): Skip warning about unrecognised
version number if the version is zero.
bin * dwarf.c (display_debug_aranges): Skip warning about unrecognised
version number if the version is zero.
* cpustate.c (aarch64_set_reg_s32): New function.
(aarch64_set_reg_u32): New function.
(aarch64_get_FP_half): Place half precision value into the correct
slot of the union.
(aarch64_set_FP_half): Likewise.
* cpustate.h: Add prototypes for aarch64_set_reg_s32 and
aarch64_set_reg_u32.
* memory.c (FETCH_FUNC): Cast the read value to the access type
before converting it to the return type. Rename to FETCH_FUNC64.
(FETCH_FUNC32): New macro. Duplicates FETCH_FUNC64 but for 32-bit
accesses. Use for 32-bit memory access functions.
* simulator.c (ldrsb_wb): Use sign extension not zero extension.
(ldrb_scale_ext, ldrsh32_abs, ldrsh32_wb): Likewise.
(ldrsh32_scale_ext, ldrsh_abs, ldrsh64_wb): Likewise.
(ldrsh_scale_ext, ldrsw_abs): Likewise.
(ldrh32_abs): Store 32 bit value not 64-bits.
(ldrh32_wb, ldrh32_scale_ext): Likewise.
(do_vec_MOV_immediate): Fix computation of val.
(do_vec_MVNI): Likewise.
(DO_VEC_WIDENING_MUL): New macro.
(do_vec_mull): Use new macro.
(do_vec_mul): Use new macro.
(do_vec_MLA): Read values before writing.
(do_vec_xtl): Likewise.
(do_vec_SSHL): Select correct shift value.
(do_vec_USHL): Likewise.
(do_scalar_UCVTF): New function.
(do_scalar_vec): Call new function.
(store_pair_u64): Treat reads of SP as reads of XZR.
* cpustate.c: Remove space after asterisk in function parameters.
* decode.h (greg): Delete unused function.
(vreg, shift, extension, scaling, writeback, condcode): Likewise.
* simulator.c: Use INSTR macro in more places.
(HALT_NYI): Use sim_io_eprintf in place of fprintf.
Remove extraneous whitespace.
* cpustate.c (aarch64_get_FP_half): New function. Read a vector
register as a half precision floating point number.
(aarch64_set_FP_half): New function. Similar, but for setting
a half precision register.
(aarch64_get_thread_id): New function. Returns the value of the
CPU's TPIDR register.
(aarch64_get_FPCR): New function. Returns the value of the CPU's
floating point control register.
(aarch64_set_FPCR): New function. Set the value of the CPU's FPCR
register.
* cpustate.h: Add prototypes for new functions.
* sim-main.h (struct _sim_cpu): Add FPCR and tpidr fields.
* memory.c: Use unaligned core access functions for all memory
reads and writes.
* simulator.c (HALT_NYI): Generate an error message if tracing
will not tell the user why the simulator is halting.
(HALT_UNREACHABLE): Delete. Delete (unneeded) uses of the macro.
(INSTR): New time-saver macro.
(fldrb_abs): New function. Loads an 8-bit value using a scaled
offset.
(fldrh_abs): New function. Likewise for 16-bit values.
(do_vec_SSHL): Allow for negative shift values.
(do_vec_USHL): Likewise.
(do_vec_SHL): Correct computation of shift amount.
(do_vec_SSHR_USHR): Correct decision of signed vs unsigned
shifts and computation of shift value.
(clz): New function. Counts leading zero bits.
(do_vec_CLZ): New function. Implements CLZ (vector).
(do_vec_MOV_element): Call do_vec_CLZ.
(dexSimpleFPCondCompare): Implement.
(do_FCVT_half_to_single): New function. Implements one of the
FCVT operations.
(do_FCVT_half_to_double): New function. Likewise.
(do_FCVT_single_to_half): New function. Likewise.
(do_FCVT_double_to_half): New function. Likewise.
(dexSimpleFPDataProc1Source): Call new FCVT functions.
(do_scalar_SHL): Handle negative shifts.
(do_scalar_shift): Handle SSHR.
(do_scalar_USHL): New function.
(do_double_add): Simplify to just performing a double precision
add operation. Move remaining code into...
(do_scalar_vec): ... New function.
(dexLoadUnsignedImmediate): Call new fldrb_abs and fldrh_abs
functions.
(system_get): Add support for TPIDR, CTR, FPCR, FPSR and CPSR
registers.
(system_set): New function.
(do_MSR_immediate): New function. Stub for now.
(do_MSR_reg): New function. Likewise. Partially implements MSR
instruction.
(do_SYS): New function. Stub for now,
(dexSystem): Call new functions.
* simulator.c (set_flags_for_sub32): Correct type of signbit.
(CondCompare): Swap interpretation of bit 30.
(DO_ADDP): Delete macro.
(do_vec_ADDP): Copy source registers before starting to update
destination register.
(do_vec_FADDP): Likewise.
(do_vec_load_store): Fix computation of sizeof_operation.
(rbit64): Fix type of constant.
(aarch64_step): When displaying insn value, display all 32 bits.
* cgen-scache.c (scache_option_handler): Prevent possible
undefined behaviour computing the size of the scache by using
unsigned integers instead of signed integers.
This fixes PR sim/19441. In the MIPS simulator the microMIPS
functions in micromips.igen were not predicated on the microMIPS
models. This was causing build issues for some target triples.
This patch sets all the microMIPS specific functions to only be built if
the micromips32, micromips64 or micromipsdsp models are used.
PR sim/19441
* micromips.igen (delayslot_micromips): Enable for `micromips32',
`micromips64' and `micromipsdsp' only.
(process_isa_mode): Enable for `micromips32' and `micromips64' only.
(do_micromips_jalr, do_micromips_jal): Likewise.
(compute_movep_src_reg): Likewise.
(compute_andi16_imm): Likewise.
(convert_fmt_micromips): Likewise.
(convert_fmt_micromips_cvt_d): Likewise.
(convert_fmt_micromips_cvt_s): Likewise.
(FMT_MICROMIPS): Likewise.
(FMT_MICROMIPS_CVT_D): Likewise.
(FMT_MICROMIPS_CVT_S): Likewise.
This patch makes a fair number of fixes in the various comments of
sim-fpu.c, mostly to either better conform to the GNU Coding Standards
(sentences start with a capital letter, end with a period), or to
fix spelling mistakes.
sim/common/ChangeLog:
* sim-fpu.c: Minor comment fixes throughout.
This patch just makes a copy of formatting changes to better conform
with the GNU Coding Style.
sim/common/ChangeLog:
* sim-fpu.c (print_bits): Minor reformatting (no code change).
(sim_fpu_map): Likewise.
The mips bfd will sign extend 32-bit addresses into 64-bit values,
so if the entry happens to be 0x80000000 or higher, it is turned to
0xffffffff80000000 which points to memory that doesn't exist.
This wasn't an issue until commit 26f8bf63bf
as all addresses were automatically truncated there in the translate
function to 32-bits. When we cleaned up that code, the full 64-bits
were checked leading to many test failures for mips-sde-elf targets
and such.
Rather than stuffing the command line with a bunch of -D flags, start
moving things to config.h which is managed by autoheader. This makes
the makefile a bit simpler and the build output tighter, and it makes
the migration to automake easier as there are fewer vars to juggle.
We'll want to move the other options out too, but it'll take more work.
This was imported from the ppc sim, but that was only used to control
a single file, and that is already governed by the hw models. There's
no need to have a sep configure option here, especially since none of
the other sims are using it. Even when the code is enabled, there's
no runtime overhead.
Currently ports have to call SIM_AC_OPTION_ENVIRONMENT explicitly in
order to make the configure flag available. There's no real reason
to not allow this flag for all ports, so move it to the common sim
macro. This way we get standard behavior across all ports too.
Currently ports have to call SIM_AC_OPTION_ASSERT explicitly in order
to make the configure flag available, which none of them do. There's
no real reason to not allow this flag for all ports, so move it to the
common sim macro. This way we get standard behavior across all ports.
We don't have alternative nltvals.def files, so always symlinking
the targ-vals.def file to it doesn't gain us anything. It does
make the build more complicated though and a pain to convert to
something newer (like automake). Drop the symlinking entirely.
In the future, we'll want to explode this file anyways into the
respective arch dirs so things can be selected dynamically at
runtime, so it's not like we'll be bringing this back.
No other port calls this macro directly, and mips has it hardcoded
to the default -- disabling smp. In the future we'll enable this
for all targets in common code, so tidy up the mips code now.
Currently ports have to call SIM_AC_OPTION_INLINE explicitly in order
to make the configure flag available. There's no real reason to not
allow this flag for all ports, so move it to the common sim macro.
This way we get standard behavior across all ports too.
These options were never exposed for most sims (just the ppc one),
and they are really only useful on 32-bit x86 systems. Considering
modern systems tend to be 64-bit x86_64 and how well modern compilers
are at optimizing code, these have outlived their usefulness.
No other sub directory provides such a configuration option, so
drop it from the sim dir as well. This cleans up a good bit of
code in the process.
If people want to use custom flags for just the sim, they can
still run configure+make by hand in the sim subdir and use the
normal CFLAGS settings.
Now that cconfig.h doesn't exist, there's no need to build in the common
subdir anymore. We leave the configure/Makefile files in there as there
is a helper for developers to generate the nltvals.def file. Once that
gets cleaned up in the future though, we can drop the build logic too.
The common subdir sets up a cconfig.h file to hold checks for the common
code. In practice, most files still end up using config.h instead which
just leads to confusion.
Merge all the configure checks that went into cconfig.h into SIM_AC_COMMON
so we can drop the cconfig.h file altogether. Now there is only a single
config.h file like normal.
Some targets have started to add support for calling the disassembler
automatically when executing code. Add support for that directly into
the trace core.
The cris sim hit a few failures after the recent getopt logic, and the
expected output showed a few ways we can improve things to better match
other utils.
The compiler/C library should produce reasonable code for htonl/ntohl,
and at least glibc tries pretty hard to always produce good code for
them. This logic only had support for 32-bit x86 systems anymore, and
it's unlikely people were even opting into this, so drop it all.
The compiler should produce reasonable code here in general, so punt the
various arch checks and bswap defines. This code will eventually go away
entirely when we convert it to the common memory code.
Jim Wilson
Nick Clifton
Oleg Endo
Mike Frysinger
Maciej W. Rozycki
Andrew Bennett
Joel Brobecker
Tristan Gingold