binutils-gdb

Commit Graph

Author	SHA1	Message	Date
Victor Do Nascimento	2f8890efc5	aarch64: rcpc3: Create implicit load/store size calc function The allowed immediate offsets in integer rcpc3 load store instructions are not encoded explicitly in the instruction itself, being rather implicitly equivalent to the amount of data loaded/stored by the instruction. This leads to the requirement that this quantity be calculated based on the number of registers involved in the transfer, either as data source or destination registers and their respective qualifiers. This is done via `calc_ldst_datasize (const aarch64_opnd_info *opnds)' implemented here, using a cumulative sum of qualifier sizes preceding the address operand in the OPNDS operand list argument.	2 years ago
Victor Do Nascimento	9e263f69a7	aarch64: rcpc3: Add +rcpc3 architectural feature support flag Indicating the presence of the Armv8.2-a feature adding further support for the Release Consistency Model, the `+rcpc3' architectural extension flag is added to the list of possible `-march' options in Binutils, together with the necessary macro for encoding rcpc3 instructions.	2 years ago
Andrew Carlotti	6344535387	aarch64: Refactor aarch64_sys_ins_reg_supported_p Add an aarch64_feature_set field to aarch64_sys_ins_reg, and use this for feature checks instead of testing against a list of operand codes.	2 years ago
Andrew Carlotti	9dd903dfbf	aarch64: Remove unused BTI feature bit OK for master?	2 years ago
Srinath Parvathaneni	b33f1bcd15	aarch64: Add SVE2.1 Contiguous load/store instructions. Hi, This patch add support for SVE2.1 instructions ld1q, ld2q, ld3q and ld4q, st1q, st2q, st3q and st4q. Regression testing for aarch64-none-elf target and found no regressions. Ok for binutils-master? Regards, Srinath.	2 years ago
Srinath Parvathaneni	39092c7a1f	aarch64: Add SVE2.1 dupq, eorqv and extq instructions. Hi, This patch add support for SVE2.1 instruction dupq, eorqv and extq. Regression testing for aarch64-none-elf target and found no regressions. Ok for binutils-master? Regards, Srinath.	2 years ago
Srinath Parvathaneni	88601c2d94	aarch64: Add support for FEAT_SVE2p1. Hi, This patch add support for FEAT_SVE2p1 (SVE2.1 Extension) feature along with +sve2p1 optional flag to enabe this feature. Also support for following SVE2p1 instructions is added addqv, andqv, smaxqv, sminqv, umaxqv, uminqv and uminqv. Regression testing for aarch64-none-elf target and found no regressions. Ok for binutils-master? Regards, Srinath.	2 years ago
Srinath Parvathaneni	89e06ec152	aarch64: Add support for FEAT_SME2p1 instructions. Hi, This patch add support for FEAT_SME2p1 and "movaz" instructions along with the optional flag +sme2p1. Following "movaz" instructions are add: Move and zero two ZA tile slices to vector registers. Move and zero four ZA tile slices to vector registers. Regression testing for aarch64-none-elf target and found no regressions. Ok for binutils-master? Regards, Srinath.	2 years ago
Srinath Parvathaneni	7e8d2d8757	aarch64: Add support for FEAT_B16B16 instructions. Hi, This patch add support for SVE2.1 and SME2.1 non-widening BFloat16 (FEAT_B16B16) instructions. Following instructions predicated, unpredicated and indexed variants are added in this patch. bfadd, bfclamp, bfmax bfmaxnm, bfmin,bfminnm, bfmla,bfmls,bfmul and bfsub. Regression testing for aarch64-none-elf target and found no regressions. Ok for binutils-master? Regards, Srinath.	2 years ago
Andrew Carlotti	43291582c0	aarch64: Add +xs flag for existing instructions Additionally, change FEAT_XS tlbi variants to be gated on "+xs" instead of "+d128". This is an incremental improvement; there are still some FEAT_XS tlbi variants that are gated incorrectly or missing entirely.	2 years ago
Andrew Carlotti	59255bf7d2	aarch64: Add +wfxt flag for existing instructions	2 years ago
Andrew Carlotti	368910707c	aarch64: Add +rcpc2 flag for existing instructions	2 years ago
Andrew Carlotti	227af30e49	aarch64: Add +jscvt flag for existing fjcvtzs instruction	2 years ago
Saurabh Jha	15f3b5baad	gas: aarch64: Add system registers for Debug and PMU extensions This patch adds support for the new AArch64 system registers that are part of the following extensions: * FEAT_DEBUGv8p9 * FEAT_PMUv3p9 * FEAT_PMUv3_SS * FEAT_PMUv3_ICNTR * FEAT_SEBEP	2 years ago
Nick Clifton	e2a2633945	Synchronize sourceware version of the libiberty sources with the master gcc versions. This brings in the following commits: commit c73cc6fe6207b2863afa31a3be8ad87b70d3df0a Author: Jakub Jelinek <jakub@redhat.com> Date: Tue Dec 5 23:32:19 2023 +0100 libiberty: Fix build with GCC < 7 Tobias reported on IRC that the linker fails to build with GCC 4.8.5. In configure I've tried to use everything actually used in the sha1.c x86 hw implementation, but unfortunately I forgot about implicit function declarations. GCC before 7 did have <cpuid.h> header and bit_SHA define and __get_cpuid function defined inline, but it didn't define __get_cpuid_count, which compiled fine (and the configure test is intentionally compile time only) due to implicit function declaration, but then failed to link when linking the linker, because __get_cpuid_count wasn't defined anywhere. The following patch fixes that by using what autoconf uses in AC_CHECK_DECL to make sure the functions are declared. commit 691858d279335eeeeed3afafdf872b1c5f8f4201 Author: Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE> Date: Tue Dec 5 11:04:06 2023 +0100 libiberty: Fix pex_unix_wait return type The recent warning patches broke Solaris bootstrap: /vol/gcc/src/hg/master/local/libiberty/pex-unix.c:326:3: error: initialization of 'pid_t ()(struct pex_obj , pid_t, int , struct pex_time , int, const char *, int )' {aka 'long int ()(struct pex_obj , long int, int , struct pex_time , int, const char *, int )'} from incompatible pointer type 'int ()(struct pex_obj , pid_t, int , struct pex_time , int, const char *, int )' {aka 'int ()(struct pex_obj , long int, int , struct pex_time , int, const char *, int )'} [-Wincompatible-pointer-types] 326 \| pex_unix_wait, \| ^~~~~~~~~~~~~ /vol/gcc/src/hg/master/local/libiberty/pex-unix.c:326:3: note: (near initialization for 'funcs.wait') While pex_funcs.wait expects a function returning pid_t, pex_unix_wait currently returns int. However, on Solaris pid_t is long for 32-bit, but int for 64-bit. This patches fixes this by having pex_unix_wait return pid_t as expected, and like every other variant already does. Bootstrapped without regressions on i386-pc-solaris2.11, sparc-sun-solaris2.11, x86_64-pc-linux-gnu, and x86_64-apple-darwin23.1.0. commit c3f281a0c1ca50e4df5049923aa2f5d1c3c39ff6 Author: Jason Merrill <jason@redhat.com> Date: Mon Sep 25 10:15:02 2023 +0100 c++: mangle function template constraints Per https://github.com/itanium-cxx-abi/cxx-abi/issues/24 and https://github.com/itanium-cxx-abi/cxx-abi/pull/166 We need to mangle constraints to be able to distinguish between function templates that only differ in constraints. From the latter link, we want to use the template parameter mangling previously specified for lambdas to also make explicit the form of a template parameter where the argument is not a "natural" fit for it, such as when the parameter is constrained or deduced. I'm concerned about how the latter link changes the mangling for some C++98 and C++11 patterns, so I've limited template_parm_natural_p to avoid two cases found by running the testsuite with -Wabi forced on: template <class T, T V> T f() { return V; } int main() { return f<int,42>(); } template <int i> int max() { return i; } template <int i, int j, int... rest> int max() { int sub = max<j, rest...>(); return i > sub ? i : sub; } int main() { return max<1,2,3>(); } A third C++11 pattern is changed by this patch: template <template <typename...> class TT, typename... Ts> TT<Ts...> f(); template <typename> struct A { }; int main() { f<A,int>(); } I aim to resolve these with the ABI committee before GCC 14.1. We also need to resolve https://github.com/itanium-cxx-abi/cxx-abi/issues/38 (mangling references to dependent template-ids where the name is fully resolved) as references to concepts in std:: will consistently run into this area. This is why mangle-concepts1.C only refers to concepts in the global namespace so far. The library changes are to avoid trying to mangle builtins, which fails. Demangler support and test coverage is not complete yet. commit f2c52c0dfde581461959b0e2b423ad106aadf179 Author: Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE> Date: Thu Nov 30 10:06:23 2023 +0100 libiberty: Disable hwcaps for sha1.o This patch commit bf4f40cc3195eb7b900bf5535cdba1ee51fdbb8e Author: Jakub Jelinek <jakub@redhat.com> Date: Tue Nov 28 13:14:05 2023 +0100 libiberty: Use x86 HW optimized sha1 broke Solaris/x86 bootstrap with the native as: libtool: compile: /var/gcc/regression/master/11.4-gcc/build/./gcc/gccgo -B/var/gcc/regression/master/11.4-gcc/build/./gcc/ -B/vol/gcc/i386-pc-solaris2.11/bin/ -B/vol/gcc/i386-pc-solaris2.11/lib/ -isystem /vol/gcc/i386-pc-solaris2.11/include -isystem /vol/gcc/i386-pc-solaris2.11/sys-include -fchecking=1 -minline-all-stringops -O2 -g -I . -c -fgo-pkgpath=internal/goarch /vol/gcc/src/hg/master/local/libgo/go/internal/goarch/goarch.go zgoarch.go ld.so.1: go1: fatal: /var/gcc/regression/master/11.4-gcc/build/gcc/go1: hardware capability (CA_SUNW_HW_2) unsupported: 0x4000000 [ SHA1 ] gccgo: fatal error: Killed signal terminated program go1 As is already done in a couple of other similar cases, this patches disables hwcaps support for libiberty. Initially, this didn't work because config/hwcaps.m4 uses target_os, but didn't ensure it is defined. Tested on i386-pc-solaris2.11 with as and gas. commit bf4f40cc3195eb7b900bf5535cdba1ee51fdbb8e Author: Jakub Jelinek <jakub@redhat.com> Date: Tue Nov 28 13:14:05 2023 +0100 libiberty: Use x86 HW optimized sha1 Nick has approved this patch (+ small ld change to use it for --build-id=), so I'm commiting it to GCC as master as well. If anyone from ARM would be willing to implement it similarly with vsha1{cq,mq,pq,h,su0q,su1q}_u32 intrinsics, it could be a useful linker speedup on those hosts as well, the intent in sha1.c was that sha1_hw_process_bytes, sha1_hw_process_block functions would be defined whenever defined (HAVE_X86_SHA1_HW_SUPPORT) \|\| defined (HAVE_WHATEVERELSE_SHA1_HW_SUPPORT) but the body of sha1_hw_process_block and sha1_choose_process_bytes would then have #elif defined (HAVE_WHATEVERELSE_SHA1_HW_SUPPORT) for the other arch support, similarly for any target attributes on sha1_hw_process_block if needed. commit 01bc30b222a9d2ff0269325d9e367f8f1fcef942 Author: Mark Wielaard <mjw@redhat.com> Date: Wed Nov 15 20:27:08 2023 +0100 Regenerate libiberty/aclocal.m4 with aclocal 1.15.1 There is a new buildbot check that all autotool files are generated with the correct versions (automake 1.15.1 and autoconf 2.69). https://builder.sourceware.org/buildbot/#/builders/gcc-autoregen Correct one file that was generated with the wrong version. commit 879cf9ff45d94065d89e24b71c6b27c7076ac518 Author: Brendan Shanks <bshanks@codeweavers.com> Date: Thu Nov 9 21:01:07 2023 -0700 [PATCH v3] libiberty: Use posix_spawn in pex-unix when available. Hi, This patch implements pex_unix_exec_child using posix_spawn when available. This should especially benefit recent macOS (where vfork just calls fork), but should have equivalent or faster performance on all platforms. In addition, the implementation is substantially simpler than the vfork+exec code path. Tested on x86_64-linux. v2: Fix error handling (previously the function would be run twice in case of error), and don't use a macro that changes control flow. v3: Match file style for error-handling blocks, don't close in/out/errdes on error, and check close() for errors. commit 810bcc00156cefce7ad40fc9d8de6e43c3a04450 Author: Jason Merrill <jason@redhat.com> Date: Thu Aug 17 11:36:23 2023 -0400 c++: constrained hidden friends [PR109751] r13-4035 avoided a problem with overloading of constrained hidden friends by checking satisfaction, but checking satisfaction early is inconsistent with the usual late checking and can lead to hard errors, so let's not do that after all. We were wrongly treating the different instantiations of the same friend template as the same function because maybe_substitute_reqs_for was failing to actually substitute in the case of a non-template friend. But we don't actually need to do the substitution anyway, because [temp.friend] says that such a friend can't be the same as any other declaration. After fixing that, instead of a redefinition error we got an ambiguous overload error, fixed by allowing constrained hidden friends to coexist until overload resolution, at which point they probably won't be in the same ADL overload set anyway. And we avoid mangling collisions by following the proposed mangling for these friends as a member function with an extra 'F' before the name. I demangle this by just adding [friend] to the name of the function because it's not feasible to reconstruct the actual scope of the function since the mangling ABI doesn't distinguish between class and namespace scopes. PR c++/109751	2 years ago
Srinath Parvathaneni	e318eb0930	aarch64: ADD FEAT_THE RCWCAS instructions. This patch adds support for FEAT_THE doubleword and quadword instructions. doubleword insturctions are enabled by "+the" flag whereas quadword instructions are enabled on passing both "+the and +d128" flags. Support for following sets of instructions is added in this patch. Read check write compare and swap doubleword: (rcwcas, rcwcasa, rcwcasal, rcwcasl) Read check write compare and swap quadword: (rcwcasp,rcwcaspa, rcwcaspal, rcwcaspl) Read check write software compare and swap doubleword: (rcwscas, rcwscasa, rcwscasal, rcwscasl) Read check write software compare and swap quadword: (rcwscasp, rcwscaspa, rcwscaspal, rcwscaspl) Read check write atomic bit clear on doubleword: (rcwclr, rcwclra, rcwclral, rcwclrl) Read check write atomic bit clear on quadword: (rcwclrp, rcwclrpa, rcwclrpal, rcwclrpl) Read check write software atomic bit clear on doubleword: (rcwsclr, rcwsclra, rcwsclral, rcwsclrl) Read check write software atomic bit clear on quadword: (rcwsclrp,rcwsclrpa, rcwsclrpal,rcwsclrpl) Read check write atomic bit set on doubleword: (rcwset,rcwseta, rcwsetal,rcwsetl) Read check write atomic bit set on quadword: (rcwsetp,rcwsetpa,rcwsetpal,rcwsetpl) Read check write software atomic bit set on doubleword: (rcwsset,rcwsseta,rcwssetal,rcwssetl) Read check write software atomic bit set on quadword: (rcwssetp,rcwssetpa,rcwssetpal,rcwssetpl) Read check write swap doubleword: (rcwswp,rcwswpa,rcwswpal,rcwswpl) Read check write swap quadword: (rcwswpp,rcwswppa, rcwswppal,rcwswppl) Read check write software swap doubleword: (rcwsswp,rcwsswpa,rcwsswpal,rcwsswpl) Read check write software swap quadword: (rcwsswpp,rcwsswppa,rcwsswppal,rcwsswppl)	2 years ago
Victor Do Nascimento	9af8f67118	aarch64: Add support for 128-bit system register mrrs and msrr insns With the addition of 128-bit system registers to the Arm architecture starting with Armv9.4-a, a mechanism for manipulating their contents is introduced with the `msrr' and `mrrs' instruction pair. These move values from one such 128-bit system register into a pair of contiguous general-purpose registers and vice-versa, as for example: msrr ttlb0_el1, x0, x1 mrrs x0, x1, ttlb0_el1 This patch adds the necessary support for these instructions, adding checks for system-register width by defining a new operand type in the form of `AARCH64_OPND_SYSREG128' and the `aarch64_sys_reg_128bit_p' predicate, responsible for checking whether the requested system register table entry is marked as implemented in the 128-bit mode via the F_REG_128 flag.	2 years ago
Victor Do Nascimento	a9e2cefdf0	aarch64: Implement TLBIP 128-bit instruction The addition of 128-bit page table descriptors and, with it, the addition of 128-bit system registers for these means that special "invalidate translation table entry" instructions are needed to cope with the new 128-bit model. This is introduced with the `tlbpi' instruction, implemented here.	2 years ago
Victor Do Nascimento	5517af8298	aarch64: Apply narrowing of allowed immediate values for SYSP While CRn and CRm fields in the SYSP instruction are 4-bit wide and are thus able to accommodate values in the range 0-15, the specifications for the SYSP instructions limit their ranges to 8-9 for CRm and 0-7 in the case of CRn. This led to the need to signal in some way to the operand parser that a given operand is under special restrictions regarding its use. This is done via the new `F_OPD_NARROW' flag, indicating a narrowing in the range of operand values for fields in the instruction tagged with the flag. The flag is then used in `parse_operands' when the instruction is assembled, but needs not be taken into consideration during disassembly.	2 years ago
Victor Do Nascimento	f89c290e23	aarch64: Add support for optional operand pairs Two of the instructions added by the `+d128' architectural extension add the flexibility to have two optional operands. Prior to the addition of the `tlbip' and `sysp' instructions, no mnemonic allowed more than one such optional operand. With `tlbip' as an example, some TLBIP instruction names do not allow for any optional operands, while others allow for both to be optional. In the latter case, it is possible that either the second operand alone is omitted or both operands are omitted. Therefore, a considerable degree of flexibility needed to be added to the way operands were parsed. It was, however, possible to achieve this with relatively few changes to existing code. it is noteworthy that opcode flags specifying the optional operand number are non-orthogonal. For example, we have: #define F_OPD1_OPT (2 << 12) : 0b10 << 12 #define F_OPD2_OPT (3 << 12) : 0b11 << 12 such that by virtue of the observation that (F_OPD1_OPT \| F_OPD2_OPT) == F_OPD2_OPT it is impossible to mark both operands 1 and 2 as optional for an instruction and it is assumed that a maximum of 1 operand can ever be optional. This is not overly-problematic given that, for optional pairs, the second optional operand is always found immediately after the first. Thus, it suffices for us to flag that there is a second optional operand. With this fact, we can infer its position in the mnemonic from the position of the first (e.g. if the second operand in the mnemonic is optional, we know the third is too). We therefore define the `F_OPD_PAIR_OPT' flag and calculate its position in the mnemonic from the value encoded by the `F_OPD<n>_OPT' flag. Another observation is that there is a tight coupling between default values assigned to the two registers when one (or both) are omitted from the mnemonic. Namely, if Xt1 has a value of 0x1f (the zero register is specified), Xt2 defaults to the same value, otherwise Xt2 will be assigned Xt + 1. This meant that where you have default value validation, in checking the second optional operand's value, it is also necessary to look at the value assigned to the previously-processed operand value before deciding its validity. Thus `process_omitted_operand' needs not only access to its `operand' argument, but also to the global `inst' struct.	2 years ago
Victor Do Nascimento	d30eb38d5b	aarch64: Add support for xzr register in register pair operands Analysis of the allowed operand values for `sysp' and `tlbip' reveals a significant departure from the allowed behavior for operand register pairs (hitherto labeled AARCH64_OPND_PAIRREG) observed for other insns in this category. For instructions `casp', `mrrs' and `msrr' the register pair must always start at an even index and the second register in the pair is the index + 1. This precludes the use of xzr as the first register, given it corresponds to register number 31. This is different in the case of `sysp' and `tlbip', however. These allow the use of xzr and, where the first operand in the pair is omitted, this is the default value assigned to it. When this operand is assigned xzr, it is expected that the second operand will likewise take on a value of xzr. These two instructions therefore "break" two rules of register pairs: * The first of the two registers is odd-numbered. * The index of the second register is equal to that of the first, and not n+1. To allow for this departure from hitherto standard behavior, we extend the functionality of the assembler by defining an extension of the AARCH64_OPND_PAIRREG, called AARCH64_OPND_PAIRREG_OR_XZR. It is used in defining `sysp' and `tlbip' and allows `operand_general_constraint_met_p' to allow the pair to both take on the value of xzr.	2 years ago
Victor Do Nascimento	2ec6065a4f	aarch64: Expand maximum number of operands from 5 to 6 Given the introduction of the new Armv9.4-a `sysp' insn using the following syntax: sysp #<op1>, <Cn>, <Cm>, #<op2>{, <Xt1>, <Xt2>} and by extension the need to encode 6 assembly operands, extend Binutils to handle instructions taking 6 operands, up from a previous maximum of 5.	2 years ago
Victor Do Nascimento	7b08cc3216	aarch64: Add +d128 architectural feature support Indicating the presence of the Armv9.4-a features concerning 128-bit Page Table Descriptors, 128-bit System Registers and Instructions, the "+d128" architectural extension flag is added to the list of possible -march options in Binutils, together with the necessary macro for encoding d128 instructions.	2 years ago
srinath	b3b647dc7f	arm: Add support for Armv8.9-A and Armv9.4-A This patch adds AArch32 support for -march=armv8.9-a and -march=armv9.4-a. The behaviour of the new options can be expressed using a combination of existing feature flags and tables. The cpu_arch_ver entries for ARM_ARCH_V9_4A and ARM_ARCH_V8_9A are technically redundant but it including them for macro code consistency across architectures.	2 years ago
Jin Ma	6a95962e25	RISC-V: T-HEAD: Fix wrong instruction encoding for th.vsetvli Since the particularity of "th.vsetvli" was not taken into account in the initial support patches for XTheadVector, the program operation failed due to instruction coding errors. According to T-Head SPEC ([1]), the "vsetvl" in the XTheadVector extension consists of SEW, LMUL and EDIV, which is quite different from the "V" extension. Therefore, we cannot simply reuse the processing of vsetvl in V extension. We have set up tens of thousands of test cases to ensure that no further encoding issues are there, and and execute all compiled test files on real HW and make sure they don't trigger SIGILL. Ref: [1] https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.3.0/xthead-2023-11-10-2.3.0.pdf Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com> Co-developed-by: Christoph Müllner <christoph.muellner@vrull.eu> gas/ChangeLog: * config/tc-riscv.c (validate_riscv_insn): Add handling for th.vsetvli. (my_getThVsetvliExpression): New function. (riscv_ip): Likewise. * testsuite/gas/riscv/x-thead-vector.d: Likewise. * testsuite/gas/riscv/x-thead-vector.s: Likewise. include/ChangeLog: * opcode/riscv.h (OP_MASK_XTHEADVLMUL): New macro. (OP_SH_XTHEADVLMUL): Likewise. (OP_MASK_XTHEADVSEW): Likewise. (OP_SH_XTHEADVSEW): Likewise. (OP_MASK_XTHEADVEDIV): Likewise. (OP_SH_XTHEADVEDIV): Likewise. (OP_MASK_XTHEADVTYPE_RES): Likewise. (OP_SH_XTHEADVTYPE_RES): Likewise. opcodes/ChangeLog: * riscv-dis.c (print_insn_args): Likewise. * riscv-opc.c: Likewise.	2 years ago
Alan Modra	fd67aa1129	Update year range in copyright notice of binutils files Adds two new external authors to etc/update-copyright.py to cover bfd/ax_tls.m4, and adds gprofng to dirs handled automatically, then updates copyright messages as follows: 1) Update cgen/utils.scm emitted copyrights. 2) Run "etc/update-copyright.py --this-year" with an extra external author I haven't committed, 'Kalray SA.', to cover gas testsuite files (which should have their copyright message removed). 3) Build with --enable-maintainer-mode --enable-cgen-maint=yes. 4) Check out /po/.pot which we don't update frequently.	2 years ago
changjiachen	775dead218	LoongArch: include: Add support for tls le relax. Add new relocs number for tls le relax. include/ChangeLog: * elf/loongarch.h: (RELOC_NUMBER (R_LARCH_TLS_LE_HI20_R, 121)): New relocs number. (RELOC_NUMBER (R_LARCH_TLS_LE_ADD_R, 122)): Likewise. (RELOC_NUMBER (R_LARCH_TLS_LE_LO12_R, 123)): Likewise.	2 years ago
H.J. Lu	a533c8df59	x86-64: Add R_X86_64_CODE_4_GOTTPOFF/R_X86_64_CODE_4_GOTPC32_TLSDESC For add name@gottpoff(%rip), %reg mov name@gottpoff(%rip), %reg add # define R_X86_64_CODE_4_GOTTPOFF 44 and for lea name@tlsdesc(%rip), %reg add # define R_X86_64_CODE_4_GOTPC32_TLSDESC 45 if the instruction starts at 4 bytes before the relocation offset. They are similar to R_X86_64_GOTTPOFF and R_X86_64_GOTPC32_TLSDESC, respectively. Linker can covert GOTTPOFF to add $name@tpoff, %reg mov $name@tpoff, %reg and GOTPC32_TLSDESC to mov $name@tpoff, %reg mov name@gottpoff(%rip), %reg if the instruction is encoded with the REX2 prefix when possible. bfd/ * elf64-x86-64.c (x86_64_elf_howto_table): Add R_X86_64_CODE_4_GOTTPOFF and R_X86_64_CODE_4_GOTPC32_TLSDESC. (R_X86_64_standard): Updated. (x86_64_reloc_map): Add BFD_RELOC_X86_64_CODE_4_GOTTPOFF and BFD_RELOC_X86_64_CODE_4_GOTPC32_TLSDESC. (elf_x86_64_check_tls_transition): Handle R_X86_64_CODE_4_GOTTPOFF and R_X86_64_CODE_4_GOTPC32_TLSDESC. (elf_x86_64_tls_transition): Likewise. (elf_x86_64_scan_relocs): Likewise. (elf_x86_64_relocate_section): Likewise. * reloc.c (bfd_reloc_code_real): Add BFD_RELOC_X86_64_CODE_4_GOTTPOFF and BFD_RELOC_X86_64_CODE_4_GOTPC32_TLSDESC. * bfd-in2.h: Regenerated. * libbfd.h: Likewise. gas/ * config/tc-i386.c (tc_i386_fix_adjustable): Handle BFD_RELOC_X86_64_CODE_4_GOTTPOFF and BFD_RELOC_X86_64_CODE_4_GOTPC32_TLSDESC. (md_assemble): Handle BFD_RELOC_X86_64_CODE_4_GOTTPOFF. (output_insn): Don't add empty REX prefix with REX2 prefix. (output_disp): Handle BFD_RELOC_X86_64_CODE_4_GOTTPOFF and BFD_RELOC_X86_64_CODE_4_GOTPC32_TLSDESC. (md_apply_fix): Likewise. (i386_validate_fix): Generate BFD_RELOC_X86_64_CODE_4_GOTTPOFF or BFD_RELOC_X86_64_CODE_4_GOTPC32_TLSDESC if ixp->fx_tcbit3 is set. (tc_gen_reloc): Handle BFD_RELOC_X86_64_CODE_4_GOTTPOFF and BFD_RELOC_X86_64_CODE_4_GOTPC32_TLSDESC. * testsuite/gas/i386/x86-64-gottpoff.d: New file. * testsuite/gas/i386/x86-64-gottpoff.s: Likewise. * testsuite/gas/i386/x86-64-tlsdesc.d: Likewise. * testsuite/gas/i386/x86-64-tlsdesc.s: Likewise. include/ * elf/x86-64.h (elf_x86_64_reloc_type): Add R_X86_64_CODE_4_GOTTPOFF and R_X86_64_CODE_4_GOTPC32_TLSDESC ld/ * testsuite/ld-x86-64/tlsbindesc.d: Updated. * testsuite/ld-x86-64/tlsbindesc.rd: Likewise. * testsuite/ld-x86-64/tlsbindesc.s: Add R_X86_64_CODE_4_GOTTPOFF and R_X86_64_CODE_4_GOTPC32_TLSDESC tests.	3 years ago
H.J. Lu	3d5a60de52	x86-64: Add R_X86_64_CODE_4_GOTPCRELX For mov name@GOTPCREL(%rip), %reg test %reg, name@GOTPCREL(%rip) binop name@GOTPCREL(%rip), %reg where binop is one of adc, add, add, cmp, or, sbb, sub, xor instructions, add # define R_X86_64_CODE_4_GOTPCRELX 43 if the instruction starts at 4 bytes before the relocation offset. It similar to R_X86_64_GOTPCRELX. Linker can treat R_X86_64_CODE_4_GOTPCRELX as R_X86_64_GOTPCREL or convert the above instructions to lea name(%rip), %reg mov $name, %reg test $name, %reg binop $name, %reg if the instruction is encoded with the REX2 prefix when possible. bfd/ * elf64-x86-64.c (x86_64_elf_howto_table): Add R_X86_64_CODE_4_GOTPCRELX. (R_X86_64_standard): Updated. (x86_64_reloc_map): Add BFD_RELOC_X86_64_CODE_4_GOTPCRELX. (elf_x86_64_convert_load_reloc): Handle R_X86_64_CODE_4_GOTPCRELX. (elf_x86_64_scan_relocs): Likewise. (elf_x86_64_relocate_section): Likewise. * reloc.c (bfd_reloc_code_real): Add BFD_RELOC_X86_64_CODE_4_GOTPCRELX. * bfd-in2.h: Regenerated. * libbfd.h: Likewise. gas/ * write.h (fix): Add fx_tcbit3. Change fx_unused to 1 bit. * config/tc-i386.c (tc_i386_fix_adjustable): Handle BFD_RELOC_X86_64_CODE_4_GOTPCRELX. (tc_gen_reloc): Likewise. (output_disp): Set fixP->fx_tcbit3 for REX2 prefix. (i386_validate_fix): Generate BFD_RELOC_X86_64_CODE_4_GOTPCRELX if fixp->fx_tcbit3 is set. * config/tc-i386.h (TC_FORCE_RELOCATION_LOCAL): Add BFD_RELOC_X86_64_CODE_4_GOTPCRELX. (TC_FORCE_RELOCATION_ABS): Likewise. * testsuite/gas/i386/x86-64-gotpcrel.s: Add tests for R_X86_64_CODE_4_GOTPCRELX. * testsuite/gas/i386/x86-64-localpic.s: Likewise. * testsuite/gas/i386/x86-64-gotpcrel.d: Updated. * testsuite/gas/i386/x86-64-localpic.d: Likewise. * testsuite/gas/i386/ilp32/x86-64-localpic.d: Likewise. include/ * elf/x86-64.h (elf_x86_64_reloc_type): Add R_X86_64_CODE_4_GOTPCRELX. ld/ * testsuite/ld-x86-64/apx-load1.s: New file. * testsuite/ld-x86-64/apx-load1a.d: Likewise. * testsuite/ld-x86-64/apx-load1b.d: Likewise. * testsuite/ld-x86-64/apx-load1c.d: Likewise. * testsuite/ld-x86-64/apx-load1d.d: Likewise. * testsuite/ld-x86-64/x86-64.exp: Run apx-load1a, apx-load1b, apx-load1c and apx-load1d.	3 years ago
Schimpe, Christina	eccdc733a5	x86: Add NT_X86_SHSTK note Define NT_X86_SHSTK which is the note for x86 Shadow Stack (SHSTK) to support Intel SHSTK in Linux kernel. For now only userspace shadow stack and kernel IBT are supported by the linux kernel. This note should be used instead of NT_X86_CET introduced in the commit "x86: Add NT_X86_CET note", as it is outdated and only used by old binutils versions.	2 years ago
Cui, Lili	80d61d8d61	Support APX GPR32 with rex2 prefix APX uses the REX2 prefix to support EGPR for map0 and map1 of legacy instructions. We added the NoEgpr flag in i386-gen.c for instructions that do not support EGPR. gas/ChangeLog: 2023-12-28 Lingling Kong <lingling.kong@intel.com> H.J. Lu <hongjiu.lu@intel.com> Lili Cui <lili.cui@intel.com> Lin Hu <lin1.hu@intel.com> * config/tc-i386.c (enum i386_error): Add unsupported_EGPR_for_addressing and invalid_pseudo_prefix. (struct _i386_insn): Add rex2 and rex2_encoding for gpr32. (cpu_arch): Add apx_f. (is_cpu): Ditto. (register_number): Handle RegRex2 for gpr32. (is_apx_rex2_encoding): New func. Test rex2 prefix encoding. (build_rex2_prefix): New func. Build legacy insn in opcode 0/1 use gpr32 with rex2 prefix. (establish_rex): Handle rex2 and rex2_encoding. (optimize_encoding): Handel add r16-r31 for registers. (md_assemble): Handle apx encoding. (parse_insn): Handle Prefix_REX2. (check_EgprOperands): New func. Check if Egprs operands are valid for the instruction (match_template): Handle Egpr operands check. (set_rex_rex2): New func. set i.rex and i.rex2. (build_modrm_byte): Ditto. (output_insn): Handle rex2 2-byte prefix output. (check_register): Handle check egpr illegal without target apx, 64-bit mode and with rex_prefix. * doc/c-i386.texi: Document .apx. * testsuite/gas/i386/ilp32/x86-64-opcode-inval-intel.d: D5 valid in 64-bit mode. * testsuite/gas/i386/ilp32/x86-64-opcode-inval.d: Ditto. * testsuite/gas/i386/rex-bad: Adjust rex testcase. * testsuite/gas/i386/x86-64-opcode-inval-intel.d: Ditto. * testsuite/gas/i386/x86-64-opcode-inval.d: Ditto. * testsuite/gas/i386/x86-64-opcode-inval.s: Ditto. * testsuite/gas/i386/x86-64-pseudos-bad.l: Add illegal rex2 test. * testsuite/gas/i386/x86-64-pseudos-bad.s: Ditto. * testsuite/gas/i386/x86-64-pseudos.d: Add rex2 test. * testsuite/gas/i386/x86-64-pseudos.s: Ditto. * testsuite/gas/i386/x86-64.exp: Run APX tests. * testsuite/gas/i386/x86-64-apx-egpr-inval.l: New test. * testsuite/gas/i386/x86-64-apx-egpr-inval.s: New test. * testsuite/gas/i386/x86-64-apx-rex2.d: New test. * testsuite/gas/i386/x86-64-apx-rex2.s: New test. include/ChangeLog: * opcode/i386.h (REX2_OPCODE): New. (REX2_M): Ditto. opcodes/ChangeLog: * i386-dis.c (struct instr_info): Add erex for gpr32. Add last_erex_prefix for rex2 prefix. (REX2_M): Extend for gpr32. (PREFIX_REX2): Ditto. (PREFIX_REX2_ILLEGAL): Ditto. (ckprefix): Ditto. (prefix_name): Ditto. (print_insn): Ditto. (print_register): Ditto. (OP_E_memory): Ditto. (OP_REG): Ditto. (OP_EX): Ditto. * i386-gen.c (rex2_disallowed): Some instructions are not allowed rex2 prefix. (process_i386_opcode_modifier): Set NoEgpr for VEX and some special instructions. (output_i386_opcode): Handle if_entry_needs_special_handle. * i386-init.h : Regenerated. * i386-mnem.h : Regenerated. * i386-opc.h (enum i386_cpu): Add CpuAPX_F. (NoEgpr): New. (Prefix_NoOptimize): Ditto. (Prefix_REX2): Ditto. (RegRex2): Ditto. * i386-opc.tbl: Add rex2 prefix. * i386-reg.tbl: Add egprs (r16-r31). * i386-tbl.h: Regenerated.	2 years ago
mengqinggang	ae296cc452	LoongArch: Add support for TLS LD/GD/DESC relaxation The pcalau12i + addi.d of TLS LD/GD/DESC relax to pcaddi. Relaxation is only performed when the TLS model transition is not possible.	2 years ago
Lulu Cai	3898e04b8e	LoongArch: Add tls transition support. Transitions between DESC->IE/LE and IE->LE are supported now. 1. For DESC -> LE: pcalau12i $a0,%desc_pc_hi20(var) => lu12i.w $a0,%le_hi20(var) addi.d $a0,$a0,%desc_pc_lo12(var) => ori $a0,$a0,%le_lo12(var) ld.d $a1,$a0,%desc_ld(var) => NOP jirl $ra,$a1,%desc_call(var) => NOP add.d $a0,$a0,$tp 2. For DESC -> IE: pcalau12i $a0,%desc_pc_hi20(var) => pcalau12i $a0,%ie_pc_hi20(var) addi.d $a0,$a0,%desc_pc_lo12(var) => ld.d $a0,$a0,%ie_pc_lo12(var) ld.d $a1,$a0,%desc_ld(var) => NOP jirl $ra,$a1,%desc_call(var) => NOP add.d $a0,$a0,$tp 3. For IE -> LE: pcalau12i $a0,%ie_pc_hi20(var) => lu12i.w $a0,%le_hi20(var) ld.d $a0,$a0,%ie_pc_lo12(var) => ori $a0,$a0,%le_lo12(var) add.d $a0,$a0,$tp 4. When a tls variable is accessed using both DESC and IE, DESC transitions to IE and uses the same GOT entry as IE.	2 years ago
Lulu Cai	26265e7fdf	LoongArch: Add new relocs and macro for TLSDESC. The normal DESC instruction sequence is: pcalau12i $a0,%desc_pc_hi20(var) #R_LARCH_TLS_DESC_PC_HI20 addi.d $a0,$a0,%desc_pc_lo12(var) #R_LARCH_TLS_DESC_PC_LO12 ld.d $ra,$a0,%desc_ld(var) #R_LARCH_TLS_DESC_LD jirl $ra,$ra,%desc_call(var) #R_LARCH_TLS_DESC_CALL add.d $a0,$a0,$tp	2 years ago
Jens Remus	f96fe7f454	s390: Optionally print instruction description in disassembly Print instruction description as comment in disassembly with s390 architecture specific option "insndesc": - For objdump it can be enabled with option "-M insndesc" - In gdb it can be enabled with "set disassembler-options insndesc" Since comments are not column aligned the output can enhanced for readability by postprocessing using a filter such as "expand": ... \| expand -t 8,16,24,32,40,80 Or when using in combination with objdump option --visualize-jumps: ... \| expand \| sed -e 's/ #/\t#/' \| expand -t 1,80 Note that the instruction descriptions add about 128 KB to s390-opc.o: s390-opc.o without instruction descriptions: 216368 bytes s390-opc.o with instruction descriptions : 348432 bytes binutils/ NEWS: Mention new s390-specific disassembler option "insndesc". include/ * opcode/s390.h (struct s390_opcode): Add field to hold instruction description. opcodes/ * s390-mkopc.c: Copy instruction description from s390-opc.txt into generated operation code table s390-opc.tab. * s390-opc.c (s390_opformats): Provide NULL as description in .insn pseudo-mnemonics opcode table. * s390-dis.c: Add s390-specific disassembler option "insndesc" and optionally print the instruction description as comment in the disassembly when it is specified. gas/ * testsuite/gas/s390/s390.exp: Add new test disassembly test case "zarch-insndesc". * testsuite/gas/s390/zarch-insndesc.s: New test case for s390- specific disassembler option "insndesc". * testsuite/gas/s390/zarch-insndesc.d: Likewise. Signed-off-by: Jens Remus <jremus@linux.ibm.com> Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com>	2 years ago
Andrea Corallo	d645278cdf	aarch64: Add FEAT_ITE support This patch add support for FEAT_ITE "Instrumentation Extension" adding the "trcit" instruction. This is enabled by the +ite march flag.	3 years ago
Andrea Corallo	88b5a8ae13	aarch64: Add FEAT_SPECRES2 support This patch add supports for FEAT_SPECRES2 "Enhanced speculation restriction instructions" adding the "cosp" instruction. This is mandatory v8.9-a/v9.4-a and optional v8.0-a+/v9.0-a+. It is enabled by the +predres2 march flag.	3 years ago
mengqinggang	dc5f359ed6	LoongArch: Add new relocation R_LARCH_CALL36 R_LARCH_CALL36 is used for medium code model function call pcaddu18i+jirl, and these two instructions must adjacent. The LoongArch ABI v2.20 at here: https://github.com/loongson/la-abi-specs.	3 years ago
Jin Ma	8cb16b6858	RISC-V: Fix the wrong encoding and operand of the XTheadFmv extension. The description of instructions 'th.fmv.hw.x' and 'th.fmv.x.hw' of the XTheadFmv extension in T-Head specific is incorrect, and it also has some impact on the implementation of the binutils, so this patch corrects this. For details see: https://github.com/T-head-Semi/thead-extension-spec/pull/34 gas/ChangeLog: * testsuite/gas/riscv/x-thead-fmv.d: Correct test. * testsuite/gas/riscv/x-thead-fmv.s: Likewise. include/ChangeLog: * opcode/riscv-opc.h (MATCH_TH_FMV_HW_X): Correct coding. (MASK_TH_FMV_HW_X): Likewise. (MATCH_TH_FMV_X_HW): Likewise. (MASK_TH_FMV_X_HW): Likewise. opcodes/ChangeLog: * riscv-opc.c: Correct operands.	2 years ago
Tom Tromey	15c350f192	Add some new DW_IDX_* constants I've reimplemented the .debug_names code in GDB -- it was quite far from being correct, and the new implementation is much closer to what is specified by DWARF. However, the new writer in GDB needs to emit some symbol properties, so that the reader can be fully functional. This patch adds a few new DW_IDX_* constants, and tries to document the existing extensions as well. (My patch series add more documentation of these to the GDB manual as well.) 2023-12-10 Tom Tromey <tom@tromey.com> * dwarf2.def (DW_IDX_GNU_internal, DW_IDX_GNU_external): Comment. (DW_IDX_GNU_main, DW_IDX_GNU_language, DW_IDX_GNU_linkage_name): New constants.	2 years ago
Andreas Schwab	1b183017aa	Add basic support for RISC-V 64-bit EFI objects This adds a new PEI target pei-riscv64-little. Only objdump and objcopy are supported. bfd: * .gitignore: Add pe-riscv64igen.c. * Makefile.am (BFD64_BACKENDS): Add pei-riscv64.lo, pe-riscv64igen.lo. (BFD64_BACKENDS_CFILES): Add pei-riscv64.c. (BUILD_CFILES): Add pe-riscv64igen.c. (pe-riscv64igen.c): New rule. * Makefile.in: Regenerate. * bfd.c (bfd_get_sign_extend_vma): Add pei-riscv64-little. * coff-riscv64.c: New file. * coffcode.h (coff_set_arch_mach_hook, coff_set_flags) (coff_write_object_contents): Add riscv64 (riscv64_pei_vec) support. * config.bfd (targ_selvecs): Add riscv64_pei_vec to all riscv* targets. * configure.ac: Handle riscv64_pei_vec. * configure: Regenerate. * libpei.h (GET_OPTHDR_IMAGE_BASE, PUT_OPTHDR_IMAGE_BASE) (GET_OPTHDR_SIZE_OF_STACK_RESERVE) (PUT_OPTHDR_SIZE_OF_STACK_RESERVE) (GET_OPTHDR_SIZE_OF_STACK_COMMIT, PUT_OPTHDR_SIZE_OF_STACK_COMMIT) (GET_OPTHDR_SIZE_OF_HEAP_RESERVE, PUT_OPTHDR_SIZE_OF_HEAP_RESERVE) (GET_OPTHDR_SIZE_OF_HEAP_COMMIT, PUT_OPTHDR_SIZE_OF_HEAP_COMMIT) (GET_PDATA_ENTRY, _bfd_XX_bfd_copy_private_bfd_data_common) (_bfd_XX_bfd_copy_private_section_data) (_bfd_XX_get_symbol_info, _bfd_XX_only_swap_filehdr_out) (_bfd_XX_print_private_bfd_data_common) (_bfd_XXi_final_link_postscript, _bfd_XXi_only_swap_filehdr_out) (_bfd_XXi_swap_aouthdr_in, _bfd_XXi_swap_aouthdr_out) (_bfd_XXi_swap_aux_in, _bfd_XXi_swap_aux_out) (_bfd_XXi_swap_lineno_in, _bfd_XXi_swap_lineno_out) (_bfd_XXi_swap_scnhdr_out, _bfd_XXi_swap_sym_in) (_bfd_XXi_swap_sym_out, _bfd_XXi_swap_debugdir_in) (_bfd_XXi_swap_debugdir_out, _bfd_XXi_write_codeview_record) (_bfd_XXi_slurp_codeview_record) [COFF_WITH_peRiscV64]: Define. (_bfd_peRiscV64_print_ce_compressed_pdata): Declare. * peXXigen.c (_bfd_XXi_swap_aouthdr_in, _bfd_XXi_swap_aouthdr_out) (_bfd_XXi_swap_scnhdr_out, pe_print_pdata) (_bfd_XX_print_private_bfd_data_common) (_bfd_XX_bfd_copy_private_section_data) (_bfd_XXi_final_link_postscript): Support COFF_WITH_peRiscV64. * pei-riscv64.c: New file. * peicode.h (coff_swap_scnhdr_in, pe_ILF_build_a_bfd) (pe_ILF_object_p): Support COFF_WITH_peRiscV64. (jtab): Add dummy entry that traps. * targets.c (_bfd_target_vector): Add riscv64_pei_vec. binutils: * testsuite/binutils-all/riscv/pei-riscv64.d: New. * testsuite/binutils-all/riscv/pei-riscv64.s: New. include: * coff/riscv64.h: New file. * coff/pe.h (IMAGE_FILE_MACHINE_RISCV32) (IMAGE_FILE_MACHINE_RISCV64): Define.	3 years ago
Jens Remus	c5306fed7d	s390: Support for jump visualization in disassembly Add support for jump visualization for the s390 architecture in disassembly: objdump -d --visualize-jumps ... Annotate the (conditional) jump and branch relative instructions with information required for jump visualization: - jump: Unconditional jump / branch relative. - condjump: Conditional jump / branch relative. - jumpsr: Jump / branch relative to subroutine. Unconditional jump and branch relative instructions are annotated as jump. Conditional jump and branch relative instructions, jump / branch relative on count/index, and compare and jump / branch relative instructions are annotated as condjump. Jump and save (jas, jasl) and branch relative and save (bras, brasl) instructions are annotated as jumpsr (jump to subroutine). Provide instruction information required for jump visualization during disassembly. The instruction type is provided after determining the opcode. For non-code it is set to dis_noninsn. Otherwise it defaults to dis_nonbranch. No annotation is done for data reference instructions (i.e. instruction types dis_dref and dis_dref2). Note that the instruction type needs to be provided before printing of the instruction, as it is used in print_address_func() to translate the argument value into an address if it is assumed to be a PC-relative offset. Note that this is never the case on s390, as print_address_func() is only called with addresses and never with offsets. The target of the (conditional) jump and branch relative instructions is provided during print, when the PC relative operand is decoded. include/ * opcode/s390.h: Define opcode flags to annotate instruction class information for jump visualization: S390_INSTR_FLAG_CLASS_BRANCH, S390_INSTR_FLAG_CLASS_RELATIVE, S390_INSTR_FLAG_CLASS_CONDITIONAL, and S390_INSTR_FLAG_CLASS_SUBROUTINE. Define opcode flags mask S390_INSTR_FLAG_CLASS_MASK for above instruction class information. Define helpers for common instruction class flag combinations: S390_INSTR_FLAGS_CLASS_JUMP, S390_INSTR_FLAGS_CLASS_CONDJUMP, and S390_INSTR_FLAGS_CLASS_JUMPSR. opcodes/ * s390-mkopc.c: Add opcode flags to annotate information for jump visualization: jump, condjump, and jumpsr. * s390-opc.txt: Annotate (conditional) jump and branch relative instructions with information for jump visualization. * s390-dis.c (print_insn_s390, s390_print_insn_with_opcode): Provide instruction information for jump visualization. Signed-off-by: Jens Remus <jremus@linux.ibm.com> Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com>	2 years ago
Nelson Chu	248bf6de04	RISC-V: Add SiFive custom vector coprocessor interface instructions v1.0 SiFive has define as set of flexible instruction for extending vector coprocessor, it able to encoding opcode like .insn but with predefined format. List of instructions: sf.vc.x sf.vc.i sf.vc.vv sf.vc.xv sf.vc.iv sf.vc.fv sf.vc.vvv sf.vc.xvv sf.vc.ivv sf.vc.fvv sf.vc.vvw sf.vc.xvw sf.vc.ivw sf.vc.fvw sf.vc.v.x sf.vc.v.i sf.vc.v.vv sf.vc.v.xv sf.vc.v.iv sf.vc.v.fv sf.vc.v.vvv sf.vc.v.xvv sf.vc.v.ivv sf.vc.v.fvv sf.vc.v.vvw sf.vc.v.xvw sf.vc.v.ivw sf.vc.v.fvw Spec of Xsfvcp https://www.sifive.com/document-file/sifive-vector-coprocessor-interface-vcix-software Co-authored-by: Hau Hsu <hau.hsu@sifive.com> Co-authored-by: Kito Cheng <kito.cheng@sifive.com>	2 years ago
Christoph Müllner	ea1bd00742	RISC-V: Zv: Add support for Zvkb ISA extension Back then when the support for the RISC-V vector crypto extensions was merged, the specification was frozen, but not ratified. A frozen specification is allowed to change within tight bounds before ratification and this has happend with the vector crypto extensions. The following changes were applied: A new extension Zvkb was defined, which is a strict subset of Zvbb. * Zvkn and Zvks include now Zvkb instead of Zvbb. This patch implements these changes between the frozen and the ratified specification. Note, that this technically an incompatible change of Zvkn and Zvks, but I am not aware of any project that depends on the currently implemented behaviour of Zvkn and Zvks. So this patch should be fine. Reported-By: Jerry Shih <jerry.shih@sifive.com> Reported-By: Eric Biggers <ebiggers@kernel.org> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>	2 years ago
Jakub Jelinek	4a50820ee8	libiberty, ld: Use x86 HW optimized sha1 The following patch attempts to use x86 SHA ISA if available to speed up in my testing about 2.5x sha1 build-id processing (in my case on AMD Ryzen 5 3600) while producing the same result. I believe AArch64 has similar HW acceleration for SHA1, perhaps it could be added similarly. Note, seems lld uses BLAKE3 rather than md5/sha1. I think it would be a bad idea to lie to users, if they choose --buildid=sha1, we should be using SHA1, not some other checksum, but perhaps we could add some other --buildid= styles and perhaps make one of the new the default. Tested on x86_64-linux, both on Intel i9-7960X (which doesn't have sha_ni ISA support) without/with the patch and on AMD Ryzen 5 3600 (which does have it) without/with the patch. 2023-11-28 Jakub Jelinek <jakub@redhat.com> include/ * sha1.h (sha1_process_bytes_fn): New typedef. (sha1_choose_process_bytes): Declare. libiberty/ * configure.ac (HAVE_X86_SHA1_HW_SUPPORT): New check. * sha1.c: If HAVE_X86_SHA1_HW_SUPPORT is defined, include x86intrin.h and cpuid.h. (sha1_hw_process_bytes, sha1_hw_process_block, sha1_choose_process_bytes): New functions. * config.in: Regenerated. * configure: Regenerated. ld/ * ldbuildid.c (generate_build_id): Use sha1_choose_process_bytes () instead of &sha1_process_bytes.	2 years ago
Jan Beulich	eb5e952f95	RISC-V: reduce redundancy in sign/zero extension macro insn handling Fold M_{S,Z}EXTH, deriving signed-ness from the incoming mnemonic. Fold riscv_ext()'s calls md_assemblef(), the first of which were entirely identical, while the other pair differed in just a single character. Acked-by: Palmer Dabbelt <palmer@rivosinc.com>	2 years ago
Jin Ma	d95ba7227e	RISC-V: Add vector permutation instructions for T-Head VECTOR vendor extension T-Head has a range of vendor-specific instructions. Therefore it makes sense to group them into smaller chunks in form of vendor extensions. This patch adds permutation instructions for the "XTheadVector" extension. The 'th' prefix and the "XTheadVector" extension are documented in a PR for the RISC-V toolchain conventions ([1]). [1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19 Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com> Co-developed-by: Christoph Müllner <christoph.muellner@vrull.eu> gas/ChangeLog: * testsuite/gas/riscv/x-thead-vector.d: Add tests for permutation instructions. * testsuite/gas/riscv/x-thead-vector.s: Likewise. include/ChangeLog: * opcode/riscv-opc.h (MATCH_TH_VMVXS): New. opcodes/ChangeLog: * riscv-opc.c: Likewise.	2 years ago
Jin Ma	832cdeeccb	RISC-V: Add vector mask instructions for T-Head VECTOR vendor extension T-Head has a range of vendor-specific instructions. Therefore it makes sense to group them into smaller chunks in form of vendor extensions. This patch adds mask instructions for the "XTheadVector" extension. The 'th' prefix and the "XTheadVector" extension are documented in a PR for the RISC-V toolchain conventions ([1]). [1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19 Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com> Co-developed-by: Christoph Müllner <christoph.muellner@vrull.eu> gas/ChangeLog: * testsuite/gas/riscv/x-thead-vector.d: Add tests for mask instructions. * testsuite/gas/riscv/x-thead-vector.s: Likewise. include/ChangeLog: * opcode/riscv-opc.h (MATCH_TH_VMPOPCM): New. opcodes/ChangeLog: * riscv-opc.c: Likewise.	2 years ago
Jin Ma	1ba39b6fe5	RISC-V: Add floating-point arithmetic instructions for T-Head VECTOR vendor extension T-Head has a range of vendor-specific instructions. Therefore it makes sense to group them into smaller chunks in form of vendor extensions. This patch adds floating-point arithmetic instructions for the "XTheadVector" extension. The 'th' prefix and the "XTheadVector" extension are documented in a PR for the RISC-V toolchain conventions ([1]). [1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19 Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com> Co-developed-by: Christoph Müllner <christoph.muellner@vrull.eu> gas/ChangeLog: * testsuite/gas/riscv/x-thead-vector.d: Add tests for floating-point arithmetic instructions. * testsuite/gas/riscv/x-thead-vector.s: Likewise. include/ChangeLog: * opcode/riscv-opc.h (MATCH_TH_VFSQRTV): New. opcodes/ChangeLog: * riscv-opc.c: Likewise.	2 years ago
Jin Ma	9a51da2636	RISC-V: Add fixed-point arithmetic instructions for T-Head VECTOR vendor extension T-Head has a range of vendor-specific instructions. Therefore it makes sense to group them into smaller chunks in form of vendor extensions. This patch adds fixed-point arithmetic instructions for the "XTheadVector" extension. The 'th' prefix and the "XTheadVector" extension are documented in a PR for the RISC-V toolchain conventions ([1]). [1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19 Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com> Co-developed-by: Christoph Müllner <christoph.muellner@vrull.eu> gas/ChangeLog: * testsuite/gas/riscv/x-thead-vector.d: Add tests for fixed-point arithmetic instructions. * testsuite/gas/riscv/x-thead-vector.s: Likewise. include/ChangeLog: * opcode/riscv-opc.h (MATCH_TH_VAADDVV): New. opcodes/ChangeLog: * riscv-opc.c: Likewise.	2 years ago

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