binutils-gdb

Commit Graph

Author	SHA1	Message	Date
David Tolnay	535aade664	libiberty: Add Rust symbol demangling. Adds Rust symbol demangler. Rust mangles symbols using GNU_V3 style, adding a hash and various special character subtitutions. This adds a new rust style to cplus_demangle and adds 3 helper functions rust_demangle, rust_demangle_sym and rust_is_mangled. rust-demangle.c was written by David. Mark did the code formatting to GNU style and integration into the gcc/libiberty build system and testsuite. include/ChangeLog: 2016-11-03 David Tolnay <dtolnay@gmail.com> Mark Wielaard <mark@klomp.org> * demangle.h (DMGL_RUST): New macro. (DMGL_STYLE_MASK): Add DMGL_RUST. (demangling_styles): Add dlang_rust. (RUST_DEMANGLING_STYLE_STRING): New macro. (RUST_DEMANGLING): New macro. (rust_demangle): New prototype. (rust_is_mangled): Likewise. (rust_demangle_sym): Likewise. libiberty/ChangeLog: 2016-11-03 David Tolnay <dtolnay@gmail.com> Mark Wielaard <mark@klomp.org> * Makefile.in (CFILES): Add rust-demangle.c. (REQUIRED_OFILES): Add rust-demangle.o. * cplus-dem.c (libiberty_demanglers): Add rust_demangling case. (cplus_demangle): Handle RUST_DEMANGLING. (rust_demangle): New function. * rust-demangle.c: New file. * testsuite/Makefile.in (really-check): Add check-rust-demangle. (check-rust-demangle): New rule. * testsuite/rust-demangle-expected: New file.	10 years ago
Jason Merrill	a4ddf8dc72	Implement P0012R1, Make exception specifications part of the type system. libiberty/ * cp-demangle.c (is_fnqual_component_type): New. (d_encoding, d_print_comp_inner, d_print_mod_list): Use it. (FNQUAL_COMPONENT_CASE): New. (d_make_comp, has_return_type, d_print_comp_inner) (d_print_function_type): Use it. (next_is_type_qual): New. (d_cv_qualifiers, d_print_mod): Handle noexcept and throw-spec. include/ * demangle.h (enum demangle_component_type): Add DEMANGLE_COMPONENT_NOEXCEPT, DEMANGLE_COMPONENT_THROW_SPEC.	10 years ago
Szabolcs Nagy	c2c4ff8d52	[AArch64] Add ARMv8.3 FCMLA and FCADD instructions Add support for FCMLA and FCADD complex arithmetic SIMD instructions. FCMLA has an indexed element variant where the index range has to be treated specially because a complex number takes two elements and the indexed vector size depends on the other operands. These complex number SIMD instructions are part of ARMv8.3 https://community.arm.com/groups/processors/blog/2016/10/27/armv8-a-architecture-2016-additions include/ 2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com> * opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_IMM_ROT1, AARCH64_OPND_IMM_ROT2, AARCH64_OPND_IMM_ROT3. (enum aarch64_op): Add OP_FCMLA_ELEM. opcodes/ 2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com> * aarch64-tbl.h (QL_V3SAMEHSD_ROT, QL_ELEMENT_ROT): Define. (aarch64_feature_simd_v8_3, SIMD_V8_3): Define. (aarch64_opcode_table): Add fcmla and fcadd. (AARCH64_OPERANDS): Add IMM_ROT{1,2,3}. * aarch64-asm.h (aarch64_ins_imm_rotate): Declare. * aarch64-asm.c (aarch64_ins_imm_rotate): Define. * aarch64-dis.h (aarch64_ext_imm_rotate): Declare. * aarch64-dis.c (aarch64_ext_imm_rotate): Define. * aarch64-opc.h (enum aarch64_field_kind): Add FLD_rotate{1,2,3}. * aarch64-opc.c (fields): Add FLD_rotate{1,2,3}. (operand_general_constraint_met_p): Rotate and index range check. (aarch64_print_operand): Handle rotate operand. * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Likewise. * aarch64-opc-2.c: Likewise. gas/ 2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com> * config/tc-aarch64.c (parse_operands): Handle AARCH64_OPND_IMM_ROT. testsuite/gas/aarch64/advsimd-armv8_3.d: New. * testsuite/gas/aarch64/advsimd-armv8_3.s: New. * testsuite/gas/aarch64/illegal-fcmla.s: New. * testsuite/gas/aarch64/illegal-fcmla.l: New. * testsuite/gas/aarch64/illegal-fcmla.d: New.	10 years ago
Szabolcs Nagy	3f06e55061	[AArch64] Add ARMv8.3 combined pointer authentication load instructions Add support for ARMv8.3 LDRAA and LDRAB combined pointer authentication and load instructions. These instructions authenticate the base register and load 8 byte from it plus a scaled 10-bit offset with optional writeback to update the base register. A new instruction class (ldst_imm10) and operand type (AARCH64_OPND_ADDR_SIMM10) were introduced to handle the special addressing form. include/ 2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com> * opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_ADDR_SIMM10. (enum aarch64_insn_class): Add ldst_imm10. opcodes/ 2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com> * aarch64-tbl.h (QL_X1NIL): New. (arch64_opcode_table): Add ldraa, ldrab. (AARCH64_OPERANDS): Add "ADDR_SIMM10". * aarch64-asm.h (aarch64_ins_addr_simm10): Declare. * aarch64-asm.c (aarch64_ins_addr_simm10): Define. * aarch64-dis.h (aarch64_ext_addr_simm10): Declare. * aarch64-dis.c (aarch64_ext_addr_simm10): Define. * aarch64-opc.h (enum aarch64_field_kind): Add FLD_S_simm10. * aarch64-opc.c (fields): Add data for FLD_S_simm10. (operand_general_constraint_met_p): Handle AARCH64_OPND_ADDR_SIMM10. (aarch64_print_operand): Likewise. * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate. * aarch64-opc-2.c: Regenerate. gas/ 2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com> * config/tc-aarch64.c (parse_operands): Handle AARCH64_OPND_ADDR_SIMM10. (fix_insn): Likewise. (warn_unpredictable_ldst): Handle ldst_imm10. * testsuite/gas/aarch64/pac.s: Add ldraa and ldrab tests. * testsuite/gas/aarch64/pac.d: Likewise. * testsuite/gas/aarch64/illegal-ldraa.s: New. * testsuite/gas/aarch64/illegal-ldraa.l: New. * testsuite/gas/aarch64/illegal-ldraa.d: New.	10 years ago
Szabolcs Nagy	c84364ece4	[AArch64] Add ARMv8.3 PACGA instruction Add support for the ARMv8.3 PACGA instruction. include/ 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com> * opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_Rm_SP. opcodes/ 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com> * aarch64-tbl.h (arch64_opcode_table): Add pacga. (AARCH64_OPERANDS): Add Rm_SP. * aarch64-opc.c (aarch64_print_operand): Handle AARCH64_OPND_Rm_SP. * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate. * aarch64-opc-2.c: Regenerate. gas/ 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com> * config/tc-aarch64.c (process_omitted_operand): Handle AARCH64_OPND_Rm_SP. (parse_operands): Likewise. * testsuite/gas/aarch64/pac.s: Add pacga. * testsuite/gas/aarch64/pac.d: Add pacga.	10 years ago
Szabolcs Nagy	1924ff7567	[AArch64] Add ARMv8.3 command line option and feature flag ARMv8.3 can be selected with -march=armv8.3-a command line option. An overview of the ARMv8.3 architecture extension is at https://community.arm.com/groups/processors/blog/2016/10/27/armv8-a-architecture-2016-additions gas/ 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com> * config/tc-aarch64.c (aarch64_archs): Add "armv8.3-a". * doc/c-aarch64.texi (-march): Likewise. include/ 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com> * opcode/aarch64.h (AARCH64_FEATURE_V8_3): Define. (AARCH64_ARCH_V8_3): Define. (AARCH64_ARCH_V8_1, AARCH64_ARCH_V8_2): Simplify.	10 years ago
Thomas Preud'homme	d46a216553	Commit missing ChangeLog entry for Cortex-M33 support 2016-11-04 Thomas Preud'homme <thomas.preudhomme@arm.com> include/ * opcode/arm.h (ARM_AEXT_V8M_MAIN_DSP): Define. (ARM_AEXT2_V8M_MAIN_DSP): Likewise. (ARM_ARCH_V8M_MAIN_DSP): Likewise.	10 years ago
Thomas Preud'homme	b19ea8d28b	Add support for ARM Cortex-M33 processor 2016-11-04 Thomas Preud'homme <thomas.preudhomme@arm.com> gas/ * config/tc-arm.c (cortex-m33): Declare new processor. * doc/c-arm.texi (-mcpu ARM command line option): Document new Cortex-M33 processor. * NEWS: Mention ARM Cortex-M33 support.	10 years ago
Graham Markall	5a736821ef	arc: Implement NPS-400 dcmac instruction gas/ChangeLog: * testsuite/gas/arc/nps-400-9.d: Added. * testsuite/gas/arc/nps-400-9.s: Added. include/ChangeLog: * opcode/arc.h: Add PROTOCOL_DECODE to insn_class_t. opcodes/ChangeLog: * arc-dis.c (arc_insn_length): Return length 8 for instructions with major opcode 0xa. * arc-nps-400-tbl.h: Add dcmac instruction. * arc-opc.c (arc_operands): Added operands for dcmac instruction. (insert_nps_rbdouble_64): Added. (extract_nps_rbdouble_64): Added. (insert_nps_proto_size): Added. (extract_nps_proto_size): Added.	10 years ago
Andrew Burgess	bdfe53e3cf	arc: Change max instruction length to 64-bits The current handling for arc instructions longer than 32-bits is all handled as a special case in both the assembler and disassembler. The problem with this approach is that it leads to code duplication, selecting a long instruction is exactly the same process as selecting a short instruction, except over more bits, in both cases we select based on bit comparison, and initial operand insertion and extraction. This commit unifies both the long and short instruction worlds, converting the core opcodes library from being largely 32-bit focused, to being largely 64-bit focused. The changes are, on the whole, not too much. There's obviously a lot of type changes but otherwise the bulk of the code just works. Most of the actual functional changes are to code that previously handled the longer 48 or 64 bit instructions. The insert/extract handlers for these have now been brought into line with the short instruction insert/extract handlers. All of the special case handling code that was previously added has now been removed again. Overall, this commit reduces the amount of code in the arc assembler and disassembler. gas/ChangeLog: * config/tc-arc.c (struct arc_insn): Change type of insn field. (md_number_to_chars_midend): Support 6- and 8-byte values. (emit_insn0): Update debug output. (find_opcode_match): Likewise. (build_fake_opcode_hash_entry): Delete. (find_special_case_long_opcode): Delete. (find_special_case): Remove long format special case handling. (insert_operand): Change instruction type and update debug print format. (assemble_insn): Change instruction type, update debug print formats, and remove unneeded assert. include/ChangeLog: * opcode/arc.h (struct arc_opcode): Change type of opcode and mask fields. (struct arc_long_opcode): Delete. (struct arc_operand): Change types for insert and extract handlers. opcodes/ChangeLog: * arc-dis.c (struct arc_operand_iterator): Remove all fields relating to long instruction processing, add new limm field. (OPCODE): Rename to... (OPCODE_32BIT_INSN): ...this. (OPCODE_AC): Delete. (skip_this_opcode): Handle different instruction lengths, update macro name. (special_flag_p): Update parameter type. (find_format_from_table): Update for more instruction lengths. (find_format_long_instructions): Delete. (find_format): Update for more instruction lengths. (arc_insn_length): Likewise. (extract_operand_value): Update for more instruction lengths. (operand_iterator_next): Remove code relating to long instructions. (arc_opcode_to_insn_type): New function. (print_insn_arc):Update for more instructions lengths. * arc-ext.c (extInstruction_t): Change argument type. * arc-ext.h (extInstruction_t): Change argument type. * arc-fxi.h: Change type unsigned to unsigned long long extensively throughout. * arc-nps400-tbl.h: Add long instructions taken from arc_long_opcodes table in arc-opc.c. * arc-opc.c: Update parameter types on insert/extract handlers. (arc_long_opcodes): Delete. (arc_num_long_opcodes): Delete. (arc_opcode_len): Update for more instruction lengths.	10 years ago
Graham Markall	2e27220211	opcodes/arc: Make some macros 64-bit safe In preparation to moving to a world where arc instructions can be 2, 4, 6, or 8 bytes long, make some macros 64-bit safe. There should be no functional change after this commit. include/ChangeLog: * opcode/arc.h: Make macros 64-bit safe.	10 years ago
Graham Markall	06fe285fd2	arc: Replace ARC_SHORT macro with arc_opcode_len function In preparation for moving to a world where arc instructions can be 2, 4, 6, or 8 bytes in length, replace the ARC_SHORT macro (which is either true of false) with an arc_opcode_len function that returns a length in bytes. There should be no functional change after this commit. gas/ChangeLog: * config/tc-arc.c (assemble_insn): Replace use of ARC_SHORT with arc_opcode_len. include/ChangeLog: * opcode/arc.h (arc_opcode_len): Declare. (ARC_SHORT): Delete. opcodes/ChangeLog: * arc-dis.c (find_format_from_table): Replace use of ARC_SHORT with arc_opcode_len. (find_format_long_instructions): Likewise. * arc-opc.c (arc_opcode_len): New function.	10 years ago
Nick Clifton	e23eba971d	Add support for RISC-V architecture. bfd * Makefile.am: Add entries for riscv32-elf and riscv64-elf. * config.bdf: Likewise. * configure.ac: Likewise. * Makefile.in: Regenerate. * configure: Regenerate. * archures.c: Add bfd_riscv_arch. * reloc.c: Add riscv relocs. * targets.c: Add riscv_elf32_vec and riscv_elf64_vec. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. * elf-bfd.h: Add RISCV_ELF_DATA to enum elf_target_id. * elfnn-riscv.c: New file. * elfxx-riscv.c: New file. * elfxx-riscv.h: New file. binutils* readelf.c (guess_is_rela): Add EM_RISCV. (get_machine_name): Likewise. (dump_relocations): Add support for riscv relocations. (get_machine_flags): Add support for riscv flags. (is_32bit_abs_reloc): Add R_RISCV_32. (is_64bit_abs_reloc): Add R_RISCV_64. (is_none_reloc): Add R_RISCV_NONE. * testsuite/binutils-all/objdump.exp (cpus_expected): Add riscv. Expect the debug_ranges test to fail. gas * Makefile.am: Add riscv files. * Makefile.in: Regenerate. * NEWS: Mention the support for this architecture. * configure.in: Define a default architecture. * configure: Regenerate. * configure.tgt: Add entries for riscv. * doc/as.texinfo: Likewise. * testsuite/gas/all/gas.exp: Expect the redef tests to fail. * testsuite/gas/elf/elf.exp: Expect the groupauto tests to fail. * config/tc-riscv.c: New file. * config/tc-riscv.h: New file. * doc/c-riscv.texi: New file. * testsuite/gas/riscv: New directory. * testsuite/gas/riscv/riscv.exp: New file. * testsuite/gas/riscv/t_insns.d: New file. * testsuite/gas/riscv/t_insns.s: New file. ld * Makefile.am: Add riscv files. * Makefile.in: Regenerate. * NEWS: Mention the support for this target. * configure.tgt: Add riscv entries. * emulparams/elf32lriscv-defs.sh: New file. * emulparams/elf32lriscv.sh: New file. * emulparams/elf64lriscv-defs.sh: New file. * emulparams/elf64lriscv.sh: New file. * emultempl/riscvelf.em: New file. opcodes * configure.ac: Add entry for bfd_riscv_arch. * configure: Regenerate. * disassemble.c (disassembler): Add support for riscv. (disassembler_usage): Likewise. * riscv-dis.c: New file. * riscv-opc.c: New file. include * dis-asm.h: Add prototypes for print_insn_riscv and print_riscv_disassembler_options. * elf/riscv.h: New file. * opcode/riscv-opc.h: New file. * opcode/riscv.h: New file.	10 years ago
Nick Clifton	6d91379408	Update list of ELF machine numbers. include * elf/common.h (DT_SYMTAB_SHNDX): Define. (EM_CLOUDSHIELD, EM_COREA_1ST, EM_COREA_2ND, EM_OPEN8): Define. (EM_VIDEOCORE5, EM_56800EX, EM_BA1, EM_BA2, EM_XCORE): Define. (EM_MCHP_PIC, EM_KM32, EM_KMX32, EM_KMX16, EM_KMX8): Define. (EM_KVARC, EM_CDP, EM_COGE, EM_COOL, EM_NORC): Define. (EM_CSR_KALIMBA, EM_Z80, EM_AMDGPU, EM_RISCV): Define. (ELFOSABI_OPENVOS): Define. (GRP_MASKOS, GRP_MASKPROC): Define. binutils * readelf.c (get_dynamic_type): Add DT_SYMTAB_SHNDX. (get_machine_type): Add EM_CLOUDSHIELD, EM_COREA_1ST, EM_COREA_2ND, EM_OPEN8, EM_VIDEOCORE5, EM_56800EX, EM_BA1, EM_BA2, EM_XCORE, EM_MCHP_PIC, EM_KM32, EM_KMX32, EM_KMX16, EM_KMX8, EM_KVARC, EM_CDP, EM_COGE, EM_COOL, EM_NORC, EM_CSR_KALIMBA, EM_Z80, EM_AMDGPU, EM_RISCV. (get_osabi_name): Add ELFOSABI_CLOUDABI and ELFOSABI_OPENVS. (get_group_flags): Update to handle flags in the GRP_MASKOS and GRP_MASKPROC ranges.	10 years ago
Pedro Alves	b4f6af8ee2	FINAL/OVERRIDE: Define to empty on g++ < 4.7 final/override were only implemented in g++ 4.7. include/ChangeLog 2016-10-14 Pedro Alves <palves@redhat.com> * ansidecl.h [__cplusplus >= 201103 && GCC_VERSION < 4007] (FINAL, OVERRIDE): Define as empty. [__cplusplus < 201103 && GCC_VERSION < 4007] (FINAL): Define as __final. [__cplusplus < 201103 && GCC_VERSION >= 4007] (OVERRIDE): Define as empty.	10 years ago
Pedro Alves	d118ee3761	Move OVERRIDE/FINAL from gcc/coretypes.h to include/ansidecl.h So that GDB and other projects that share the top level can use them. Bootstrapped with all default languages + jit on x86-64 Fedora 23. gcc/ChangeLog: 2016-10-14 Pedro Alves <palves@redhat.com> * coretypes.h (OVERRIDE, FINAL): Delete, moved to include/ansidecl.h. include/ChangeLog: 2016-10-14 Pedro Alves <palves@redhat.com> * ansidecl.h (GCC_FINAL): Delete. (OVERRIDE, FINAL): New, moved from gcc/coretypes.h.	10 years ago
Claudiu Zissulescu	e5b06ef06b	[ARC] Disassembler: fix LIMM detection for short instructions. The ARC (short) instructions are using a special register number to indicate is the instruction uses a long immediate (LIMM). In the case of short instruction, this LIMM indicator depends on the ISA version used. Thus, for ARCv1 processors, the LIMM indicator is 0x3E, the same value used in "long" instructions. However, for the ARCv2 processors, this LIMM indicator is 0x1E. This patch fixes the LIMM detection for ARCv1 ISA and adds two tests. gas/ 2016-10-13 Claudiu Zissulescu <claziss@synopsys.com> * testsuite/gas/arc/shortlimm_a7.d: New file. * testsuite/gas/arc/shortlimm_a7.s: Likewise. * testsuite/gas/arc/shortlimm_hs.d: Likewise. * testsuite/gas/arc/shortlimm_hs.s: Likewise. include/ 2016-10-13 Claudiu Zissulescu <claziss@synopsys.com> * opcode/arc.h (ARC_OPCODE_ARCV2): New define. opcodes/ 2016-10-13 Claudiu Zissulescu <claziss@synopsys.com> * arc-dis.c (find_format_from_table): Discriminate LIMM indicator usage on ISA basis.	10 years ago
Alan Modra	a5721ba270	Disallow 3-operand cmp[l][i] for ppc64 cmp[l][o] get an optional L field only when generating 32-bit code. dcbf, tlbie and tlbiel keep their optional L field, ditto for R field of tbegin. cmprb, tsr., wlcr[all] and mtsle all change to a compulsory L field. L field of dcbf and wclr is 2 bits. PR 20641 include/ * opcode/ppc.h (PPC_OPERAND_OPTIONAL32): Define. opcodes/ * ppc-opc.c (L): Make compulsory. (LOPT): New, optional form of L. (HTM_R): Define as LOPT. (L0, L1): Delete. (L32OPT): New, optional for 32-bit L. (L2OPT): New, 2-bit L for dcbf. (SVC_LEC): Update. (L2): Define. (insert_l0, extract_l0, insert_l1, extract_l2): Delete. (powerpc_opcodes <cmpli, cmpi, cmpl, cmp>): Use L32OPT. <dcbf>: Use L2OPT. <tlbiel, tlbie>: Use LOPT. <wclr, wclrall>: Use L2. gas/ * config/tc-ppc.c (md_assemble): Handle PPC_OPERAND_OPTIONAL32. * testsuite/gas/ppc/power8.s: Provide tbegin. operand. * testsuite/gas/ppc/power9.d: Update cmprb disassembly.	10 years ago
Claudiu Zissulescu	2b848ebdbb	[ARC] ISA alignment. include/ 2016-09-26 Claudiu Zissulescu <claziss@synopsys.com> * opcode/arc.h (insn_class_t): Add two new classes. opcodes/ 2016-09-26 Claudiu Zissulescu <claziss@synopsys.com> * arc-ext-tbl.h (EXTINSN2OPF): Define. (EXTINSN2OP): Use EXTINSN2OPF. (bspeekm, bspop, modapp): New extension instructions. * arc-opc.c (F_DNZ_ND): Define. (F_DNZ_D): Likewise. (F_SIZEB1): Changed. (C_DNZ_D): Define. (C_HARD): Changed. * arc-tbl.h (dbnz): New instruction. (prealloc): Allow it for ARC EM. (xbfu): Likewise.	10 years ago
Alan Modra	005d79fd61	PowerPC .gnu.attributes This patch extends Tag_GNU_Power_ABI_FP to cover long double ABIs, makes the assembler warn about undefined tag values, and removes similar warnings from the linker. I think it is better to not warn in the linker about undefined tag values as future extensions to the tags then won't result in likely bogus warnings. This is consistent with the fact that an older linker won't warn on an entirely new tag. include/ * elf/ppc.h (Tag_GNU_Power_ABI_FP): Comment. bfd/ * elf-bfd.h (_bfd_elf_ppc_merge_fp_attributes): Declare. * elf32-ppc.c (_bfd_elf_ppc_merge_fp_attributes): New function. (ppc_elf_merge_obj_attributes): Use it. Don't copy first file attributes, merge them. Don't warn about undefined tag bits, or copy unknown values to output. * elf64-ppc.c (ppc64_elf_merge_private_bfd_data): Call _bfd_elf_ppc_merge_fp_attributes. binutils/ * readelf.c (display_power_gnu_attribute): Catch truncated section for all powerpc attributes. Display long double ABI. Don't capitalize words, except for names. Show known bits of tag values when some unknown bits are present. Whitespace fixes. gas/ * config/tc-ppc.c (ppc_elf_gnu_attribute): New function. (md_pseudo_table <ELF>): Handle "gnu_attribute". ld/ * testsuite/ld-powerpc/attr-gnu-4-4.s: Delete. * testsuite/ld-powerpc/attr-gnu-4-14.d: Delete. * testsuite/ld-powerpc/attr-gnu-4-24.d: Delete. * testsuite/ld-powerpc/attr-gnu-4-34.d: Delete. * testsuite/ld-powerpc/attr-gnu-4-41.d: Delete. * testsuite/ld-powerpc/attr-gnu-4-32.d: Adjust expected warning. * testsuite/ld-powerpc/attr-gnu-8-23.d: Likewise. * testsuite/ld-powerpc/attr-gnu-4-01.d: Adjust expected output. * testsuite/ld-powerpc/attr-gnu-4-02.d: Likewise. * testsuite/ld-powerpc/attr-gnu-4-03.d: Likewise. * testsuite/ld-powerpc/attr-gnu-4-10.d: Likewise. * testsuite/ld-powerpc/attr-gnu-4-11.d: Likewise. * testsuite/ld-powerpc/attr-gnu-4-20.d: Likewise. * testsuite/ld-powerpc/attr-gnu-4-22.d: Likewise. * testsuite/ld-powerpc/attr-gnu-4-33.d: Likewise. * testsuite/ld-powerpc/attr-gnu-8-11.d: Likewise. * testsuite/ld-powerpc/powerpc.exp: Don't run deleted tests.	10 years ago
Richard Sandiford	bb7eff5206	[AArch64] Add SVE condition codes SVE defines new names for existing NZCV conditions, to reflect the result of instructions like PTEST. This patch adds support for these names. The patch also adds comments to the disassembly output to show the alternative names of a condition code. For example: cinv x0, x1, cc becomes: cinv x0, x1, cc // cc = lo, ul, last and: b.cc f0 <...> becomes: b.cc f0 <...> // b.lo, b.ul, b.last Doing this for the SVE names follows the practice recommended by the SVE specification and is definitely useful when reading SVE code. If the feeling is that it's too distracting elsewhere, we could add an option to turn it off. include/ * opcode/aarch64.h (aarch64_cond): Bump array size to 4. opcodes/ * aarch64-dis.c (remove_dot_suffix): New function, split out from... (print_mnemonic_name): ...here. (print_comment): New function. (print_aarch64_insn): Call it. * aarch64-opc.c (aarch64_conds): Add SVE names. (aarch64_print_operand): Print alternative condition names in a comment. gas/ * config/tc-aarch64.c (opcode_lookup): Search for the end of a condition name, rather than assuming that it will have exactly 2 characters. (parse_operands): Likewise. * testsuite/gas/aarch64/alias.d: Add new condition-code comments to the expected output. * testsuite/gas/aarch64/beq_1.d: Likewise. * testsuite/gas/aarch64/float-fp16.d: Likewise. * testsuite/gas/aarch64/int-insns.d: Likewise. * testsuite/gas/aarch64/no-aliases.d: Likewise. * testsuite/gas/aarch64/programmer-friendly.d: Likewise. * testsuite/gas/aarch64/reloc-insn.d: Likewise. * testsuite/gas/aarch64/b_c_1.d, testsuite/gas/aarch64/b_c_1.s: New test. ld/ * testsuite/ld-aarch64/emit-relocs-280.d: Match branch comments. * testsuite/ld-aarch64/weak-undefined.d: Likewise.	10 years ago
Richard Sandiford	c0890d2628	[AArch64][SVE 31/32] Add SVE instructions This patch adds the SVE instruction definitions and associated OP_* enum values. include/ * opcode/aarch64.h (AARCH64_FEATURE_SVE): New macro. (OP_MOV_P_P, OP_MOV_Z_P_Z, OP_MOV_Z_V, OP_MOV_Z_Z, OP_MOV_Z_Zi) (OP_MOVM_P_P_P, OP_MOVS_P_P, OP_MOVZS_P_P_P, OP_MOVZ_P_P_P) (OP_NOTS_P_P_P_Z, OP_NOT_P_P_P_Z): New aarch64_ops. opcodes/ * aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB) (OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ) (OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD) (OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU) (OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB) (OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR) (OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS) (OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB) (OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD) (OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD) (OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD) (OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD) (OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD) (OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD) (OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS) (OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD) (OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD) (OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD) (OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD) (OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD) (OP_SVE_XWU, OP_SVE_XXU): New macros. (aarch64_feature_sve): New variable. (SVE): New macro. (_SVE_INSN): Likewise. (aarch64_opcode_table): Add SVE instructions. * aarch64-opc.h (extract_fields): Declare. * aarch64-opc-2.c: Regenerate. * aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops. * aarch64-asm-2.c: Regenerate. * aarch64-dis.c (extract_fields): Make global. (do_misc_decoding): Handle the new SVE aarch64_ops. * aarch64-dis-2.c: Regenerate. gas/ * doc/c-aarch64.texi: Document the "sve" feature. * config/tc-aarch64.c (REG_TYPE_R_Z_BHSDQ_VZP): New register type. (get_reg_expected_msg): Handle it. (parse_operands): When parsing operands of an SVE instruction, disallow immediates that match REG_TYPE_R_Z_BHSDQ_VZP. (aarch64_features): Add an entry for SVE.	10 years ago
Richard Sandiford	116b601937	[AArch64][SVE 30/32] Add SVE instruction classes The main purpose of the SVE aarch64_insn_classes is to describe how an index into an aarch64_opnd_qualifier_seq_t is represented in the instruction encoding. Other instructions usually use flags for this information, but (a) we're running out of those and (b) the iclass would otherwise be unused for SVE. include/ * opcode/aarch64.h (sve_cpy, sve_index, sve_limm, sve_misc) (sve_movprfx, sve_pred_zm, sve_shift_pred, sve_shift_unpred) (sve_size_bhs, sve_size_bhsd, sve_size_hsd, sve_size_sd): New aarch64_insn_classes. opcodes/ * aarch64-opc.h (FLD_SVE_M_4, FLD_SVE_M_14, FLD_SVE_M_16) (FLD_SVE_sz, FLD_SVE_tsz, FLD_SVE_tszl_8, FLD_SVE_tszl_19): New aarch64_field_kinds. * aarch64-opc.c (fields): Add corresponding entries. * aarch64-asm.c (aarch64_get_variant): New function. (aarch64_encode_variant_using_iclass): Likewise. (aarch64_opcode_encode): Call it. * aarch64-dis.c (aarch64_decode_variant_using_iclass): New function. (aarch64_opcode_decode): Call it.	10 years ago
Richard Sandiford	047cd301d4	[AArch64][SVE 29/32] Add new SVE core & FP register operands SVE uses some new fields to store W, X and scalar FP registers. This patch adds corresponding operands. include/ * opcode/aarch64.h (AARCH64_OPND_SVE_Rm): New aarch64_opnd. (AARCH64_OPND_SVE_Rn_SP, AARCH64_OPND_SVE_VZn, AARCH64_OPND_SVE_Vd) (AARCH64_OPND_SVE_Vm, AARCH64_OPND_SVE_Vn): Likewise. opcodes/ * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core and FP register operands. * aarch64-opc.h (FLD_SVE_Rm, FLD_SVE_Rn, FLD_SVE_Vd, FLD_SVE_Vm) (FLD_SVE_Vn): New aarch64_field_kinds. * aarch64-opc.c (fields): Add corresponding entries. (aarch64_print_operand): Handle the new SVE core and FP register operands. * aarch64-opc-2.c: Regenerate. * aarch64-asm-2.c: Likewise. * aarch64-dis-2.c: Likewise. gas/ * config/tc-aarch64.c (parse_operands): Handle the new SVE core and FP register operands.	10 years ago
Richard Sandiford	165d495085	[AArch64][SVE 28/32] Add SVE FP immediate operands This patch adds support for the new SVE floating-point immediate operands. One operand uses the same 8-bit encoding as base AArch64, but in a different position. The others use a single bit to select between two values. One of the single-bit operands is a choice between 0 and 1, where 0 is not a valid 8-bit encoding. I think the cleanest way of handling these single-bit immediates is therefore to use the IEEE float encoding itself as the immediate value and select between the two possible values when encoding and decoding. As described in the covering note for the patch that added F_STRICT, we get better error messages by accepting unsuffixed vector registers and leaving the qualifier matching code to report an error. This means that we carry on parsing the other operands, and so can try to parse FP immediates for invalid instructions like: fcpy z0, #2.5 In this case there is no suffix to tell us whether the immediate should be treated as single or double precision. Again, we get better error messages by picking one (arbitrary) immediate size and reporting an error for the missing suffix later. include/ * opcode/aarch64.h (AARCH64_OPND_SVE_FPIMM8): New aarch64_opnd. (AARCH64_OPND_SVE_I1_HALF_ONE, AARCH64_OPND_SVE_I1_HALF_TWO) (AARCH64_OPND_SVE_I1_ZERO_ONE): Likewise. opcodes/ * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE FP immediate operands. * aarch64-opc.h (FLD_SVE_i1): New aarch64_field_kind. * aarch64-opc.c (fields): Add corresponding entry. (operand_general_constraint_met_p): Handle the new SVE FP immediate operands. (aarch64_print_operand): Likewise. * aarch64-opc-2.c: Regenerate. * aarch64-asm.h (ins_sve_float_half_one, ins_sve_float_half_two) (ins_sve_float_zero_one): New inserters. * aarch64-asm.c (aarch64_ins_sve_float_half_one): New function. (aarch64_ins_sve_float_half_two): Likewise. (aarch64_ins_sve_float_zero_one): Likewise. * aarch64-asm-2.c: Regenerate. * aarch64-dis.h (ext_sve_float_half_one, ext_sve_float_half_two) (ext_sve_float_zero_one): New extractors. * aarch64-dis.c (aarch64_ext_sve_float_half_one): New function. (aarch64_ext_sve_float_half_two): Likewise. (aarch64_ext_sve_float_zero_one): Likewise. * aarch64-dis-2.c: Regenerate. gas/ * config/tc-aarch64.c (double_precision_operand_p): New function. (parse_operands): Use it to calculate the dp_p input to parse_aarch64_imm_float. Handle the new SVE FP immediate operands.	10 years ago
Richard Sandiford	e950b34539	[AArch64][SVE 27/32] Add SVE integer immediate operands This patch adds the new SVE integer immediate operands. There are three kinds: - simple signed and unsigned ranges, but with new widths and positions. - 13-bit logical immediates. These have the same form as in base AArch64, but at a different bit position. In the case of the "MOV Zn.<T>, #<limm>" alias of DUPM, the logical immediate <limm> is not allowed to be a valid DUP immediate, since DUP is preferred over DUPM for constants that both instructions can handle. - a new 9-bit arithmetic immediate, of the form "<imm8>{, LSL #8}". In some contexts the operand is signed and in others it's unsigned. As an extension, we allow shifted immediates to be written as a single integer, e.g. "#256" is equivalent to "#1, LSL #8". We also use the shiftless form as the preferred disassembly, except for the special case of "#0, LSL #8" (a redundant encoding of 0). include/ * opcode/aarch64.h (AARCH64_OPND_SIMM5): New aarch64_opnd. (AARCH64_OPND_SVE_AIMM, AARCH64_OPND_SVE_ASIMM) (AARCH64_OPND_SVE_INV_LIMM, AARCH64_OPND_SVE_LIMM) (AARCH64_OPND_SVE_LIMM_MOV, AARCH64_OPND_SVE_SHLIMM_PRED) (AARCH64_OPND_SVE_SHLIMM_UNPRED, AARCH64_OPND_SVE_SHRIMM_PRED) (AARCH64_OPND_SVE_SHRIMM_UNPRED, AARCH64_OPND_SVE_SIMM5) (AARCH64_OPND_SVE_SIMM5B, AARCH64_OPND_SVE_SIMM6) (AARCH64_OPND_SVE_SIMM8, AARCH64_OPND_SVE_UIMM3) (AARCH64_OPND_SVE_UIMM7, AARCH64_OPND_SVE_UIMM8) (AARCH64_OPND_SVE_UIMM8_53): Likewise. (aarch64_sve_dupm_mov_immediate_p): Declare. opcodes/ * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE integer immediate operands. * aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5) (FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9) (FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds. * aarch64-opc.c (fields): Add corresponding entries. (operand_general_constraint_met_p): Handle the new SVE integer immediate operands. (aarch64_print_operand): Likewise. (aarch64_sve_dupm_mov_immediate_p): New function. * aarch64-opc-2.c: Regenerate. * aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm) (ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters. * aarch64-asm.c (aarch64_ins_limm_1): New function, split out from... (aarch64_ins_limm): ...here. (aarch64_ins_inv_limm): New function. (aarch64_ins_sve_aimm): Likewise. (aarch64_ins_sve_asimm): Likewise. (aarch64_ins_sve_limm_mov): Likewise. (aarch64_ins_sve_shlimm): Likewise. (aarch64_ins_sve_shrimm): Likewise. * aarch64-asm-2.c: Regenerate. * aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm) (ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors. * aarch64-dis.c (decode_limm): New function, split out from... (aarch64_ext_limm): ...here. (aarch64_ext_inv_limm): New function. (decode_sve_aimm): Likewise. (aarch64_ext_sve_aimm): Likewise. (aarch64_ext_sve_asimm): Likewise. (aarch64_ext_sve_limm_mov): Likewise. (aarch64_top_bit): Likewise. (aarch64_ext_sve_shlimm): Likewise. (aarch64_ext_sve_shrimm): Likewise. * aarch64-dis-2.c: Regenerate. gas/ * config/tc-aarch64.c (parse_operands): Handle the new SVE integer immediate operands.	10 years ago
Richard Sandiford	98907a7049	[AArch64][SVE 26/32] Add SVE MUL VL addressing modes This patch adds support for addresses of the form: [<base>, #<offset>, MUL VL] This involves adding a new AARCH64_MOD_MUL_VL modifier, which is why I split it out from the other addressing modes. For LD2, LD3 and LD4, the offset must be a multiple of the structure size, so for LD3 the possible values are 0, 3, 6, .... The patch therefore extends value_aligned_p to handle non-power-of-2 alignments. include/ * opcode/aarch64.h (AARCH64_OPND_SVE_ADDR_RI_S4xVL): New aarch64_opnd. (AARCH64_OPND_SVE_ADDR_RI_S4x2xVL, AARCH64_OPND_SVE_ADDR_RI_S4x3xVL) (AARCH64_OPND_SVE_ADDR_RI_S4x4xVL, AARCH64_OPND_SVE_ADDR_RI_S6xVL) (AARCH64_OPND_SVE_ADDR_RI_S9xVL): Likewise. (AARCH64_MOD_MUL_VL): New aarch64_modifier_kind. opcodes/ * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL operands. * aarch64-opc.c (aarch64_operand_modifiers): Initialize the AARCH64_MOD_MUL_VL entry. (value_aligned_p): Cope with non-power-of-two alignments. (operand_general_constraint_met_p): Handle the new MUL VL addresses. (print_immediate_offset_address): Likewise. (aarch64_print_operand): Likewise. * aarch64-opc-2.c: Regenerate. * aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl) (ins_sve_addr_ri_s9xvl): New inserters. * aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function. (aarch64_ins_sve_addr_ri_s6xvl): Likewise. (aarch64_ins_sve_addr_ri_s9xvl): Likewise. * aarch64-asm-2.c: Regenerate. * aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl) (ext_sve_addr_ri_s9xvl): New extractors. * aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function. (aarch64_ext_sve_addr_ri_s4xvl): Likewise. (aarch64_ext_sve_addr_ri_s6xvl): Likewise. (aarch64_ext_sve_addr_ri_s9xvl): Likewise. * aarch64-dis-2.c: Regenerate. gas/ * config/tc-aarch64.c (SHIFTED_NONE, SHIFTED_MUL_VL): New parse_shift_modes. (parse_shift): Handle SHIFTED_MUL_VL. (parse_address_main): Add an imm_shift_mode parameter. (parse_address, parse_sve_address): Update accordingly. (parse_operands): Handle MUL VL addressing modes.	10 years ago
Richard Sandiford	4df068de52	[AArch64][SVE 25/32] Add support for SVE addressing modes This patch adds most of the new SVE addressing modes and associated operands. A follow-on patch adds MUL VL, since handling it separately makes the changes easier to read. The patch also introduces a new "operand-dependent data" field to the operand flags, based closely on the existing one for opcode flags. For SVE this new field needs only 2 bits, but it could be widened in future if necessary. include/ * opcode/aarch64.h (AARCH64_OPND_SVE_ADDR_RI_U6): New aarch64_opnd. (AARCH64_OPND_SVE_ADDR_RI_U6x2, AARCH64_OPND_SVE_ADDR_RI_U6x4) (AARCH64_OPND_SVE_ADDR_RI_U6x8, AARCH64_OPND_SVE_ADDR_RR) (AARCH64_OPND_SVE_ADDR_RR_LSL1, AARCH64_OPND_SVE_ADDR_RR_LSL2) (AARCH64_OPND_SVE_ADDR_RR_LSL3, AARCH64_OPND_SVE_ADDR_RX) (AARCH64_OPND_SVE_ADDR_RX_LSL1, AARCH64_OPND_SVE_ADDR_RX_LSL2) (AARCH64_OPND_SVE_ADDR_RX_LSL3, AARCH64_OPND_SVE_ADDR_RZ) (AARCH64_OPND_SVE_ADDR_RZ_LSL1, AARCH64_OPND_SVE_ADDR_RZ_LSL2) (AARCH64_OPND_SVE_ADDR_RZ_LSL3, AARCH64_OPND_SVE_ADDR_RZ_XTW_14) (AARCH64_OPND_SVE_ADDR_RZ_XTW_22, AARCH64_OPND_SVE_ADDR_RZ_XTW1_14) (AARCH64_OPND_SVE_ADDR_RZ_XTW1_22, AARCH64_OPND_SVE_ADDR_RZ_XTW2_14) (AARCH64_OPND_SVE_ADDR_RZ_XTW2_22, AARCH64_OPND_SVE_ADDR_RZ_XTW3_14) (AARCH64_OPND_SVE_ADDR_RZ_XTW3_22, AARCH64_OPND_SVE_ADDR_ZI_U5) (AARCH64_OPND_SVE_ADDR_ZI_U5x2, AARCH64_OPND_SVE_ADDR_ZI_U5x4) (AARCH64_OPND_SVE_ADDR_ZI_U5x8, AARCH64_OPND_SVE_ADDR_ZZ_LSL) (AARCH64_OPND_SVE_ADDR_ZZ_SXTW, AARCH64_OPND_SVE_ADDR_ZZ_UXTW): Likewise. opcodes/ * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE address operands. * aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14) (FLD_SVE_xs_22): New aarch64_field_kinds. (OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags. (get_operand_specific_data): New function. * aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14 and FLD_SVE_xs_22. (operand_general_constraint_met_p): Handle the new SVE address operands. (sve_reg): New array. (get_addr_sve_reg_name): New function. (aarch64_print_operand): Handle the new SVE address operands. * aarch64-opc-2.c: Regenerate. * aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl) (ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl) (ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters. * aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function. (aarch64_ins_sve_addr_rr_lsl): Likewise. (aarch64_ins_sve_addr_rz_xtw): Likewise. (aarch64_ins_sve_addr_zi_u5): Likewise. (aarch64_ins_sve_addr_zz): Likewise. (aarch64_ins_sve_addr_zz_lsl): Likewise. (aarch64_ins_sve_addr_zz_sxtw): Likewise. (aarch64_ins_sve_addr_zz_uxtw): Likewise. * aarch64-asm-2.c: Regenerate. * aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl) (ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl) (ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors. * aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function. (aarch64_ext_sve_addr_ri_u6): Likewise. (aarch64_ext_sve_addr_rr_lsl): Likewise. (aarch64_ext_sve_addr_rz_xtw): Likewise. (aarch64_ext_sve_addr_zi_u5): Likewise. (aarch64_ext_sve_addr_zz): Likewise. (aarch64_ext_sve_addr_zz_lsl): Likewise. (aarch64_ext_sve_addr_zz_sxtw): Likewise. (aarch64_ext_sve_addr_zz_uxtw): Likewise. * aarch64-dis-2.c: Regenerate. gas/ * config/tc-aarch64.c (REG_TYPE_SVE_BASE, REG_TYPE_SVE_OFFSET): New register types. (get_reg_expected_msg): Handle them. (aarch64_addr_reg_parse): New function, split out from aarch64_reg_parse_32_64. Handle Z registers too. (aarch64_reg_parse_32_64): Call it. (parse_address_main): Add base_qualifier, offset_qualifier, base_type and offset_type parameters. Handle SVE base and offset registers. (parse_address): Update call to parse_address_main. (parse_sve_address): New function. (parse_operands): Parse the new SVE address operands.	10 years ago
Richard Sandiford	2442d8466e	[AArch64][SVE 24/32] Add AARCH64_OPND_SVE_PATTERN_SCALED Some SVE instructions count the number of elements in a given vector pattern and allow a scale factor of [1, 16] to be applied to the result. This scale factor is written ", MUL #n", where "MUL" is a new operator. E.g.: UQINCD X0, POW2, MUL #2 This patch adds support for this kind of operand. All existing operators were shifts of some kind, so there was a natural range of [0, 63] regardless of context. This was then narrowered further by later checks (e.g. to [0, 31] when used for 32-bit values). In contrast, MUL doesn't really have a natural context-independent range. Rather than pick one arbitrarily, it seemed better to make the "shift" amount a full 64-bit value and leave the range test to the usual operand-checking code. I've rearranged the fields of aarch64_opnd_info so that this doesn't increase the size of the structure (although I don't think its size is critical anyway). include/ * opcode/aarch64.h (AARCH64_OPND_SVE_PATTERN_SCALED): New aarch64_opnd. (AARCH64_MOD_MUL): New aarch64_modifier_kind. (aarch64_opnd_info): Make shifter.amount an int64_t and rearrange the fields. opcodes/ * aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for AARCH64_OPND_SVE_PATTERN_SCALED. * aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind. * aarch64-opc.c (fields): Add a corresponding entry. (set_multiplier_out_of_range_error): New function. (aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL. (operand_general_constraint_met_p): Handle AARCH64_OPND_SVE_PATTERN_SCALED. (print_register_offset_address): Use PRIi64 to print the shift amount. (aarch64_print_operand): Likewise. Handle AARCH64_OPND_SVE_PATTERN_SCALED. * aarch64-opc-2.c: Regenerate. * aarch64-asm.h (ins_sve_scale): New inserter. * aarch64-asm.c (aarch64_ins_sve_scale): New function. * aarch64-asm-2.c: Regenerate. * aarch64-dis.h (ext_sve_scale): New inserter. * aarch64-dis.c (aarch64_ext_sve_scale): New function. * aarch64-dis-2.c: Regenerate. gas/ * config/tc-aarch64.c (SHIFTED_MUL): New parse_shift_mode. (parse_shift): Handle it. Reject AARCH64_MOD_MUL for all other shift modes. Skip range tests for AARCH64_MOD_MUL. (process_omitted_operand): Handle AARCH64_OPND_SVE_PATTERN_SCALED. (parse_operands): Likewise.	10 years ago
Richard Sandiford	245d2e3fe8	[AArch64][SVE 23/32] Add SVE pattern and prfop operands The SVE instructions have two enumerated operands: one to select a vector pattern and another to select a prefetch operation. The latter is a cut-down version of the base AArch64 prefetch operation. Both types of operand can also be specified as raw enum values such as #31. Reserved values can only be specified this way. If it hadn't been for the pattern operand, I would have been tempted to use the existing parsing for prefetch operations and add extra checks for SVE. However, since the patterns needed new enum parsing code anyway, it seeemed cleaner to reuse it for the prefetches too. Because of the small number of enum values, I don't think we'd gain anything by using hash tables. include/ * opcode/aarch64.h (AARCH64_OPND_SVE_PATTERN): New aarch64_opnd. (AARCH64_OPND_SVE_PRFOP): Likewise. (aarch64_sve_pattern_array): Declare. (aarch64_sve_prfop_array): Likewise. opcodes/ * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP. * aarch64-opc.h (FLD_SVE_pattern): New aarch64_field_kind. (FLD_SVE_prfop): Likewise. * aarch64-opc.c: Include libiberty.h. (aarch64_sve_pattern_array): New variable. (aarch64_sve_prfop_array): Likewise. (fields): Add entries for FLD_SVE_pattern and FLD_SVE_prfop. (aarch64_print_operand): Handle AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP. * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Likewise. * aarch64-opc-2.c: Likewise. gas/ * config/tc-aarch64.c (parse_enum_string): New function. (po_enum_or_fail): New macro. (parse_operands): Handle AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP.	10 years ago
Richard Sandiford	d50c751e00	[AArch64][SVE 22/32] Add qualifiers for merging and zeroing predication This patch adds qualifiers to represent /z and /m suffixes on predicate registers. include/ * opcode/aarch64.h (AARCH64_OPND_QLF_P_Z): New aarch64_opnd_qualifier. (AARCH64_OPND_QLF_P_M): Likewise. opcodes/ * aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for AARCH64_OPND_QLF_P_[ZM]. (aarch64_print_operand): Print /z and /m where appropriate. gas/ * config/tc-aarch64.c (vector_el_type): Add NT_zero and NT_merge. (parse_vector_type_for_operand): Assert that the skipped character is a '.'. (parse_predication_for_operand): New function. (parse_typed_reg): Parse /z and /m suffixes for predicate registers. (vectype_to_qualifier): Handle NT_zero and NT_merge.	10 years ago
Richard Sandiford	f11ad6bc0f	[AArch64][SVE 21/32] Add Zn and Pn registers This patch adds the Zn and Pn registers, and associated fields and operands. include/ * opcode/aarch64.h (AARCH64_OPND_CLASS_SVE_REG): New aarch64_operand_class. (AARCH64_OPND_CLASS_PRED_REG): Likewise. (AARCH64_OPND_SVE_Pd, AARCH64_OPND_SVE_Pg3, AARCH64_OPND_SVE_Pg4_5) (AARCH64_OPND_SVE_Pg4_10, AARCH64_OPND_SVE_Pg4_16) (AARCH64_OPND_SVE_Pm, AARCH64_OPND_SVE_Pn, AARCH64_OPND_SVE_Pt) (AARCH64_OPND_SVE_Za_5, AARCH64_OPND_SVE_Za_16, AARCH64_OPND_SVE_Zd) (AARCH64_OPND_SVE_Zm_5, AARCH64_OPND_SVE_Zm_16, AARCH64_OPND_SVE_Zn) (AARCH64_OPND_SVE_Zn_INDEX, AARCH64_OPND_SVE_ZnxN) (AARCH64_OPND_SVE_Zt, AARCH64_OPND_SVE_ZtxN): New aarch64_opnds. opcodes/ * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands. * aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5) (FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt) (FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16) (FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds. * aarch64-opc.c (fields): Add corresponding entries here. (operand_general_constraint_met_p): Check that SVE register lists have the correct length. Check the ranges of SVE index registers. Check for cases where p8-p15 are used in 3-bit predicate fields. (aarch64_print_operand): Handle the new SVE operands. * aarch64-opc-2.c: Regenerate. * aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters. * aarch64-asm.c (aarch64_ins_sve_index): New function. (aarch64_ins_sve_reglist): Likewise. * aarch64-asm-2.c: Regenerate. * aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors. * aarch64-dis.c (aarch64_ext_sve_index): New function. (aarch64_ext_sve_reglist): Likewise. * aarch64-dis-2.c: Regenerate. gas/ * config/tc-aarch64.c (NTA_HASVARWIDTH): New macro. (AARCH64_REG_TYPES): Add ZN and PN. (get_reg_expected_msg): Handle them. (parse_vector_type_for_operand): Add a reg_type parameter. Skip the width for Zn and Pn registers. (parse_typed_reg): Extend vector handling to Zn and Pn. Update the call to parse_vector_type_for_operand. Set HASVARTYPE for Zn and Pn, expecting the width to be 0. (parse_vector_reg_list): Restrict error about [BHSD]nn operands to REG_TYPE_VN. (vectype_to_qualifier): Use S_[BHSD] qualifiers for NTA_HASVARWIDTH. (parse_operands): Handle the new Zn and Pn operands. (REGSET16): New macro, split out from... (REGSET31): ...here. (reg_names): Add Zn and Pn entries.	10 years ago
Richard Sandiford	0c608d6b62	[AArch64][SVE 20/32] Add support for tied operands SVE has some instructions in which the same register appears twice in the assembly string, once as an input and once as an output. This patch adds a general mechanism for that. The patch needs to add new information to the instruction entries. One option would have been to extend the flags field of the opcode to 64 bits (since we already rely on 64-bit integers being available on the host). However, the _INSN macros mean that it's easy to add new information as top-level fields without affecting the existing table entries too much. Going for that option seemed to give slightly neater code. include/ opcode/aarch64.h (aarch64_opcode): Add a tied_operand field. (AARCH64_OPDE_UNTIED_OPERAND): New aarch64_operand_error_kind. opcodes/ * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN) (_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN) (V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field. * aarch64-opc.c (aarch64_match_operands_constraint): Check for tied operands. gas/ * config/tc-aarch64.c (output_operand_error_record): Handle AARCH64_OPDE_UNTIED_OPERAND.	10 years ago
Richard Sandiford	4989adac84	[AArch64][SVE 13/32] Add an F_STRICT flag SVE predicate operands can appear in three forms: 1. unsuffixed: "Pn" 2. with a predication type: "Pn/[ZM]" 3. with a size suffix: "Pn.[BHSD]" No variation is allowed: unsuffixed operands cannot have a (redundant) suffix, and the suffixes can never be dropped. Unsuffixed Pn are used in LDR and STR, but they are also used for Pg operands in cases where the result is scalar and where there is therefore no choice to be made between "merging" and "zeroing". This means that some Pg operands have suffixes and others don't. It would be possible to use context-sensitive parsing to handle this difference. The tc-aarch64.c code would then raise an error if the wrong kind of suffix is used for a particular instruction. However, we get much more user-friendly error messages if we parse all three forms for all SVE instructions and record the suffix as a qualifier. The normal qualifier matching code can then report cases where the wrong kind of suffix is used. This is a slight extension of existing usage, which really only checks for the wrong choice of suffix within a particular kind of suffix. The only catch is a that a "NIL" entry in the qualifier list specifically means "no suffix should be present" (case 1 above). NIL isn't a wildcard here. It also means that an instruction that requires all-NIL qualifiers can fail to match (because a suffix was supplied when it shouldn't have been); this requires a slight change to find_best_match. This patch adds an F_STRICT flag to select this behaviour. The flag will be set for all SVE instructions. The behaviour for other instructions doesn't change. include/ * opcode/aarch64.h (F_STRICT): New flag. opcodes/ * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT. gas/ * config/tc-aarch64.c (find_best_match): Simplify, allowing an instruction with all-NIL qualifiers to fail to match.	10 years ago
Richard Earnshaw	27e5a27096	[arm] Automatically enable CRC instructions on supported ARMv8-A CPUs. 2016-09-07 Richard Earnshaw <rearnsha@arm.com> * opcode/arm.h (ARM_ARCH_V8A_CRC): New architecture. 2016-09-07 Richard Earnshaw <rearnsha@arm.com> * config/tc-arm.c ((arm_cpus): Use ARM_ARCH_V8A_CRC for all ARMv8-A CPUs except xgene1.	10 years ago
Cupertino Miranda	a87aa054a6	Fixes to legacy ARC relocations. Added support for ARC_SDA_12 reloc. Fixed ARC_N32_ME. Added ME (middle-endian) to ARC_SDA_12 reloc. bfd/ChangeLog: Cupertino Miranda <cmiranda@synopsys.com> * reloc.c: Fixed type in ARC_SECTOFF relocations. Added ARC_SDA_12 relocation. * bfd-in2.h: Regenerated from the previous changes. * libbfd.h: Regenerated from the previous changes. include/ChangeLog: Cupertino Miranda <cmiranda@synopsys.com> * elf/arc-reloc.def: Fixed relocation formula for N, SDA, SDA_12, SDA_16_LD, S13_PCREL, N32_ME, SECTOFF_* relocations. * opcode/arc-func.h (replace_disp12s): Added. Used for SDA_12 relocation.	10 years ago
Thomas Preud'homme	4ba2ef8fbe	2016-08-04 Thomas Preud'homme <thomas.preudhomme@arm.com> bfd/ * elf32-arm.c (CMSE_PREFIX): Define macro. (elf32_arm_stub_cmse_branch_thumb_only): Define stub sequence. (cmse_branch_thumb_only): Declare stub. (struct elf32_arm_link_hash_table): Define cmse_stub_sec field. (elf32_arm_get_plt_info): Add globals parameter. Use it to return FALSE if there is no PLT. (arm_type_of_stub): Adapt to new elf32_arm_get_plt_info signature. (elf32_arm_final_link_relocate): Likewise. (elf32_arm_gc_sweep_hook): Likewise. (elf32_arm_gc_mark_extra_sections): Mark sections holding ARMv8-M secure entry functions. (arm_stub_is_thumb): Add case for arm_stub_cmse_branch_thumb_only. (arm_dedicated_stub_output_section_required): Change to a switch case and add a case for arm_stub_cmse_branch_thumb_only. (arm_dedicated_stub_output_section_required_alignment): Likewise. (arm_stub_dedicated_output_section_name): Likewise. (arm_stub_dedicated_input_section_ptr): Likewise and remove ATTRIBUTE_UNUSED for htab parameter. (arm_stub_required_alignment): Likewise. (arm_stub_sym_claimed): Likewise. (arm_dedicated_stub_section_padding): Likewise. (cmse_scan): New function. (elf32_arm_size_stubs): Call cmse_scan for ARM M profile targets. Set stub_changed to TRUE if such veneers were created. (elf32_arm_swap_symbol_in): Add detection code for CMSE special symbols. include/ * arm.h (ARM_GET_SYM_CMSE_SPCL): Define macro. (ARM_SET_SYM_CMSE_SPCL): Likewise. ld/ * ld.texinfo (Placement of SG veneers): New concept entry. * testsuite/ld-arm/arm-elf.exp (Secure gateway veneers: no .gnu.sgstubs section): New test. (Secure gateway veneers: wrong entry functions): Likewise. (Secure gateway veneers (ARMv8-M Baseline)): Likewise. (Secure gateway veneers (ARMv8-M Mainline)): Likewise. * testsuite/ld-arm/cmse-veneers.s: New file. * testsuite/ld-arm/cmse-veneers.d: Likewise. * testsuite/ld-arm/cmse-veneers.rd: Likewise. * testsuite/ld-arm/cmse-veneers.sd: Likewise. * testsuite/ld-arm/cmse-veneers-no-gnu_sgstubs.out: Likewise. * testsuite/ld-arm/cmse-veneers-wrong-entryfct.out: Likewise.	10 years ago
Nick Clifton	fa3fcee7b8	Synchronize libiberty sources with FSF GCC mainline version. include * libiberty.h (MAX_ALLOCA_SIZE): New macro. libiberty * make-relative-prefix.c (make_relative_prefix_1): Fall back to malloc if alloca argument is greater than MAX_ALLOCA_SIZE. * cp-demangle.c (cplus_demangle_operators): Add f[lrLR]. (d_expression_1): Handle them. (d_maybe_print_fold_expression): New. (d_print_comp_inner): Use it. (d_index_template_argument): Handle negative index. * cp-demangle.c (cplus_demangle_operators): Add sP and sZ. (d_print_comp_inner): Handle them. (d_template_args_1): Split out from d_template_args. (d_args_length): New. PR c++/70926 * cplus-dem.c: Handle large values and overflow when demangling length variables. (demangle_template_value_parm): Read only until end of mangled string. (do_hpacc_template_literal): Likewise. (do_type): Handle overflow when demangling array indices. * cp-demangle.c (cplus_demangle_print_callback): Avoid zero-length VLAs. PR c++/70498 * cp-demangle.c (d_expression_1): Formatting fix. * cplus-dem.c (enum type_kind_t): Add tk_rvalue_reference constant. (demangle_template_value_parm): Handle tk_rvalue_reference type kind. (do_type): Support 'O' type id (rvalue references). * testsuite/demangle-expected: Add tests. PR c++/70498 * cp-demangle.c: Parse numbers as integer instead of long to avoid overflow after sanity checks. Include <limits.h> if available. (INT_MAX): Define if necessary. (d_make_template_param): Takes integer argument instead of long. (d_make_function_param): Likewise. (d_append_num): Likewise. (d_identifier): Likewise. (d_number): Parse as and return integer. (d_compact_number): Handle overflow. (d_source_name): Change variable type to integer for parsed number. (d_java_resource): Likewise. (d_special_name): Likewise. (d_discriminator): Likewise. (d_unnamed_type): Likewise. * testsuite/demangle-expected: Add regression test cases. * configure: Remove SH5 support. PR c++/69687 * cplus-dem.c: Include <limits.h> if available. (INT_MAX): Define if necessary. (remember_type, remember_Ktype, register_Btype, string_need): Abort if we detect cases where we the size of the allocation would overflow. PR c++/70492 * cplus-dem.c (gnu_special): Handle case where consume_count returns -1. PR c++/67394 PR c++/70481 * cplus-dem.c (squangle_mop_up): Zero bsize/ksize after freeing btypevec/ktypevec. * testsuite/demangle-expected: Add coverage tests.	10 years ago
Andrew Jenner	dfdaec14b0	Fix some PowerPC VLE BFD issues and add some PowerPC VLE instructions. bfd/ * elf32-ppc.c (is_branch_reloc): Recognise VLE branch relocations. (ppc_elf_howto_raw): Fix dst_mask of R_PPC_VLE_REL15. (ppc_elf_vle_split16): Clear field before inserting. opcodes/ * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and 'e_cmplwi' to 'e_cmpli' instead. (OPVUPRT, OPVUPRT_MASK): Define. (powerpc_opcodes): Add E200Z4 insns. (vle_opcodes): Add context save/restore insns. include/ * opcode/ppc.h (PPC_OPCODE_E200Z4): New define.	10 years ago
Graham Markall	db18dbabad	Begin implementing ARC NPS-400 Accelerator instructions opcodes * arc-nps400-tbl.h: Change block comments to GNU format. * arc-dis.c: Add new globals addrtypenames, addrtypenames_max, and addtypeunknown. (get_addrtype): New function. (print_insn_arc): Print colons and address types when required. * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to define insert and extract functions for all address types. (arc_operands): Add operands for colon and all address types. * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table. * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands, insert_nps_bd_num_buff and extract_nps_bd_num_buff functions. * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table. * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands, insert_nps_pmu_num_job and extract_nps_pmu_num_job functions. include * opcode/arc.h: Add ARC_OPERAND_ADDRTYPE, ARC_OPERAND_COLON. Add the arc_nps_address_type enum and ARC_NUM_ADDRTYPES. * opcode/arc.h: Add BMU to insn_class_t enum. * opcode/arc.h: Add PMU to insn_class_t enum. gas * config/tc-arc.c: Add new global arc_addrtype_hash. Define O_colon and O_addrtype. (debug_exp): Add O_colon and O_addrtype. (tokenize_arguments): Handle colon and address type tokens. (declare_addrtype): New function. (md_begin): Initialise arc_addrtype_hash. (arc_parse_name): Add lookup of address types. (assemble_insn): Handle colons and address types by ignoring them. * testsuite/gas/arc/nps400-8.s: New file. * testsuite/gas/arc/nps400-8.d: New file. * testsuite/gas/arc/nps400-8.s: Add PMU instruction tests. * testsuite/gas/arc/nps400-8.d: Add expected PMU instruction output.	10 years ago
Claudiu Zissulescu	37fd5ef3ec	Add support to the ARC disassembler for selecting instruction classes. gas * testsuite/gas/arc/dsp.d: New file. * testsuite/gas/arc/dsp.s: Likewise. * testsuite/gas/arc/fpu.d: Likewise. * testsuite/gas/arc/fpu.s: Likewise. * testsuite/gas/arc/ext2op.d: Add specific disassembler option. * testsuite/gas/arc/ext3op.d: Likewise. * testsuite/gas/arc/tdpfp.d: Likewise. * testsuite/gas/arc/tfpuda.d: Likewise. opcodes * arc-dis.c (skipclass): New structure. (decodelist): New variable. (is_compatible_p): New function. (new_element): Likewise. (skip_class_p): Likewise. (find_format_from_table): Use skip_class_p function. (find_format): Decode first the extension instructions. (print_insn_arc): Select either ARCEM or ARCHS based on elf e_flags. (parse_option): New function. (parse_disassembler_options): Likewise. (print_arc_disassembler_options): Likewise. (print_insn_arc): Use parse_disassembler_options function. Proper select ARCv2 cpu variant. * disassemble.c (disassembler_usage): Add ARC disassembler options. binutils* doc/binutils.texi (objdump): Add ARC disassembler options. * testsuite/binutils-all/arc/dsp.s: New file. * testsuite/binutils-all/arc/objdump.exp: Likewise. include * dis-asm.h: Declare print_arc_disassembler_options.	10 years ago
Thomas Preud'homme	7635954182	Add support for creating ELF import libraries 2016-07-15 Thomas Preud'homme <thomas.preudhomme@arm.com> bfd/ * elf-bfd.h (elf_backend_filter_implib_symbols): Declare backend hook. (_bfd_elf_filter_global_symbols): Declare. * elf.c (_bfd_elf_filter_global_symbols): New function. * elflink.c (elf_filter_global_symbols): Likewise. (elf_output_implib): Likewise. (bfd_elf_final_link): Call above function, failing if it does. * elfxx-target.h (elf_backend_filter_implib_symbols): Define macro and default it to NULL. (elf_backend_copy_indirect_symbol): Fix spacing. (elf_backend_hide_symbol): Likewise. (elfNN_bed): Initialize elf_backend_filter_implib_symbols backend hook. include/ * bfdlink.h (struct bfd_link_info): Declare new ldscript_def and out_implib_bfd fields. 2016-07-15 Thomas Preud'homme <thomas.preudhomme@arm.com> Nick Clifton <nickc@redhat.com> ld/ * emultempl/elf32.em (gld${EMULATION_NAME}_after_open): Open import library file for writing and initialize implib_bfd field of link_info structure. * emultempl/pe.em (pe_implib_filename): Remove variable declaration. (OPTION_IMPLIB_FILENAME): Remove macro definition. (gld${EMULATION_NAME}_add_options): Remove --out-implib option. (gld_${EMULATION_NAME}_list_options): Likewise. (gld${EMULATION_NAME}_handle_option): Likewise. (gld_${EMULATION_NAME}_finish): Use command_line.out_implib_filename instead of pe_implib_filename. * emultempl/pep.em (pep_implib_filename): Remove variable declaration. (OPTION_IMPLIB_FILENAME): Remove enumerator. (gld${EMULATION_NAME}_add_options): Remove --out-implib option. (gld_${EMULATION_NAME}_list_options): Likewise. (gld${EMULATION_NAME}_handle_option): Likewise. (gld_${EMULATION_NAME}_finish): Use command_line.out_implib_filename instead of pep_implib_filename. * ld.h (args_type): Declare new out_implib_filename field. * ld.texinfo (--out-implib): Move documentation to arch-independent part and rephrase to apply to ELF targets. * ldexp.c (exp_fold_tree_1): Set ldscript_def field to 1 for symbols defined in linker scripts. * ldlex.h (enum option_values): Declare new OPTION_OUT_IMPLIB enumerator. * lexsup.c (ld_options): Add entry for new --out-implib switch. (parse_args): Handle OPTION_OUT_IMPLIB case. * testsuite/ld-elf/elf.exp (Generate empty import library): New test. (Generate import library): Likewise. * testsuite/ld-elf/implib.s: Likewise. * testsuite/ld-elf/implib.rd: New file. * testsuite/ld-elf/empty-implib.out: Likewise	10 years ago
John Baldwin	bc7b765ab7	Pass SIGLIBRT directly to child processes. FreeBSD's librt uses SIGLIBRT as an internal signal to implement SIGEV_THREAD sigevent notifications. Similar to SIGLWP or SIGCANCEL this signal should be passed through to child processes by default. include/ChangeLog: * signals.def: Add GDB_SIGNAL_LIBRT. gdb/ChangeLog: * common/signals.c (gdb_signal_from_host): Handle SIGLIBRT. (do_gdb_signal_to_host): Likewise. * infrun.c (_initialize_infrun): Pass GDB_SIGNAL_LIBRT through to programs. * proc-events.c (signal_table): Add entry for SIGLIBRT.	10 years ago
Claudiu Zissulescu	fa1c017017	[ARC] Fix/improve small data support. The R_ARC_SDA32 is wrongly described as a ME relocation, fix it. Offset the __SDATA_BEGIN__ to take advantage of the signed 9-bit field of the load/store instructions. include/ 2016-07-08 Claudiu Zissulescu <claziss@synopsys.com> * elf/arc-reloc.def (ARC_SDA32): Don't use ME transformation. ld/ 2016-07-08 Claudiu Zissulescu <claziss@synopsys.com> * emulparams/arcelf.sh (SDATA_START_SYMBOLS): Add offset. * testsuite/ld-arc/sda-relocs.dd: New file. * testsuite/ld-arc/sda-relocs.ld: Likewise. * testsuite/ld-arc/sda-relocs.rd: Likewise. * testsuite/ld-arc/sda-relocs.s: Likewise. * testsuite/ld-arc/arc.exp: Add SDA tests.	10 years ago
Cupertino Miranda	08759e0fc8	Fixes done to TLS. TLS relocations did not support multiple TLS modes for the same symbol in a single object file. Refactored how GOT and TLS is implemented. Removed code duplications between local and global symbols conditioning. bfd/ChangeLog: 2016-06-14 Cupertino Miranda <cmiranda@synopsys.com> * arc-got.h: Moved got related structures from elf32-arc.c to this file. More precisely, tls_type_e, tls_got_entries, got_entry. * (arc_get_local_got_ents, got_entry_for_type, new_got_entry_to_list, tls_type_for_reloc, symbol_has_entry_of_type, get_got_entry_list_for_symbol, arc_got_entry_type_for_reloc, ADD_SYMBOL_REF_SEC_AND_RELOC, arc_fill_got_info_for_reloc, relocate_fix_got_relocs_for_got_info, create_got_dynrelocs_for_single_entry, create_got_dynrelocs_for_got_info): Added to file. * elf32-arc.c: Removed GOT & TLS related structs and functions to arc-got.h. Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>	10 years ago
Andre Vieria	f0728ee368	[ARM] Change noread to purecode. bfd/ChangeLog 2016-07-05 Andre Vieria <andre.simoesdiasvieira@arm.com> * bfd-in2.h (SEC_ELF_NOREAD): Rename to ... (SEC_ELF_PURECODE): ... this. * elf32-arm.c (elf32_arm_post_process_headers): Rename SEC_ELF_NOREAD to SEC_ELF_NOREAD. (elf32_arm_fake_sections): Likewise. (elf_32_arm_section_flags): Likewise. (elf_32_arm_lookup_section_flags): Likewise. * section.c (SEC_ELF_NOREAD): Rename to ... (SEC_ELF_PURECODE): ... this. binutils/ChangeLog 2016-07-05 Andre Vieria <andre.simoesdiasvieira@arm.com> * objdump.c (dump_section_header): Rename SEC_ELF_NOREAD to SEC_ELF_NOREAD. * readelf.c (get_elf_section_flags): Rename ARM_NOREAD to ARM_PURECODE and SHF_ARM_NOREAD to SHF_ARM_PURECODE. (process_section_headers): Rename noread to purecode. * section.c (SEC_ELF_NOREAD): Rename to ... (SEC_ELF_PURECODE): ... this. include/ChangeLog 2016-07-05 Andre Vieria <andre.simoesdiasvieira@arm.com> * elf/arm.h (SHF_ARM_NOREAD): Rename to ... (SHF_ARM_PURECODE): ... this. ld/ChangeLog 2016-07-05 Andre Vieria <andre.simoesdiasvieira@arm.com> * testsuite/ld-arm/arm_noread.ld: Renamed to ... testsuite/ld-arm/arm_purecode.ld: ... this, and replaced all noread's by purecode.	10 years ago
Szabolcs Nagy	93d8990cba	[AArch64] Fix +nofp16 handling Feature flag handling was not perfect, +nofp16 disabled fp instructions too. New feature flag macros were added to check features with multiple bits set (matters for FP_F16 and SIMD_F16 opcode feature tests). The unused AARCH64_OPCODE_HAS_FEATURE was removed, all checks should use one of the AARCH64_CPU_HAS_* macros. AARCH64_CPU_HAS_FEATURE now checks all feature bits. The aarch64_features table now contains the dependencies as a separate field (so when the feature is enabled all dependencies are enabled and when it is disabled everything that depends on it is disabled). Note that armv8-a+foo+nofoo is not equivalent to armv8-a if +foo turns on dependent features that nofoo does not turn off. gas/ * config/tc-aarch64.c (struct aarch64_option_cpu_value_table): Add require field. (aarch64_features): Initialize require fields. (aarch64_parse_features): Handle dependencies. (aarch64_feature_enable_set, aarch64_feature_disable_set): New. (md_assemble): Use AARCH64_CPU_HAS_ALL_FEATURES. * testsuite/gas/aarch64/illegal-nofp16.s: New. * testsuite/gas/aarch64/illegal-nofp16.l: New. * testsuite/gas/aarch64/illegal-nofp16.d: New. include/ * opcode/aarch64.h (AARCH64_CPU_HAS_ALL_FEATURES): New. (AARCH64_CPU_HAS_ANY_FEATURES): New. (AARCH64_CPU_HAS_FEATURE): Define as AARCH64_CPU_HAS_ALL_FEATURES. (AARCH64_OPCODE_HAS_FEATURE): Remove.	10 years ago
Matthew Wahab	534dbe460e	[ARM][GAS] ARMv8.2 should enable ARMv8.1 NEON instructions. GAS fails to recognize march=armv8.2-a as a superset of march=armv8.1-a when assembling NEON instructions. The patch corrects this, making -march=armv8.2-a -mfpu=neon-fp-armv8 enable the NEON intructions introduced with ARMv8.1-A. include/ 2016-06-30 Matthew Wahab <matthew.wahab@arm.com> * opcode/arm.h (ARM_ARCH_V8_2a): Add FPU_NEON_EXT_RDMA to the set of enabled FPU features. gas/ 2016-06-30 Matthew Wahab <matthew.wahab@arm.com> * testsuite/gas/arm/armv8_2+rdma.d: New.	10 years ago
Trevor Saunders	042c94de56	sparc: make SPARC_OPCODE_ARCH_MAX part of its enum include/ChangeLog: 2016-06-29 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * opcode/sparc.h (enum sparc_opcode_arch_val): Move SPARC_OPCODE_ARCH_MAX into the enum.	10 years ago
Richard Sandiford	dab26bf4e7	[AArch64] Make register indices be full 64-bit values aarch64_opnd_info used bitfields to hold vector element indices, but values were stored into those bitfields before their ranges had been checked. This meant large invalid indices could be silently truncated to smaller valid indices. The two obvious fixes were to do the range checking earlier or use a full 64-bit field for the index. I went for the latter for two reasons: - Doing the range checking in operand_general_constraint_met_p seems structurally cleaner than doing it while parsing. - The bitfields didn't really buy us anything. The imm field of the union is already 128 bits, so we can use a full int64_t index without growing the structure. The patch also adds missing range checks for the elements in a register list index. include/ * opcode/aarch64.h (aarch64_opnd_info): Change index fields to int64_t. opcodes/ * aarch64-opc.c (operand_general_constraint_met_p): Check the range of ldst_elemlist operands. (print_register_list): Use PRIi64 to print the index. (aarch64_print_operand): Likewise. gas/ * testsuite/gas/aarch64/diagnostic.s, testsuite/gas/aarch64/diagnostic.l: Add tests for out-of-range indices.	10 years ago

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2089 Commits (2d7f2507d4d26430da7e32e8fc75f045f634fced)