binutils-gdb

Commit Graph

Author	SHA1	Message	Date
Alan Modra	c9049d301b	* subsegs.h (struct frchain): Delete frch_seg. (frchain_root): Delete. (seg_info): Define as macro. * subsegs.c (frchain_root): Delete. (abs_seg_info, und_seg_info, absolute_frchain): Delete. (subsegs_begin, subseg_change): Adjust for above. (subseg_set_rest): Likewise. Add new frchain structs to seginfo rather than to one big list. (subseg_get): Don't special case abs, und sections. (subseg_new, subseg_force_new): Don't set frchainP here. (seg_info): Delete. (subsegs_print_statistics): Adjust frag chain control list traversal. * debug.c (dmp_frags): Likewise. * dwarf2dbg.c (first_frag_for_seg): Don't start looking for frag at frchain_root. Make use of known frchain ordering. (last_frag_for_seg): Likewise. (get_frag_fix): Likewise. Add seg param. (process_entries, out_debug_aranges): Adjust get_frag_fix calls. * write.c (chain_frchains_together_1): Adjust for struct frchain. (SUB_SEGMENT_ALIGN): Likewise. (subsegs_finish): Adjust frchain list traversal. * config/tc-xtensa.c (xtensa_cleanup_align_frags): Likewise. (xtensa_fix_target_frags, xtensa_mark_narrow_branches): Likewise. (xtensa_mark_zcl_first_insns, xtensa_fix_a0_b_retw_frags): Likewise. (xtensa_fix_b_j_loop_end_frags): Likewise. (xtensa_fix_close_loop_end_frags): Likewise. (xtensa_fix_short_loop_frags, xtensa_sanity_check): Likewise. (retrieve_segment_info): Delete frch_seg initialisation.	21 years ago
Thiemo Seufer	104b4fab38	2006-05-03 Thiemo Seufer <ths@mips.com> [ opcodes/ChangeLog ] * mips-opc.c (mips_builtin_opcodes): Fix mftr argument order. [ gas/testsuite/ChangeLog ] * gas/mips/mips32-mt.d: Fix mftr argument order.	21 years ago
Alan Modra	f592407e4d	bfd/ * libbfd-in.h (_bfd_generic_new_section_hook): Declare. * section.c (bfd_abs_symbol, bfd_com_symbol): Delete. (bfd_und_symbol, bfd_ind_symbol): Delete. (BFD_FAKE_SECTION): Remove SYM_PTR param, set symbol_ptr_ptr to &SEC.symbol. (STD_SECTION): Adjust. (_bfd_generic_new_section_hook): New function, extracted from.. (bfd_section_init): ..here. (bfd_make_section_old_way): Call new_section_hook for abs, com, und and ind sections. * elf.c (_bfd_elf_large_com_section): Adjust. * aoutx.h (new_section_hook): Call _bfd_generic_new_section_hook. * pdp11.c (new_section_hook): Likewise. * coffcode.h (coff_new_section_hook): Likewise. * ecoff.c (_bfd_ecoff_new_section_hook): Likewise. * elf.c (_bfd_elf_new_section_hook): Likewise. * vms.c (vms_new_section_hook): Likwise. * elf32-arm.c (elf32_arm_new_section_hook): Check used_by_bfd isn't already set. * elf32-sh64.c (sh64_elf_new_section_hook): Likewise. * elf32-xtensa.c (elf_xtensa_new_section_hook): Likewise. * elf64-mmix.c (mmix_elf_new_section_hook): Likewise. * elf64-ppc.c (ppc64_elf_new_section_hook): Likewise. * elfxx-mips.c (_bfd_mips_elf_new_section_hook): Likewise. * elfxx-sparc.c (_bfd_sparc_elf_new_section_hook): Likewise. * ieee.c (ieee_new_section_hook): Likewise. Call _bfd_generic_new_section_hook too. * mmo.c (mmo_new_section_hook): Likewise. * oasys.c (oasys_new_section_hook): Likewise. * som.c (som_new_section_hook): Likewise. * coff-w65.c (reloc_processing): Don't use bfd_abs_symbol. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. gas/ * subsegs.c (subseg_get): Don't call obj_sec_set_private_data. * config/obj-elf.h (obj_sec_set_private_data): Delete. * config/tc-hppa.c (tc_gen_reloc): Don't use bfd_abs_symbol. * config/tc-mn10300.c (tc_gen_reloc): Likewise.	21 years ago
Joseph Myers	df7849c593	* config/tc-arm.c (do_iwmmxt_wldstbh): Don't multiply offset by 4 here. (md_apply_fix3): Multiply offset by 4 here for BFD_RELOC_ARM_CP_OFF_IMM_S2 and BFD_RELOC_ARM_T32_CP_OFF_IMM_S2. testsuite: * gas/arm/iwmmxt.s: Increase offsets for wstrb and wstrh. * gas/arm/iwmmxt.d: Update expected results. * gas/arm/iwmmxt-bad2.s: Test wstrb, wstrh, wldrb and wldrh. * gas/arm/iwmmxt-bad2.l: Update expected error messages.	21 years ago
H.J. Lu	2d545b822e	2006-05-02 H.J. Lu <hongjiu.lu@intel.com> Jan Beulich <jbeulich@novell.com> * config/tc-i386.c (output_invalid_buf): Change size for unsigned char. * config/tc-tic30.c (output_invalid_buf): Likewise. * config/tc-i386.c (output_invalid): Cast none-ascii char to unsigned char. * config/tc-tic30.c (output_invalid): Likewise.	21 years ago
Daniel Jacobowitz	38fc1cb168	binutils/ * doc/Makefile.am (AM_MAKEINFOFLAGS): New. (TEXI2POD): Use AM_MAKEINFOFLAGS. (config.texi): Don't set top_srcdir. * doc/binutils.texi: Don't use top_srcdir. * aclocal.m4, Makefile.in, doc/Makefile.in: Regenerated. gas/ * doc/Makefile.am (AM_MAKEINFOFLAGS): New. (TEXI2POD): Use AM_MAKEINFOFLAGS. (asconfig.texi): Don't set top_srcdir. * doc/as.texinfo: Don't use top_srcdir. * aclocal.m4, Makefile.in, doc/Makefile.in: Regenerated. ld/ * Makefile.am (AM_MAKEINFOFLAGS): Add libiberty. (TEXI2POD): Use AM_MAKEINFOFLAGS. (configdoc.texi): Don't set top_srcdir. * ld.texinfo: Don't use top_srcdir. * aclocal.m4, Makefile.in: Regenerated.	21 years ago
H.J. Lu	f9f21a03c5	2006-05-02 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (output_invalid_buf): Change size to 16. * config/tc-tic30.c (output_invalid_buf): Likewise. * config/tc-i386.c (output_invalid): Use snprintf instead of sprintf. * config/tc-ia64.c (declare_register_set): Likewise. (emit_one_bundle): Likewise. (check_dependencies): Likewise. * config/tc-tic30.c (output_invalid): Likewise.	21 years ago
Paul Brook	a8bc6c780e	2006-05-02 Paul Brook <paul@codesourcery.com> bfd/ * elf32-arm.c (elf32_arm_final_link_relocate): Set thumb funciton bit for R_ARM_REL32. gas/ * config/tc-arm.c (arm_optimize_expr): New function. * config/tc-arm.h (md_optimize_expr): Define (arm_optimize_expr): Add prototype. (TC_FORCE_RELOCATION_SUB_SAME): Define. ld/testsuite/ * ld-arm/arm-elf.exp: Add thumb-rel32. * ld-arm/thumb-rel32.d: New test. * ld-arm/thumb-rel32.s: New test.	21 years ago
Ben Elliston	22772e33f6	* config/obj-elf.h (ELF_TARGET_SYMBOL_FIELDS): Make single bit field unsigned.	21 years ago
Ben Elliston	58633d9add	* sb.h (sb_list_vector): Move to sb.c. * sb.c (free_list): Use type of sb_list_vector directly. (sb_build): Fix off-by-one error in assertion about `size'.	21 years ago
Ben Elliston	89cdfe5739	* listing.c (listing_listing): Remove useless loop. * macro.c (macro_expand): Remove is_positional local variable. * read.c (s_comm_internal): Simplify `if' condition 1 \|\| x -> 1 and simplify surrounding expressions, where possible. (assign_symbol): Likewise. (s_weakref): Likewise. * symbols.c (colon): Likewise.	21 years ago
Alan Modra	c35da14031	* subsegs.c (subseg_set_rest): Always set seginfp->frchainP if NULL.	21 years ago
Thiemo Seufer	9bcd4f993c	[ gas/ChangeLog ] 2006-04-30 Thiemo Seufer <ths@mips.com> David Ung <davidu@mips.com> * config/tc-mips.c (validate_mips_insn): Handling of udi cases. (mips_immed): New table that records various handling of udi instruction patterns. (mips_ip): Adds udi handling. [ include/opcode/ChangeLog ] 2006-04-30 Thiemo Seufer <ths@mips.com> David Ung <davidu@mips.com> * mips.h: Defines udi bits and masks. Add description of characters which may appear in the args field of udi instructions. [ opcodes/ChangeLog ] 2006-04-30 Thiemo Seufer <ths@mips.com> David Ung <davidu@mips.com> * mips-opc.c (mips_builtin_opcodes): Add udi instructions "udi0" to "udi15". * mips-dis.c (print_insn_args): Adds udi argument handling.	21 years ago
H.J. Lu	5645cf1e51	2006-04-29 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/fp.d: New file. * gas/i386/fp.s: Likewise. * gas/i386/i386.exp: Run "fp".	21 years ago
Thiemo Seufer	bdb09db1cf	Don't mis-spell your boss' name...	21 years ago
Thiemo Seufer	59c455b37c	[ opcodes/ChangeLog ] 2006-04-28 Thiemo Seufer <ths@mips.com> David Ung <davidu@mips.com> Nigel Stevens <nigel@mips.com> * mips-dis.c (mips_cp0sel_names_mips3264r2): Add MT register names. [ gas/testsuite/ChangeLog ] 2006-04-28 Thiemo Seufer <ths@mips.com> David Ung <davidu@mips.com> Nigel Stevens <nigel@mips.com> * gas/mips/cp0sel-names-mips32r2.d, gas/mips/cp0sel-names-mips64r2.d: Update for MT register names.	21 years ago
Alan Modra	001ae1a4ab	* dwarf2dbg.c (get_line_subseg): Attach new struct line_seg to end of list rather than beginning.	21 years ago
Julian Brown	136da41424	* gas/config/tc-arm.c (neon_is_quarter_float): Move, and rename to... (is_quarter_float): Rename from above. Simplify slightly. (parse_qfloat_immediate): Parse a "quarter precision" floating-point number. (parse_neon_mov): Parse floating-point constants. (neon_qfloat_bits): Fix encoding. (neon_cmode_for_move_imm): Tweak to use floating-point encoding in preference to integer encoding when using the F32 type.	21 years ago
Julian Brown	b7dc49052a	* gas/testsuite/gas/arm/neon-const.s: New testcase. Neon floating-point constants. * gas/testsuite/gas/arm/neon-const.d: Expected output of above. * gas/testsuite/gas/arm/neon-cov.d: Expect floating-point disassembly for VMOV.F32.	21 years ago
Julian Brown	dcbf9037d8	* config/tc-arm.c (neon_el_type): Make NT_invtype be the zero (so zero-initialising structures containing it will lead to invalid types). (arm_it): Add vectype to each operand. (NTA_HASTYPE, NTA_HASINDEX): Constants used in neon_typed_alias defined field. (neon_typed_alias): New structure. Extra information for typed register aliases. (reg_entry): Add neon type info field. (arm_reg_parse): Remove RTYPE argument (revert to previous arguments). Break out alternative syntax for coprocessor registers, etc. into... (arm_reg_alt_syntax): New function. Alternate syntax handling broken out from arm_reg_parse. (parse_neon_type): Move. Return SUCCESS/FAIL. (first_error): New function. Call to ensure first error which occurs is reported. (parse_neon_operand_type): Parse exactly one type. (NEON_ALL_LANES, NEON_INTERLEAVE_LANES): Move. (parse_typed_reg_or_scalar): New function. Handle core of both arm_typed_reg_parse and parse_scalar. (arm_typed_reg_parse): Parse a register with an optional type. (NEON_SCALAR_REG, NEON_SCALAR_INDEX): Extract parts of parse_scalar result. (parse_scalar): Parse a Neon scalar with optional type. (parse_reg_list): Use first_error. (parse_vfp_reg_list): Use arm_typed_reg_parse instead of arm_reg_parse. (neon_alias_types_same): New function. Return true if two (alias) types are the same. (parse_neon_el_struct_list): Use parse_typed_reg_or_scalar. Return type of elements. (insert_reg_alias): Return new reg_entry not void. (insert_neon_reg_alias): New function. Insert type/index information as well as register for alias. (create_neon_reg_alias): New function. Parse .dn/.qn directives and make typed register aliases accordingly. (s_dn, s_qn): New functions. Handle incorrectly used .dn/.qn at start of line. (s_unreq): Delete type information if present. (s_arm_unwind_save_mmxwr): Remove arg 3 from arm_reg_parse calls. (s_arm_unwind_save_mmxwcg): Likewise. (s_arm_unwind_movsp): Likewise. (s_arm_unwind_setfp): Likewise. (parse_shift): Likewise. (parse_shifter_operand): Likewise. (parse_address): Likewise. (parse_tb): Likewise. (tc_arm_regname_to_dw2regnum): Likewise. (md_pseudo_table): Add dn, qn. (parse_neon_mov): Handle typed operands. (parse_operands): Likewise. (neon_type_mask): Add N_SIZ. (N_ALLMODS): New macro. (neon_check_shape): Fix typo in NS_DDD_QQQ case. Use first_error. (el_type_of_type_chk): Add some safeguards. (modify_types_allowed): Fix logic bug. (neon_check_type): Handle operands with types. (neon_three_same): Remove redundant optional arg handling. (do_neon_dyadic_i64_su, do_neon_shl_imm, do_neon_qshl_imm) (do_neon_logic, do_neon_qdmulh, do_neon_fcmp_absolute) (do_neon_step): Adjust accordingly. (neon_cmode_for_logic_imm): Use first_error. (do_neon_bitfield): Call neon_check_type. (neon_dyadic): Rename to... (neon_dyadic_misc): ...this. New name for neon_dyadic. Add bitfield to allow modification of type of the destination. (do_neon_dyadic_if_su, do_neon_dyadic_if_i, do_neon_dyadic_if_i_d) (do_neon_addsub_if_i, do_neon_mul): Adjust accordingly. (do_neon_compare): Make destination be an untyped bitfield. (neon_scalar_for_mul): Use NEON_SCALAR_REG, NEON_SCALAR_INDEX. (neon_mul_mac): Return early in case of errors. (neon_move_immediate): Use first_error. (neon_mac_reg_scalar_long): Fix type to include scalar. (do_neon_dup): Likewise. (do_neon_mov): Likewise (in several places). (do_neon_tbl_tbx): Fix type. (do_neon_ld_st_interleave, neon_alignment_bit, do_neon_ld_st_lane) (do_neon_ld_dup): Exit early in case of errors and/or use first_error. (opcode_lookup): Update for parse_neon_type returning SUCCESS/FAIL. Handle .dn/.qn directives. (REGDEF): Add zero for reg_entry neon field.	21 years ago
Julian Brown	2161fcce7b	* gas/arm/neon-psyn.s: Basic test of programmers syntax. * gas/arm/neon-psyn.d: Expected output of above.	21 years ago
Julian Brown	5287ad6231	* config/tc-arm.c (limits.h): Include. (fpu_arch_vfp_v3, fpu_vfp_ext_v3, fpu_neon_ext_v1) (fpu_vfp_v3_or_neon_ext): Declare constants. (neon_el_type): New enumeration of types for Neon vector elements. (neon_type_el): New struct. Define type and size of a vector element. (NEON_MAX_TYPE_ELS): Define constant. The maximum number of types per instruction. (neon_type): Define struct. The type of an instruction. (arm_it): Add 'vectype' for the current instruction. (isscalar, immisalign, regisimm, isquad): New predicates for operands. (vfp_sp_reg_pos): Rename to... (vfp_reg_pos): ...this, and add VFP_REG_Dd, VFP_REG_Dm, VFP_REG_Dn tags. (arm_reg_type): Add REG_TYPE_NQ (Neon Q register) and REG_TYPE_NDQ (Neon D or Q register). (reg_expected_msgs): Sync with above. Allow VFD to mean VFP or Neon D register. (GE_OPT_PREFIX_BIG): Define constant, for use in... (my_get_expression): Allow above constant as argument to accept 64-bit constants with optional prefix. (arm_reg_parse): Add extra argument to return the specific type of register in when either a D or Q register (REG_TYPE_NDQ) is requested. Can be NULL. (parse_scalar): New function. Parse Neon scalar (vector reg and index). (parse_reg_list): Update for new arm_reg_parse args. (parse_vfp_reg_list): Allow parsing of Neon D/Q register lists. (parse_neon_el_struct_list): New function. Parse element/structure register lists for VLD<n>/VST<n> instructions. (s_arm_unwind_save_vfp): Update for new parse_vfp_reg_list args. (s_arm_unwind_save_mmxwr): Likewise. (s_arm_unwind_save_mmxwcg): Likewise. (s_arm_unwind_movsp): Likewise. (s_arm_unwind_setfp): Likewise. (parse_big_immediate): New function. Parse an immediate, which may be 64 bits wide. Put results in inst.operands[i]. (parse_shift): Update for new arm_reg_parse args. (parse_address): Likewise. Add parsing of alignment specifiers. (parse_neon_mov): Parse the operands of a VMOV instruction. (operand_parse_code): Add OP_RND, OP_RNQ, OP_RNDQ, OP_RNSC, OP_NRDLST, OP_NSTRLST, OP_NILO, OP_RNDQ_I0, OP_RR_RNSC, OP_RNDQ_RNSC, OP_RND_RNSC, OP_VMOV, OP_RNDQ_IMVNb, OP_RNDQ_I63b, OP_I0, OP_I16z, OP_I32z, OP_I64, OP_I64z, OP_oI32b, OP_oRND, OP_oRNQ, OP_oRNDQ. (parse_operands): Handle new codes above. (encode_arm_vfp_sp_reg): Rename to... (encode_arm_vfp_reg): ...this. Handle D regs (0-31) too. Complain if selected VFP version only supports D0-D15. (do_vfp_sp_monadic, do_vfp_sp_dyadic, do_vfp_sp_compare_z) (do_vfp_dp_sp_cvt, do_vfp_reg_from_sp, do_vfp_reg2_from_sp2) (do_vfp_sp_from_reg, do_vfp_sp2_from_reg2, do_vfp_sp_ldst) (do_vfp_dp_ldst, vfp_sp_ldstm, vfp_dp_ldstm): Update for new encode_arm_vfp_reg name, and allow 32 D regs. (do_vfp_dp_rd_rm, do_vfp_dp_rn_rd, do_vfp_dp_rd_rn, do_vfp_dp_rd_rn_rm) (do_vfp_rm_rd_rn): New functions to encode VFP insns allowing 32 D regs. (do_vfp_sp_const, do_vfp_dp_const, vfp_conv, do_vfp_sp_conv_16) (do_vfp_dp_conv_16, do_vfp_sp_conv_32, do_vfp_dp_conv_32): Handle constant-load and conversion insns introduced with VFPv3. (neon_tab_entry): New struct. (NEON_ENC_TAB): Bit patterns for overloaded Neon instructions, and those which are the targets of pseudo-instructions. (neon_opc): Enumerate opcodes, use as indices into... (neon_enc_tab): ...this. Hold data from NEON_ENC_TAB. (NEON_ENC_INTEGER, NEON_ENC_ARMREG, NEON_ENC_POLY, NEON_ENC_FLOAT) (NEON_ENC_SCALAR, NEON_ENC_IMMED, NEON_ENC_INTERLV, NEON_ENC_LANE) (NEON_ENC_DUP): Define meaningful helper macros to look up values in neon_enc_tab. (neon_shape): Enumerate shapes (permitted register widths, etc.) for Neon instructions. (neon_type_mask): New. Compact type representation for type checking. (N_SU_ALL, N_SU_32, N_SU_16_64, N_SUF_32, N_I_ALL, N_IF_32): Common permitted type combinations. (N_IGNORE_TYPE): New macro. (neon_check_shape): New function. Check an instruction shape for multiple alternatives. Return the specific shape for the current instruction. (neon_modify_type_size): New function. Modify a vector type and size, depending on the bit mask in argument 1. (neon_type_promote): New function. Convert a given "key" type (of an operand) into the correct type for a different operand, based on a bit mask. (type_chk_of_el_type): New function. Convert a type and size into the compact representation used for type checking. (el_type_of_type_ckh): New function. Reverse of above (only when a single bit is set in the bit mask). (modify_types_allowed): New function. Alter a mask of allowed types based on a bit mask of modifications. (neon_check_type): New function. Check the type of the current instruction against the variable argument list. The "key" type of the instruction is returned. (neon_dp_fixup): New function. Fill in and modify instruction bits for a Neon data-processing instruction depending on whether we're in ARM mode or Thumb-2 mode. (neon_logbits): New function. (neon_three_same, neon_two_same, do_neon_dyadic_i_su) (do_neon_dyadic_i64_su, neon_imm_shift, do_neon_shl_imm) (do_neon_qshl_imm, neon_cmode_for_logic_imm, neon_bits_same_in_bytes) (neon_squash_bits, neon_is_quarter_float, neon_qfloat_bits) (neon_cmode_for_move_imm, neon_write_immbits, neon_invert_size) (do_neon_logic, do_neon_bitfield, neon_dyadic, do_neon_dyadic_if_su) (do_neon_dyadic_if_su_d, do_neon_dyadic_if_i, do_neon_dyadic_if_i_d) (do_neon_addsub_if_i, neon_exchange_operands, neon_compare) (do_neon_cmp, do_neon_cmp_inv, do_neon_ceq, neon_scalar_for_mul) (neon_mul_mac, do_neon_mac_maybe_scalar, do_neon_tst, do_neon_mul) (do_neon_qdmulh, do_neon_fcmp_absolute, do_neon_fcmp_absolute_inv) (do_neon_step, do_neon_abs_neg, do_neon_sli, do_neon_sri) (do_neon_qshlu_imm, do_neon_qmovn, do_neon_qmovun) (do_neon_rshift_sat_narrow, do_neon_rshift_sat_narrow_u, do_neon_movn) (do_neon_rshift_narrow, do_neon_shll, neon_cvt_flavour, do_neon_cvt) (neon_move_immediate, do_neon_mvn, neon_mixed_length) (do_neon_dyadic_long, do_neon_abal, neon_mac_reg_scalar_long) (do_neon_mac_maybe_scalar_long, do_neon_dyadic_wide, do_neon_vmull) (do_neon_ext, do_neon_rev, do_neon_dup, do_neon_mov) (do_neon_rshift_round_imm, do_neon_movl, do_neon_trn, do_neon_zip_uzp) (do_neon_sat_abs_neg, do_neon_pair_long, do_neon_recip_est) (do_neon_cls, do_neon_clz, do_neon_cnt, do_neon_swp, do_neon_tbl_tbx) (do_neon_ldm_stm, do_neon_ldr_str, do_neon_ld_st_interleave) (neon_alignment_bit, do_neon_ld_st_lane, do_neon_ld_dup) (do_neon_ldx_stx): New functions. Neon bit encoding and encoding helpers. (parse_neon_type): New function. Parse Neon type specifier. (opcode_lookup): Allow parsing of Neon type specifiers. (REGNUM2, REGSETH, REGSET2): New macros. (reg_names): Add new VFPv3 and Neon registers. (NUF, nUF, NCE, nCE): New macros for opcode table. (insns): More VFP registers allowed in fcpyd, fmdhr, fmdlr, fmrdh, fmrdl, fabsd, fnegd, fsqrtd, faddd, fsubd, fmuld, fdivd, fmacd, fmscd, fnmuld, fnmacd, fnmscd, fcmpd, fcmpzd, fcmped, fcmpezd, fmdrr, fmrrd. Add Neon instructions vaba, vhadd, vrhadd, vhsub, vqadd, vqsub, vrshl, vqrshl, vshl, vqshl{u}, vand, vbic, vorr, vorn, veor, vbsl, vbit, vbif, vabd, vmax, vmin, vcge, vcgt, vclt, vcle, vceq, vpmax, vpmin, vmla, vmls, vpadd, vadd, vsub, vtst, vmul, vqdmulh, vqrdmulh, vacge, vacgt, vaclt, vacle, vrecps, vrsqrts, vabs, vneg, v{r}shr, v{r}sra, vsli, vsri, vqshrn, vq{r}shr{u}n, v{r}shrn, vshll, vcvt, vmov, vmvn, vabal, vabdl, vaddl, vsubl, vmlal, vmlsl, vaddw, vsubw, v{r}addhn, v{r}subhn, vqdmlal, vqdmlsl, vqdmull, vmull, vext, vrev64, vrev32, vrev16, vdup, vmovl, v{q}movn, vzip, vuzp, vqabs, vqneg, vpadal, vpaddl, vrecpe, vrsqrte, vcls, vclz, vcnt, vswp, vtrn, vtbl, vtbx, vldm, vstm, vldr, vstr, vld[1234], vst[1234], fconst[sd], f[us][lh]to[sd], fto[us][lh][sd]. (tc_arm_regname_to_dw2regnum): Update for arm_reg_parse args. (arm_cpu_option_table): Add Neon and VFPv3 to Cortex-A8. (arm_option_cpu_value): Add vfp3 and neon. (aeabi_set_public_attributes): Support VFPv3 and NEON attributes. Fix VFPv1 attribute.	21 years ago
Julian Brown	edd40341c5	* gas/arm/copro.s: Avoid ldcl which encodes as a bad Neon instruction. * gas/arm/copro.d: Update accordingly. * gas/arm/neon-cond.s: New test. Conditional Neon opcodes in ARM mode. * gas/arm/neon-cond.d: Expected results of above. * gas/arm/neon-cov.s: New test. Coverage of Neon instructions. * gas/arm/neon-cov.d: Expected results of above. * gas/arm/neon-ldst-es.s: New test. Element and structure loads and stores. * gas/arm/neon-ldst-es.d: Expected results of above. * gas/arm/neon-ldst-rm.s: New test. Single and multiple register loads and stores. * gas/arm/neon-ldst-rm.d: Expected results of above. * gas/arm/neon-omit.s: New test. Omission of optional operands. * gas/arm/neon-omit.d: Expected results of above. * gas/arm/vfp1.d: Expect Neon syntax for some VFP instructions. * gas/arm/vfp1_t2.d: Likewise. * gas/arm/vfp1xD.d: Likewise. * gas/arm/vfp1xD_t2.d: Likewise. * gas/arm/vfp2.d: Likewise. * gas/arm/vfp2_t2.d: Likewise. * gas/arm/vfp3-32drs.s: New test. Extended D register range for VFP instructions. * gas/arm/vfp3-32drs.d: Expected results of above. * gas/arm/vfp3-const-conv.s: New test. VFPv3 constant-load and conversion instructions. * gas/arm/vfp3-const-conv.d: Expected results of above.	21 years ago
Andreas Jaeger	9ca26584e9	Add missing changelog entry	21 years ago
Bob Wilson	1946c96e94	* config/xtensa-relax.c (widen_spec_list): Use new "WIDE.<opcode>" syntax instead of hardcoded opcodes with ".w18" suffixes. (wide_branch_opcode): New. (build_transition): Use it to check for wide branch opcodes with either ".w18" or ".w15" suffixes.	21 years ago
Bob Wilson	5033a6459b	* config/tc-xtensa.c (xtensa_create_literal_symbol, xg_assemble_literal, xg_assemble_literal_space): Do not set the frag's is_literal flag.	21 years ago
Bob Wilson	395fa56f0f	* config/xtensa-relax.c (XCHAL_HAVE_WIDE_BRANCHES): Provide default.	21 years ago
Kazu Hirata	708587a480	* config/obj-coff.c, config/tc-arm.c, config/tc-bfin.c, config/tc-cris.c, config/tc-crx.c, config/tc-i386.c, config/tc-ia64.c, config/tc-maxq.c, config/tc-maxq.h, config/tc-mips.c, config/tc-msp430.c, config/tc-sh.c, config/tc-tic4x.c, config/tc-xtensa.c: Fix comment typos.	21 years ago
Paul Brook	8463be011b	2005-04-20 Paul Brook <paul@codesourcery.com> gas/ * config/tc-arm.c (s_arm_arch, s_arm_cpu, s_arm_fpu): Enable for all targets. (md_pseudo_table): Enable .arch, .cpu and .fpu for all targets. gas/testsuite/ * gas/arm/arch7.d: Remove skip. * gas/arm/svc.d: Ditto. * gas/arm/thumb2_bcond.d: Ditto. * gas/arm/thumb2_it_bad.d: Ditto.	21 years ago
Alan Modra	f26a5955b0	* Makefile.am (CPU_TYPES): Add maxq and mt. Sort. (CPU_OBJ_VALID): Change sense of COFF test to default to invalid. Make some cpus unsupported on ELF. Run "make dep-am". * Makefile.in: Regenerate.	21 years ago
Alan Modra	241a6c40c8	bfd/ * warning.m4 (--enable-werror, -build-warnings): Format help messages. * configure: Regenerate. binutils/ * configure: Regenerate. gas/ * configure.in (--enable-targets): Indent help message. * configure: Regenerate. gprof/ * configure: Regenerate. ld/ * configure: Regenerate. opcodes/ * configure: Regenerate.	21 years ago
H.J. Lu	bb8f592040	gas/ 2006-04-18 H.J. Lu <hongjiu.lu@intel.com> PR gas/2533 * config/tc-i386.c (i386_immediate): Check illegal immediate register operand. gas/testsuite/ 2006-04-18 H.J. Lu <hongjiu.lu@intel.com> PR gas/2533 * gas/i386/inval.s: Add test for illegal immediate register operand. * gas/i386/inval.l: Updated.	21 years ago
Alan Modra	64e7447423	* config/tc-i386.c: Formatting. (output_disp, output_imm): ISO C90 params.	21 years ago
Alan Modra	6cbe03fb0f	* frags.c (frag_offset_fixed_p): Constify args. * frags.h (frag_offset_fixed_p): Ditto.	21 years ago
Alan Modra	23d9d9dee5	* config/tc-dlx.h (tc_coff_symbol_emit_hook): Delete. (COFF_MAGIC): Delete.	21 years ago
Alan Modra	a37d486e3a	* config/tc-xc16x.h (TC_LINKRELAX_FIXUP): Delete.	21 years ago
Daniel Jacobowitz	e740356690	Update POTFILES.in.	21 years ago
Mark Mitchell	58ab4f3d64	* doc/as.texinfo: Mention that some .type syntaxes are not supported on all architectures.	21 years ago
Nick Clifton	10d1573802	Skip ELF specific tests on non-ELF ARM targets	21 years ago
Bob Wilson	482fd9f9bf	* config/tc-xtensa.c (emit_single_op): Do not relax MOVI instructions when such transformations have been disabled.	21 years ago
Bob Wilson	05d5814545	* config/tc-xtensa.c (xg_assemble_vliw_tokens): Record loop target symbols in RELAX[_CHECK]_ALIGN_NEXT_OPCODE frags. (xtensa_fix_close_loop_end_frags): Use the recorded values instead of decoding the loop instructions. Remove current_offset variable. (xtensa_fix_short_loop_frags): Likewise. (min_bytes_to_other_loop_end): Remove current_offset argument.	21 years ago
Arnold Metselaar	9e75b3faad	removed z80_optimize_expr; redundant since 2006-04-04	21 years ago
Nick Clifton	d727e8c26e	Add support for attiny261, attiny461, attiny861, attiny25, attiny45, attiny85, attiny24, attiny44, attiny84, at90pwm2, at90pwm3, atmega164, atmega324, atmega644, atmega329, atmega3290, atmega649, atmega6490, atmega406, atmega640, atmega1280, atmega1281, at90can32, at90can64, at90usb646, at90usb647, at90usb1286 and at90usb1287. Move atmega48 and atmega88 from AVR_ISA_M8 to AVR_ISA_PWMx.	21 years ago
Paul Brook	d252fddeb1	2006-04-07 Paul Brook <paul@codesourcery.com> * config/tc-arm.c (parse_operands): Set default error message.	21 years ago
Paul Brook	ab1eb5fea7	2006-04-07 Paul Brook <paul@codesourcery.com> * config/tc-arm.c (parse_tb): Set inst.error before returning FAIL.	21 years ago
Paul Brook	7ae2971b7a	2006-04-07 Paul Brook <paul@codesourcery.com> gas/ * config/tc-arm.c (md_apply_fix): Set H bit on blx instruction. gas/testsuite/ * gas/arm/blx-local.d: New test. * gas/arm/blx-local.d: New test.	21 years ago
Paul Brook	53365c0d76	2006-04-07 Paul Brook <paul@codesourcery.com> gas/ * config/tc-arm.c (THUMB2_LOAD_BIT): Define. (move_or_literal_pool): Handle Thumb-2 instructions. (do_t_ldst): Call move_or_literal_pool for =N addressing modes. gas/testsuite/ * gas/arm/thumb2_pool.d: New test. * gas/arm/thumb2_pool.s: New test.	21 years ago
Alan Modra	45aa61fe2e	PR 2512. * config/tc-i386.c (match_template): Move 64-bit operand tests inside loop.	21 years ago
Carlos O'Donell	108a6f8eb4	2006-04-06 Carlos O'Donell <carlos@codesourcery.com>	21 years ago
Alan Modra	ec651a3b25	* frags.c (frag_offset_fixed_p): Reinitialise offset before second scan.	21 years ago

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3717 Commits (251533c9556bbb894524588ff15ed02ce645f264)