binutils-gdb

Commit Graph

Author	SHA1	Message	Date
Richard Sandiford	2442d8466e	[AArch64][SVE 24/32] Add AARCH64_OPND_SVE_PATTERN_SCALED Some SVE instructions count the number of elements in a given vector pattern and allow a scale factor of [1, 16] to be applied to the result. This scale factor is written ", MUL #n", where "MUL" is a new operator. E.g.: UQINCD X0, POW2, MUL #2 This patch adds support for this kind of operand. All existing operators were shifts of some kind, so there was a natural range of [0, 63] regardless of context. This was then narrowered further by later checks (e.g. to [0, 31] when used for 32-bit values). In contrast, MUL doesn't really have a natural context-independent range. Rather than pick one arbitrarily, it seemed better to make the "shift" amount a full 64-bit value and leave the range test to the usual operand-checking code. I've rearranged the fields of aarch64_opnd_info so that this doesn't increase the size of the structure (although I don't think its size is critical anyway). include/ * opcode/aarch64.h (AARCH64_OPND_SVE_PATTERN_SCALED): New aarch64_opnd. (AARCH64_MOD_MUL): New aarch64_modifier_kind. (aarch64_opnd_info): Make shifter.amount an int64_t and rearrange the fields. opcodes/ * aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for AARCH64_OPND_SVE_PATTERN_SCALED. * aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind. * aarch64-opc.c (fields): Add a corresponding entry. (set_multiplier_out_of_range_error): New function. (aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL. (operand_general_constraint_met_p): Handle AARCH64_OPND_SVE_PATTERN_SCALED. (print_register_offset_address): Use PRIi64 to print the shift amount. (aarch64_print_operand): Likewise. Handle AARCH64_OPND_SVE_PATTERN_SCALED. * aarch64-opc-2.c: Regenerate. * aarch64-asm.h (ins_sve_scale): New inserter. * aarch64-asm.c (aarch64_ins_sve_scale): New function. * aarch64-asm-2.c: Regenerate. * aarch64-dis.h (ext_sve_scale): New inserter. * aarch64-dis.c (aarch64_ext_sve_scale): New function. * aarch64-dis-2.c: Regenerate. gas/ * config/tc-aarch64.c (SHIFTED_MUL): New parse_shift_mode. (parse_shift): Handle it. Reject AARCH64_MOD_MUL for all other shift modes. Skip range tests for AARCH64_MOD_MUL. (process_omitted_operand): Handle AARCH64_OPND_SVE_PATTERN_SCALED. (parse_operands): Likewise.	10 years ago
Richard Sandiford	245d2e3fe8	[AArch64][SVE 23/32] Add SVE pattern and prfop operands The SVE instructions have two enumerated operands: one to select a vector pattern and another to select a prefetch operation. The latter is a cut-down version of the base AArch64 prefetch operation. Both types of operand can also be specified as raw enum values such as #31. Reserved values can only be specified this way. If it hadn't been for the pattern operand, I would have been tempted to use the existing parsing for prefetch operations and add extra checks for SVE. However, since the patterns needed new enum parsing code anyway, it seeemed cleaner to reuse it for the prefetches too. Because of the small number of enum values, I don't think we'd gain anything by using hash tables. include/ * opcode/aarch64.h (AARCH64_OPND_SVE_PATTERN): New aarch64_opnd. (AARCH64_OPND_SVE_PRFOP): Likewise. (aarch64_sve_pattern_array): Declare. (aarch64_sve_prfop_array): Likewise. opcodes/ * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP. * aarch64-opc.h (FLD_SVE_pattern): New aarch64_field_kind. (FLD_SVE_prfop): Likewise. * aarch64-opc.c: Include libiberty.h. (aarch64_sve_pattern_array): New variable. (aarch64_sve_prfop_array): Likewise. (fields): Add entries for FLD_SVE_pattern and FLD_SVE_prfop. (aarch64_print_operand): Handle AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP. * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Likewise. * aarch64-opc-2.c: Likewise. gas/ * config/tc-aarch64.c (parse_enum_string): New function. (po_enum_or_fail): New macro. (parse_operands): Handle AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP.	10 years ago
Richard Sandiford	d50c751e00	[AArch64][SVE 22/32] Add qualifiers for merging and zeroing predication This patch adds qualifiers to represent /z and /m suffixes on predicate registers. include/ * opcode/aarch64.h (AARCH64_OPND_QLF_P_Z): New aarch64_opnd_qualifier. (AARCH64_OPND_QLF_P_M): Likewise. opcodes/ * aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for AARCH64_OPND_QLF_P_[ZM]. (aarch64_print_operand): Print /z and /m where appropriate. gas/ * config/tc-aarch64.c (vector_el_type): Add NT_zero and NT_merge. (parse_vector_type_for_operand): Assert that the skipped character is a '.'. (parse_predication_for_operand): New function. (parse_typed_reg): Parse /z and /m suffixes for predicate registers. (vectype_to_qualifier): Handle NT_zero and NT_merge.	10 years ago
Richard Sandiford	f11ad6bc0f	[AArch64][SVE 21/32] Add Zn and Pn registers This patch adds the Zn and Pn registers, and associated fields and operands. include/ * opcode/aarch64.h (AARCH64_OPND_CLASS_SVE_REG): New aarch64_operand_class. (AARCH64_OPND_CLASS_PRED_REG): Likewise. (AARCH64_OPND_SVE_Pd, AARCH64_OPND_SVE_Pg3, AARCH64_OPND_SVE_Pg4_5) (AARCH64_OPND_SVE_Pg4_10, AARCH64_OPND_SVE_Pg4_16) (AARCH64_OPND_SVE_Pm, AARCH64_OPND_SVE_Pn, AARCH64_OPND_SVE_Pt) (AARCH64_OPND_SVE_Za_5, AARCH64_OPND_SVE_Za_16, AARCH64_OPND_SVE_Zd) (AARCH64_OPND_SVE_Zm_5, AARCH64_OPND_SVE_Zm_16, AARCH64_OPND_SVE_Zn) (AARCH64_OPND_SVE_Zn_INDEX, AARCH64_OPND_SVE_ZnxN) (AARCH64_OPND_SVE_Zt, AARCH64_OPND_SVE_ZtxN): New aarch64_opnds. opcodes/ * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands. * aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5) (FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt) (FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16) (FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds. * aarch64-opc.c (fields): Add corresponding entries here. (operand_general_constraint_met_p): Check that SVE register lists have the correct length. Check the ranges of SVE index registers. Check for cases where p8-p15 are used in 3-bit predicate fields. (aarch64_print_operand): Handle the new SVE operands. * aarch64-opc-2.c: Regenerate. * aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters. * aarch64-asm.c (aarch64_ins_sve_index): New function. (aarch64_ins_sve_reglist): Likewise. * aarch64-asm-2.c: Regenerate. * aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors. * aarch64-dis.c (aarch64_ext_sve_index): New function. (aarch64_ext_sve_reglist): Likewise. * aarch64-dis-2.c: Regenerate. gas/ * config/tc-aarch64.c (NTA_HASVARWIDTH): New macro. (AARCH64_REG_TYPES): Add ZN and PN. (get_reg_expected_msg): Handle them. (parse_vector_type_for_operand): Add a reg_type parameter. Skip the width for Zn and Pn registers. (parse_typed_reg): Extend vector handling to Zn and Pn. Update the call to parse_vector_type_for_operand. Set HASVARTYPE for Zn and Pn, expecting the width to be 0. (parse_vector_reg_list): Restrict error about [BHSD]nn operands to REG_TYPE_VN. (vectype_to_qualifier): Use S_[BHSD] qualifiers for NTA_HASVARWIDTH. (parse_operands): Handle the new Zn and Pn operands. (REGSET16): New macro, split out from... (REGSET31): ...here. (reg_names): Add Zn and Pn entries.	10 years ago
Richard Sandiford	0c608d6b62	[AArch64][SVE 20/32] Add support for tied operands SVE has some instructions in which the same register appears twice in the assembly string, once as an input and once as an output. This patch adds a general mechanism for that. The patch needs to add new information to the instruction entries. One option would have been to extend the flags field of the opcode to 64 bits (since we already rely on 64-bit integers being available on the host). However, the _INSN macros mean that it's easy to add new information as top-level fields without affecting the existing table entries too much. Going for that option seemed to give slightly neater code. include/ opcode/aarch64.h (aarch64_opcode): Add a tied_operand field. (AARCH64_OPDE_UNTIED_OPERAND): New aarch64_operand_error_kind. opcodes/ * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN) (_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN) (V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field. * aarch64-opc.c (aarch64_match_operands_constraint): Check for tied operands. gas/ * config/tc-aarch64.c (output_operand_error_record): Handle AARCH64_OPDE_UNTIED_OPERAND.	10 years ago
Richard Sandiford	01dbfe4c0e	[AArch64][SVE 19/32] Refactor address-printing code SVE adds addresses in which the base or offset are vector registers. The addresses otherwise have the same kind of form as normal AArch64 addresses, including things like SXTW with or without a shift, UXTW with or without a shift, and LSL. This patch therefore refactors the address-printing code so that it can cope with both scalar and vector registers. opcodes/ * aarch64-opc.c (get_offset_int_reg_name): New function. (print_immediate_offset_address): Likewise. (print_register_offset_address): Take the base and offset registers as parameters. (aarch64_print_operand): Update caller accordingly. Use print_immediate_offset_address.	10 years ago
Richard Sandiford	72e9f31937	[AArch64][SVE 18/32] Tidy definition of aarch64-opc.c:int_reg Use a macro to define 31 regular registers followed by a supplied value for 0b11111. The SVE code will also use this for vector base and offset registers. opcodes/ * aarch64-opc.c (BANK): New macro. (R32, R64): Take a register number as argument (int_reg): Use BANK.	10 years ago
Richard Sandiford	8a7f0c1b5a	[AArch64][SVE 17/32] Add a prefix parameter to print_register_list This patch generalises the interface to print_register_list so that it can print register lists involving SVE z registers as well as AdvSIMD v ones. opcodes/ * aarch64-opc.c (print_register_list): Add a prefix parameter. (aarch64_print_operand): Update accordingly.	10 years ago
Richard Sandiford	aa2aa4c694	[AArch64][SVE 16/32] Use specific insert/extract methods for fpimm FPIMM used the normal "imm" insert/extract methods, with a specific test for FPIMM in the extract method. SVE needs to use the same extractors, so rather than add extra checks for specific operand types, it seemed cleaner to use a separate insert/extract method. opcodes/ * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm for FPIMM. * aarch64-asm.h (ins_fpimm): New inserter. * aarch64-asm.c (aarch64_ins_fpimm): New function. * aarch64-asm-2.c: Regenerate. * aarch64-dis.h (ext_fpimm): New extractor. * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test. (aarch64_ext_fpimm): New function. * aarch64-dis-2.c: Regenerate.	10 years ago
Richard Sandiford	b5464a6825	[AArch64][SVE 15/32] Add {insert,extract}_all_fields helpers Several of the SVE operands use the aarch64_operand fields array to store the fields that make up the operand, rather than hard-coding the names in the C code. This patch adds helpers for inserting and extracting those fields. opcodes/ * aarch64-asm.c: Include libiberty.h. (insert_fields): New function. (aarch64_ins_imm): Use it. * aarch64-dis.c (extract_fields): New function. (aarch64_ext_imm): Use it.	10 years ago
Richard Sandiford	42408347b8	[AArch64][SVE 14/32] Make aarch64_logical_immediate_p take an element size SVE supports logical immediate operations on 8-bit, 16-bit and 32-bit elements, treating them as aliases of operations on 64-bit elements in which the immediate is replicated. This patch therefore replaces the "32-bit/64-bit" input to aarch64_logical_immediate_p with a more general "number of bytes" input. opcodes/ * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32 with an esize parameter. (operand_general_constraint_met_p): Update accordingly. Fix misindented code. * aarch64-asm.c (aarch64_ins_limm): Update call to aarch64_logical_immediate_p.	10 years ago
Richard Sandiford	4989adac84	[AArch64][SVE 13/32] Add an F_STRICT flag SVE predicate operands can appear in three forms: 1. unsuffixed: "Pn" 2. with a predication type: "Pn/[ZM]" 3. with a size suffix: "Pn.[BHSD]" No variation is allowed: unsuffixed operands cannot have a (redundant) suffix, and the suffixes can never be dropped. Unsuffixed Pn are used in LDR and STR, but they are also used for Pg operands in cases where the result is scalar and where there is therefore no choice to be made between "merging" and "zeroing". This means that some Pg operands have suffixes and others don't. It would be possible to use context-sensitive parsing to handle this difference. The tc-aarch64.c code would then raise an error if the wrong kind of suffix is used for a particular instruction. However, we get much more user-friendly error messages if we parse all three forms for all SVE instructions and record the suffix as a qualifier. The normal qualifier matching code can then report cases where the wrong kind of suffix is used. This is a slight extension of existing usage, which really only checks for the wrong choice of suffix within a particular kind of suffix. The only catch is a that a "NIL" entry in the qualifier list specifically means "no suffix should be present" (case 1 above). NIL isn't a wildcard here. It also means that an instruction that requires all-NIL qualifiers can fail to match (because a suffix was supplied when it shouldn't have been); this requires a slight change to find_best_match. This patch adds an F_STRICT flag to select this behaviour. The flag will be set for all SVE instructions. The behaviour for other instructions doesn't change. include/ * opcode/aarch64.h (F_STRICT): New flag. opcodes/ * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT. gas/ * config/tc-aarch64.c (find_best_match): Simplify, allowing an instruction with all-NIL qualifiers to fail to match.	10 years ago
Richard Sandiford	bd11d5d837	[AArch64][SVE 02/32] Avoid hard-coded limit in indented_print The maximum indentation needed by aarch64-gen.c grows as more instructions are added to aarch64-tbl.h. Rather than having to increase the indentation limit to a higher value, it seemed better to replace it with "%s". opcodes/ aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.	10 years ago
Claudiu Zissulescu	f807f43d7e	[ARC] Disassemble correctly extension instructions. For each MAJOR-MINOR opcode tuple, we can have either a 3-operand, or 2-operand, or a single operand instruction format, depending on the values present in i-field, and a-field. The disassembler is reading the section containing the extension instruction format and stores them in a table. Each table element represents a linked list with encodings for a particular MAJOR-MINOR tuple. The current implementation checks only against the first element of the list, hence, the issue. This patch is walking the linked list until empty or finds an opcode match. It also adds a test outlining the found problem. opcodes/ 2016-09-15 Claudiu Zissulescu <claziss@synopsys.com> * arc-dis.c (find_format): Walk the linked list pointed by einsn. gas/ 2016-09-15 Claudiu Zissulescu <claziss@synopsys.com> * testsuite/gas/arc/textinsnxop.d: New file. * testsuite/gas/arc/textinsnxop.s: Likewise.	10 years ago
Peter Bergner	fd486b633e	Modify POWER9 support to match final ISA 3.0 documentation. opcodes/ * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic. <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool, xor3>: Delete mnemonics. <cp_abort>: Rename mnemonic from ... <cpabort>: ...to this. <setb>: Change to a X form instruction. <sync>: Change to 1 operand form. <copy>: Delete mnemonic. <copy_first>: Rename mnemonic from ... <copy>: ...to this. <paste, paste.>: Delete mnemonics. <paste_last>: Rename mnemonic from ... <paste.>: ...to this. gas/ * testsuite/gas/ppc/power9.d <slbiag, cpabort> New tests. <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool, xor3, cp_abort, copy_first, paste, paste_last, sync>: Remove tests. <copy, paste.>: Update tests. * testsuite/gas/ppc/power9.s: Likewise.	10 years ago
Anton Kolesov	dce084426d	Stop the ARC disassembler from seg-faulting if initialised without a BFD present. * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.	10 years ago
Andreas Krebbel	952c3f51ac	S/390: Add alternate processor names. This patch adds alternate CPU names which adhere to the number of the architecture document. So instead of having z196, zEC12, and z13 you can use arch9, arch10, and arch11. The old cpu names stay valid and should primarily be used. The alternate names are supposed to improve compatibility with the IBM XL compiler toolchain which uses the arch numbering. opcodes/ChangeLog: 2016-09-12 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * s390-mkopc.c (main): Support alternate arch strings. gas/ChangeLog: 2016-09-12 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * config/tc-s390.c (s390_parse_cpu): Support alternate arch strings. * doc/as.texinfo: Document new arch strings. * doc/c-s390.texi: Likewise.	10 years ago
Patrick Steuer	8b71537b6b	S/390: Fix kmctr instruction type. opcodes/ChangeLog: 2016-09-12 Patrick Steuer <steuer@linux.vnet.ibm.com> * s390-opc.txt: Fix kmctr instruction type. gas/ChangeLog: 2016-09-12 Patrick Steuer <steuer@linux.vnet.ibm.com> * testsuite/gas/s390/zarch-z196.d: Adjust testcase.	10 years ago
H.J. Lu	5b64d091e9	X86: Allow additional ISAs for IAMCU in assembler Originally only Pentium integer instructions are allowed for IAMCU. This patch removes such a restriction. For example, 387 and SSE2 instructions can be enabled by passing "-march=iamcu+sse2+387" to assembler. gas/ * config/tc-i386.c (valid_iamcu_cpu_flags): Removed. (set_cpu_arch): Updated. (md_parse_option): Likewise. * testsuite/gas/i386/i386.exp: Run iamcu-4 and iamcu-5. Remove iamcu-inval-2 and iamcu-inval-3. * testsuite/gas/i386/iamcu-4.d: New file. * testsuite/gas/i386/iamcu-4.s: Likewise. * testsuite/gas/i386/iamcu-5.d: Likewise. * testsuite/gas/i386/iamcu-5.s: Likewise. * testsuite/gas/i386/iamcu-inval-2.l: Removed. * testsuite/gas/i386/iamcu-inval-2.s: Likewise. * testsuite/gas/i386/iamcu-inval-3.l: Likewise. * testsuite/gas/i386/iamcu-inval-3.s: Likewise. opcodes/ * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS. * i386-init.h: Regenerated.	10 years ago
Cupertino Miranda	7763838e99	Fixed issue with NULL pointer access on header var. Variable "header" in function is set conditionally, but was accessed without verifying if pointer was NULL. opcodes/ChangeLog: Cupertino Miranda <cmiranda@synopsys.com> * opcodes/arc-dis.c (print_insn_arc): Changed.	10 years ago
Jose E. Marchesi	1b8b65328f	opcodes, gas: fix mnemonic of sparc camellia_fl This patch fixes a typo in the mnemonic of the camellia_fl instruction, which was implemented before as camellia_fi. gas/ChangeLog: 2016-08-26 Jose E. Marchesi <jose.marchesi@oracle.com> * testsuite/gas/sparc/crypto.d: Rename invalid opcode camellia_fi to camellia_fl. * testsuite/gas/sparc/crypto.s: Likewise. opcodes/ChangeLog: 2016-08-26 Jose E. Marchesi <jose.marchesi@oracle.com> * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi -> camellia_fl.	10 years ago
Thomas Preud'homme	1a336194b7	Add missing ARMv8-M special registers 2016-08-26 Thomas Preud'homme <thomas.preudhomme@arm.com> gas/ * config/tc-arm.c (v7m_psrs): Add MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS, FAULTMASK_NS, CONTROL_NS, SP_NS and their lowecase counterpart special registers. Write register identifier in hex. * testsuite/gas/arm/archv8m-cmse-msr.s: Reorganize tests per operation, special register and then case. Use different register for each operation. Add tests for new special registers. * testsuite/gas/arm/archv8m-cmse-msr-base.d: Adapt expected result accordingly. * testsuite/gas/arm/archv8m-cmse-msr-main.d: Likewise. * testsuite/gas/arm/archv8m-main-dsp-4.d: Likewise. opcodes/ * arm-dis.c (psr_name): Use hex as case labels. Add detection for MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS, FAULTMASK_NS, CONTROL_NS and SP_NS special registers.	10 years ago
H.J. Lu	6b40c46231	X86: Add ptwrite instruction Implement ptwrite instruction defined in Intel64 and IA-32 Architectures Software Developer’s Manual, June 2016. gas/ * config/tc-i386.c (cpu_arch): Add .ptwrite. * doc/c-i386.texi: Document ptwrite and .ptwrite. * testsuite/gas/i386/i386.exp: Run ptwrite, ptwrite-intel, x86-64-ptwrite and x86-64-ptwrite-intel. * testsuite/gas/i386/ptwrite-intel.d: New file. * testsuite/gas/i386/ptwrite.d: Likewise. * testsuite/gas/i386/ptwrite.s: Likewise. * testsuite/gas/i386/x86-64-ptwrite-intel.d: Likewise. * testsuite/gas/i386/x86-64-ptwrite.d: Likewise. * testsuite/gas/i386/x86-64-ptwrite.s: Likewise. opcodes/ * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New. (PREFIX_MOD_3_0FAE_REG_4): Likewise. (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and PREFIX_MOD_3_0FAE_REG_4. (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and PREFIX_MOD_3_0FAE_REG_4. * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS. (cpu_flags): Add CpuPTWRITE. * i386-opc.h (CpuPTWRITE): New. (i386_cpu_flags): Add cpuptwrite. * i386-opc.tbl: Add ptwrite instruction. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.	10 years ago
Anton Kolesov	ab548d2db9	[ARC] C++ compatibility for arc-dis.h opcodes/ 2016-08-24 Anton Kolesov <Anton.Kolesov@synopsys.com> * arc-dis.h: Wrap around in extern "C". Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>	10 years ago
Richard Sandiford	344bde0a7f	[AArch64] Add V8_2_INSN macro For consistency with the previous two patches, this one adds a macro for the two ARMv8.2 table entries. Both table entries need a non-null aarch64_op field. I haven't added macros for the RAS and STAT_PROFILE entries since there's only one of each. The series isn't getting rid of braced entries altogether, so I've only looked at replacing things that occur more than once. opcodes/ * aarch64-tbl.h (V8_2_INSN): New macro. (aarch64_opcode_table): Use it.	10 years ago
Richard Sandiford	5ce912d801	[AArch64] Make more use of CORE/FP/SIMD_INSN After the previous patch, this one makes all CORE, FP and SIMD table entries with null "verify" fields use the associated macros. opcodes/ * aarch64-tbl.h (aarch64_opcode_table): Make more use of CORE_INSN, __FP_INSN and SIMD_INSN.	10 years ago
Richard Sandiford	9d30b0bdab	[AArch64] Add OP parameter to aarch64-tbl.h macros Nick recently wrapped most of aarch64-tbl.h entries in macros like CORE_INSN. These new macros assumed that the aarch64_op "op" field of aarch64_opcode is 0 and that the new "verifier" field is NULL. However, there are a lot of CORE, SIMD and FP insns whose table entries need a nonzero aarch64_op field, so these entries continued to use a braced list instead of a macro. This makes the table entries less consistent and means that there are still quite a few braced entries that need to be updated when making further changes to the aarch64_opcode structure. I think the number of entries that need a nonzero aarch64_op field is high enough to justify having an explicit aarch64_op entry for all CORE, SIMD and FP entries. This patch adds one and updates all existing uses of the macros. A following patch makes more use of the macros. I've followed existing practice by using 0 instead of OP_NIL for empty aarch64_op fields. Empty fields are still the norm and you need to know what the fields are when reading the table anyway, so it was hard to justify an additional patch to replace all 0 op fields with OP_NIL. opcodes/ * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter. (aarch64_opcode_table): Update uses accordingly.	10 years ago
Andrew Jenner	dfdaec14b0	Fix some PowerPC VLE BFD issues and add some PowerPC VLE instructions. bfd/ * elf32-ppc.c (is_branch_reloc): Recognise VLE branch relocations. (ppc_elf_howto_raw): Fix dst_mask of R_PPC_VLE_REL15. (ppc_elf_vle_split16): Clear field before inserting. opcodes/ * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and 'e_cmplwi' to 'e_cmpli' instead. (OPVUPRT, OPVUPRT_MASK): Define. (powerpc_opcodes): Add E200Z4 insns. (vle_opcodes): Add context save/restore insns. include/ * opcode/ppc.h (PPC_OPCODE_E200Z4): New define.	10 years ago
Maciej W. Rozycki	7bd374a44d	MIPS/GAS: Implement microMIPS branch/jump compaction Convert microMIPS branches and jumps whose delay slot would be filled by a generated NOP instruction to the corresponding compact form where one exists, in a manner similar to MIPS16 JR->JRC and JALR->JALRC swap. Do so even where the transformation switches from a 16-bit to a 32-bit branch encoding for no benefit in code size reduction, as this is still advantageous. This is because a branch/NOP pair takes 2 pipeline slots or a 2-cycle completion latency except in superscalar implementations. Whereas a compact branch may or may not stall on its target fetch, so it will at most have a 2-cycle completion latency and may have only 1 even in scalar implementations, and in superscalar implementations it is expected to have no worse latency as a branch/NOP pair has. Also it won't stall and therefore take the extra latency cycle in the not-taken case. Technically this is the same as MIPS16 compaction: for the qualifying instruction encodings the APPEND_ADD_COMPACT machine code generation method is selected where APPEND_ADD_WITH_NOP otherwise would and tells the code generator in `append_insn' to convert the regular form of an instruction to its corresponding compact form. For this the opcode is tweaked as necessary and the microMIPS opcode table is scanned for the matching updated instruction. A non-$0 `rt' operand to BEQ and BNE instructions is moved to the `rs' operand field of BEQZC and BNEZC encodings as required. Unlike with MIPS16 compaction however we need to handle out-of-distance branch relaxation as well. We do this by deferring the generation of any delay-slot NOP required to relaxation made in `md_convert_frag', by converting the APPEND_ADD_WITH_NOP machine code generation to APPEND_ADD where a relaxed instruction is recorded. Relaxation then, depending on actual code produced, chooses between either using a compact branch or jump encoding and emitting the NOP outstanding if no compact encoding is possible. For code simplicity's sake the relaxation pass is retained even if the principle of preferring a compact encoding to a 16-bit branch/NOP pair means, in the absence of out-of-range branch relaxation, that a single compact branch machine code instruction will eventually be produced from a given assembly source instruction. gas/ * config/tc-mips.c (RELAX_MICROMIPS_ENCODE): Add `nods' flag. (RELAX_MICROMIPS_RELAX32, RELAX_MICROMIPS_TOOFAR16) (RELAX_MICROMIPS_MARK_TOOFAR16, RELAX_MICROMIPS_CLEAR_TOOFAR16) (RELAX_MICROMIPS_TOOFAR32, RELAX_MICROMIPS_MARK_TOOFAR32) (RELAX_MICROMIPS_CLEAR_TOOFAR32): Shift bits. (get_append_method): Also return APPEND_ADD_COMPACT for microMIPS instructions. (find_altered_mips16_opcode): Exclude macros from matching. Factor code out... (find_altered_opcode): ... to this new function. (find_altered_micromips_opcode): New function. (frag_branch_delay_slot_size): Likewise. (append_insn): Handle microMIPS branch/jump compaction. (macro_start): Likewise. (relaxed_micromips_32bit_branch_length): Likewise. (md_convert_frag): Likewise. * testsuite/gas/mips/micromips.s: Add conditional explicit NOPs for delay slot filling. * testsuite/gas/mips/micromips-b16.s: Add explicit NOPs for delay slot filling. * testsuite/gas/mips/micromips-size-1.s: Likewise. * testsuite/gas/mips/micromips.l: Adjust line numbers. * testsuite/gas/mips/micromips-warn.l: Likewise. * testsuite/gas/mips/micromips-size-1.l: Likewise. * testsuite/gas/mips/micromips.d: Adjust padding. * testsuite/gas/mips/micromips-trap.d: Likewise. * testsuite/gas/mips/micromips-insn32.d: Likewise. * testsuite/gas/mips/micromips-noinsn32.d: Likewise. * testsuite/gas/mips/micromips@beq.d: Update patterns for branch/jump compaction. * testsuite/gas/mips/micromips@bge.d: Likewise. * testsuite/gas/mips/micromips@bgeu.d: Likewise. * testsuite/gas/mips/micromips@blt.d: Likewise. * testsuite/gas/mips/micromips@bltu.d: Likewise. * testsuite/gas/mips/micromips@branch-misc-4.d: Likewise. * testsuite/gas/mips/micromips@branch-misc-4-64.d: Likewise. * testsuite/gas/mips/micromips@branch-misc-5.d: Likewise. * testsuite/gas/mips/micromips@branch-misc-5pic.d: Likewise. * testsuite/gas/mips/micromips@branch-misc-5-64.d: Likewise. * testsuite/gas/mips/micromips@branch-misc-5pic-64.d: Likewise. * testsuite/gas/mips/micromips@jal-svr4pic-local.d: Likewise. * testsuite/gas/mips/micromips@jal-svr4pic-local-n32.d: Likewise. * testsuite/gas/mips/micromips@jal-svr4pic-local-n64.d: Likewise. * testsuite/gas/mips/micromips@loc-swap.d: Likewise. * testsuite/gas/mips/micromips@loc-swap-dis.d: Likewise. * testsuite/gas/mips/micromips@relax.d: Likewise. * testsuite/gas/mips/micromips@relax-at.d: Likewise. * testsuite/gas/mips/micromips@relax-swap3.d: Likewise. * testsuite/gas/mips/branch-extern-2.d: Likewise. * testsuite/gas/mips/branch-extern-4.d: Likewise. * testsuite/gas/mips/branch-section-2.d: Likewise. * testsuite/gas/mips/branch-section-4.d: Likewise. * testsuite/gas/mips/branch-weak-2.d: Likewise. * testsuite/gas/mips/branch-weak-5.d: Likewise. * testsuite/gas/mips/micromips-branch-absolute.d: Likewise. * testsuite/gas/mips/micromips-branch-absolute-n32.d: Likewise. * testsuite/gas/mips/micromips-branch-absolute-n64.d: Likewise. * testsuite/gas/mips/micromips-branch-absolute-addend.d: Likewise. * testsuite/gas/mips/micromips-branch-absolute-addend-n32.d: Likewise. * testsuite/gas/mips/micromips-branch-absolute-addend-n64.d: Likewise. * testsuite/gas/mips/micromips-compact.d: New test. * testsuite/gas/mips/mips.exp: Run the new test. ld/ * testsuite/ld-mips-elf/micromips-branch-absolute.d: Update patterns for branch compaction. * testsuite/ld-mips-elf/micromips-branch-absolute-addend.d: Likewise. opcodes/ * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b", "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to "j".	10 years ago
Graham Markall	db18dbabad	Begin implementing ARC NPS-400 Accelerator instructions opcodes * arc-nps400-tbl.h: Change block comments to GNU format. * arc-dis.c: Add new globals addrtypenames, addrtypenames_max, and addtypeunknown. (get_addrtype): New function. (print_insn_arc): Print colons and address types when required. * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to define insert and extract functions for all address types. (arc_operands): Add operands for colon and all address types. * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table. * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands, insert_nps_bd_num_buff and extract_nps_bd_num_buff functions. * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table. * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands, insert_nps_pmu_num_job and extract_nps_pmu_num_job functions. include * opcode/arc.h: Add ARC_OPERAND_ADDRTYPE, ARC_OPERAND_COLON. Add the arc_nps_address_type enum and ARC_NUM_ADDRTYPES. * opcode/arc.h: Add BMU to insn_class_t enum. * opcode/arc.h: Add PMU to insn_class_t enum. gas * config/tc-arc.c: Add new global arc_addrtype_hash. Define O_colon and O_addrtype. (debug_exp): Add O_colon and O_addrtype. (tokenize_arguments): Handle colon and address type tokens. (declare_addrtype): New function. (md_begin): Initialise arc_addrtype_hash. (arc_parse_name): Add lookup of address types. (assemble_insn): Handle colons and address types by ignoring them. * testsuite/gas/arc/nps400-8.s: New file. * testsuite/gas/arc/nps400-8.d: New file. * testsuite/gas/arc/nps400-8.s: Add PMU instruction tests. * testsuite/gas/arc/nps400-8.d: Add expected PMU instruction output.	10 years ago
H.J. Lu	fecd57f9f1	Set BFD_VERSION to 2.27.51 bfd/ * version.m4 (BFD_VERSION): Set to 2.27.51. * configure: Regenerated. binutils/ * configure: Regenerated. gas/ * configure: Regenerated. gprof/ * configure: Regenerated. ld/ * configure: Regenerated. opcodes/ * configure: Regenerated.	10 years ago
Claudiu Zissulescu	37fd5ef3ec	Add support to the ARC disassembler for selecting instruction classes. gas * testsuite/gas/arc/dsp.d: New file. * testsuite/gas/arc/dsp.s: Likewise. * testsuite/gas/arc/fpu.d: Likewise. * testsuite/gas/arc/fpu.s: Likewise. * testsuite/gas/arc/ext2op.d: Add specific disassembler option. * testsuite/gas/arc/ext3op.d: Likewise. * testsuite/gas/arc/tdpfp.d: Likewise. * testsuite/gas/arc/tfpuda.d: Likewise. opcodes * arc-dis.c (skipclass): New structure. (decodelist): New variable. (is_compatible_p): New function. (new_element): Likewise. (skip_class_p): Likewise. (find_format_from_table): Use skip_class_p function. (find_format): Decode first the extension instructions. (print_insn_arc): Select either ARCEM or ARCHS based on elf e_flags. (parse_option): New function. (parse_disassembler_options): Likewise. (print_arc_disassembler_options): Likewise. (print_insn_arc): Use parse_disassembler_options function. Proper select ARCv2 cpu variant. * disassemble.c (disassembler_usage): Add ARC disassembler options. binutils* doc/binutils.texi (objdump): Add ARC disassembler options. * testsuite/binutils-all/arc/dsp.s: New file. * testsuite/binutils-all/arc/objdump.exp: Likewise. include * dis-asm.h: Declare print_arc_disassembler_options.	10 years ago
Maciej W. Rozycki	92281a5b06	MIPS/opcodes: Address issues with NAL disassembly Address issues with the disassembly of the NAL assembly idiom and R6 instruction introduced with commit `7361da2c95` ("Add support for MIPS R6.") and then further tweaked with commit `b9121b573e` ("Add in a JALRC alias and fix the NAL instruction."). As from R6 this instruction has replaced the encoding of `bltzal $0, . + 4' as the solely supported form of the former BLTZAL instruction for the regular MIPS ISA. The instruction is marked as an alias only in our regular MIPS opcode table, making it fail to disassemble in R6 code if the `no-aliases' machine option has been passed to `objdump': $ cat test.s .text foo: nal $ as -mips64r6 -o test.o test.s $ objdump -dr --prefix-addresses --show-raw-insn -M no-aliases test.o nal.o: file format elf32-tradbigmips Disassembly of section .text: 00000000 <foo> 04100000 0x4100000 ... $ This is because the `bltzal' entry has been marked as pre-R6 only in the opcode table and there is no other opcode pattern to match. Additionally the changes referred made NAL replace the equivalent `bltzal $0, . + 4' instruction in disassembly, unless the `no-aliases' machine option has been used, in legacy code. Seeing NAL, especially in its updated form lacking the branch target argument, in the disassembly of such code may be confusing to people. This is because unlike with EHB only used in R2 and newer code -- the machine encoding of which we anyway always disassemble to its corresponding current architecture's mnemonic rather than its legacy meaning of `sll $0, $0, 3' -- BLTZAL has been indeed used in legacy code. Even though `bltzal $0, . + 8' and its machine code encoding (0x04100001) -- which is not equivalent to NAL and still disassembles as BLTZAL -- has been the predominant form as opposed to NAL's `bltzal $0, . + 4' (0x04100000), it makes sense to always keep the old form in disassembly, while still accepting `nal' in assembly. Remove the alias marking then from the the `nal' instruction pattern, making it always match for R6 code, even with the `no-aliases' option. And move the entry beyond the `bltzal' entry, making the latter one take precedence for legacy binary code, while letting the former still match any `nal' mnemonic in source code assembled for a legacy target. Add a suitable test case to the GAS test suite. While the change affects the disassembler more than the assembler, so placing the test case in the binutils test suite might be more appropriate, the intent is also to verify that `nal' is still accepted by GAS for legacy targets, plus we have test infrastructure available in the GAS test suite for automatic multiple ISA level testing, which we lack from the binutils framework. opcodes/ * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS annotation from the "nal" entry and reorder it beyond "bltzal". gas/ * testsuite/gas/mips/nal-1.d: New test. * testsuite/gas/mips/mipsr6@nal-1.d: New test. * testsuite/gas/mips/nal-2.d: New test. * testsuite/gas/mips/mipsr6@nal-2.d: New test. * testsuite/gas/mips/nal.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests.	10 years ago
Jose E. Marchesi	6e7ced37e7	opcodes,gas: support for the ldtxa SPARC instructions. This patch adds support for the LDTXA instructions, along with the corresponding ASIs. Tests for GAS are included. opcodes/ChangeLog: 2016-07-12 Jose E. Marchesi <jose.marchesi@oracle.com> * sparc-opc.c (ldtxa): New macro. (sparc_opcodes): Use the macro defined above to add entries for the LDTXA instructions. (asi_table): Add the ASI_TWINX_* asis used in the LDTXA instruction. gas/ChangeLog: 2016-07-12 Jose E. Marchesi <jose.marchesi@oracle.com> * testsuite/gas/sparc/ldtxa.s: New file. * testsuite/gas/sparc/ldtxa.d: Likewise. * testsuite/gas/sparc/sparc.exp: Execute the ldtxa test.	10 years ago
jamesbowman	2f831b9a2b	FT32: adjust disassembly opcode match fields Tighten up the opcode match fields for conditional jump and call instructions so more general opcodes don't match them in disassembly. opcodes/ChangeLog: * opcodes/ft32-opc.c (ft32_opc_info): Correct mask for "callc" and "jmpc".	10 years ago
Jan Beulich	c07315e0c6	x86: allow suffix-less movzw and 64-bit movzb ... just like is already the case for 16- and 32-bit movzb: I can't see why omitting suffixes on this (and movs{b,w,l}) is not allowed, when it is allowed for all other instructions where the suffix is redundant with (one of) the operands.	10 years ago
Jan Beulich	9243100aef	x86: remove stray instruction attributes - with Cpu64 Disp16 makes no sense for memory operands - with CpuNo64 Disp32S makes no sense - non-64-bit lgdt doesn't allow 10-byte operands	10 years ago
Jan Beulich	8325cc6398	x86/Intel: fix operand checking for MOVSD The dual purpose mnemonic (string move vs scalar double move) breaks the assumption that the isstring flag would be set on both the first and last entry in the current set of templates, which results in bogus or missing diagnostics for the string move variant of the mnemonic. Short of mostly rewriting i386_index_check() and its interaction with the rest of the code, simply shrink the template set to just string instructions when encountering the second memory operand, and run i386_index_check() a second time for the first memory operand after that reduction.	10 years ago
Yao Qi	838441e4a2	Fix typo in comment This patch fixes the typo "uf" in the comment. I'll push it in as the change is obvious. 2016-06-30 Yao Qi <yao.qi@linaro.org> * arm-dis.c (print_insn): Fix typo in comment.	10 years ago
Richard Sandiford	dab26bf4e7	[AArch64] Make register indices be full 64-bit values aarch64_opnd_info used bitfields to hold vector element indices, but values were stored into those bitfields before their ranges had been checked. This meant large invalid indices could be silently truncated to smaller valid indices. The two obvious fixes were to do the range checking earlier or use a full 64-bit field for the index. I went for the latter for two reasons: - Doing the range checking in operand_general_constraint_met_p seems structurally cleaner than doing it while parsing. - The bitfields didn't really buy us anything. The imm field of the union is already 128 bits, so we can use a full int64_t index without growing the structure. The patch also adds missing range checks for the elements in a register list index. include/ * opcode/aarch64.h (aarch64_opnd_info): Change index fields to int64_t. opcodes/ * aarch64-opc.c (operand_general_constraint_met_p): Check the range of ldst_elemlist operands. (print_register_list): Use PRIi64 to print the index. (aarch64_print_operand): Likewise. gas/ * testsuite/gas/aarch64/diagnostic.s, testsuite/gas/aarch64/diagnostic.l: Add tests for out-of-range indices.	10 years ago
Trevor Saunders	5703197e04	remove a few sentinals gas/ChangeLog: 2016-06-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * config/tc-bfin.c (bfin_cpus): Remove sentinal. (md_parse_option): Adjust. * config/tc-aarch64.c (aarch64_parse_abi): Replace use of a sentinal with iteration from 0 to ARRAY_SIZE. * config/tc-mcore.c (md_begin): Likewise. * config/tc-visium.c (visium_parse_arch): Likewise. opcodes/ChangeLog: 2016-06-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * mcore-opc.h: Remove sentinal. * mcore-dis.c (print_insn_mcore): Adjust.	10 years ago
Graham Markall	ce440d638d	[ARC] Misc minor edits/fixes The code supporting -mspfp, -mdpfp, and -mfpuda options are in sections of code that are commented as being for backward compatibility only, and having no effect. However, they do have an effect, enabling the SPX, DPX, and DPA instruction subclasses respectively. This commit moves the code supporting these options away from the comments indicating that they are dummy options, and also fixes a small issue where -mnps400 had the additional effect of enabling SPX instructions. A couple of other minor edits (that make no functional change) are also included. gas/ChangeLog: * config/tc-arc.c (options, md_longopts, md_parse_option): Move -mspfp, -mdpfp and -mfpuda out of the sections for dummy options. Correct erroneous enabling of SPFP instructions when using -mnps400. include/ChangeLog: * opcode/arc.h: Make insn_class_t alphabetical again. opcodes/ChangeLog: * arc-opc.c: Correct description of availability of NPS400 features.	10 years ago
Peter Bergner	6fd3a02da5	Add support for yet some more new ISA 3.0 instructions. opcodes/ * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines. (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni, mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool, xor3>: New mnemonics. <setb>: Change to a VX form instruction. (insert_sh6): Add support for rldixor. (extract_sh6): Likewise. gas/ * testsuite/gas/ppc/power9.d <brd, brh, brw, mffs, mffs., mffsce, mffscdrn, mffscdrni, mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool, xor3>: New tests. * testsuite/gas/ppc/power9.s: Likewise.	10 years ago
Trevor Saunders	6b4778968b	addmore extern C opcodes/ChangeLog: 2016-06-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * arc-ext.h: Wrap in extern C. include/ChangeLog: 2016-06-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org> * elf/dlx.h: Wrap in extern C. * elf/xtensa.h: Likewise. * opcode/arc.h: Likewise.	10 years ago
Graham Markall	bdd582dbf1	Arc assembler: Convert nps400 from a machine type to an extension. gas * config/tc-arc.c (check_cpu_feature, md_parse_option): Add nps400 option and feature. Add check for nps400 feature. Refactor existing checks to check subclass before feature enablement. (md_show_usage): Document flags for NPS-400 and add some other undocumented flags. (cpu_type): Remove nps400 CPU type entry (check_zol): Remove bfd_mach_arc_nps400 case. (md_show_usage): Add help on -mcpu=nps400. (cpu_types): Add entry for nps400 as arc700 plus nps400 extension set. * doc/c-arc.texi: Document the -mnps400, -mspfp, -mdpfp, and -fpuda flags. Document -mcpu=nps400. * testsuite/gas/arc/nps-400-0.d: Use -mcpu=arc700 -mnps400. Change expected flags to match ARC700 instead of NPS400. * testsuite/gas/arc/nps-400-1.d: Use -mcpu=arc700 -mnps400. * testsuite/gas/arc/nps-400-2.d: Likewise. * testsuite/gas/arc/nps-400-3.d: Likewise. * testsuite/gas/arc/nps-400-4.d: Likewise. * testsuite/gas/arc/nps-400-5.d: Likewise. * testsuite/gas/arc/nps-400-6.d: Likewise. * testsuite/gas/arc/nps-400-7.d: Likewise. * testsuite/gas/arc/textinsn2op01.s: Change opcode of myinsn to avoid clash with cbba instruction. * testsuite/gas/arc/textinsn2op01.d: Likewise. * testsuite/gas/arc/textinsn3op.d: Likewise. * testsuite/gas/arc/textinsn3op.s: Likewise. * testsuite/gas/arc/nps-400-0.d: Test using NPS-400 using -mcpu=nps400 as an alternative to -mcpu=arc700 -mnps400 flags. binutils* readelf.c (decode_ARC_machine_flags): Remove E_ARC_MACH_NPS400 case. ld * testsuite/ld-arc/nps-1a.d: Use -mcpu=arc700 -mnps400. * testsuite/ld-arc/nps-1b.d: Likewise. include * opcode/arc.h: Add nps400 extension and instruction subclass. Remove ARC_OPCODE_NPS400 * elf/arc.h: Remove E_ARC_MACH_NPS400 opcodes * arc-dis.c (arc_insn_length): Add comment on instruction length. Use same method for determining instruction length on ARC700 and NPS-400. (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400. * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions with the NPS400 subclass. * arc-opc.c: Likewise. bfd * archures.c: Remove bfd_mach_arc_nps400. * bfd-in2.h: Likewise. * cpu-arc.c (arch_info_struct): Likewise. * elf32-arc.c (arc_elf_object_p, arc_elf_final_write_processing): Likewise.	10 years ago
Jose E. Marchesi	96074adc6a	opcodes,gas: sparc: fix rdasr,wrasr,rdpr,wrpr,rdhpr,wrhpr insns. This patch fixes and expands the definition of the read/write instructions for ancillary-state, privileged and hyperprivileged registers in opcodes. It also adds support for three new v9m hyperprivileged registers: %hmcdper, %hmcddfr and %hva_mask_nz. Finally, the patch expands existing tests (and adds several new ones) in order to cover all the read/write instructions in all its variants. opcodes/ChangeLog: 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com> * sparc-opc.c (rdasr): New macro. (wrasr): Likewise. (rdpr): Likewise. (wrpr): Likewise. (rdhpr): Likewise. (wrhpr): Likewise. (sparc_opcodes): Use the macros above to fix and expand the definition of read/write instructions from/to asr/privileged/hyperprivileged instructions. * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and %hva_mask_nz. Prefer softint_set and softint_clear over set_softint and clear_softint. (print_insn_sparc): Support %ver in Rd. gas/ChangeLog: 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com> * config/tc-sparc.c (hpriv_reg_table): Add registers %hmcdper, %hmcddfr and %hva_mask_nz. (sparc_ip): New handling of asr/privileged/hyperprivileged registers, adapted to the new form of the sparc opcodes table. * testsuite/gas/sparc/rdasr.s: New file. * testsuite/gas/sparc/rdasr.d: Likewise. * testsuite/gas/sparc/wrasr.s: Likewise. * testsuite/gas/sparc/wrasr.d: Likewise. * testsuite/gas/sparc/sparc.exp (sparc_elf_setup): Add rdasr and wrasr tests. * testsuite/gas/sparc/rdpr.d: Use -Av9m, as some privileged registers require it. * testsuite/gas/sparc/wrpr.s: Complete to cover all privileged registers and write instruction modalities. * testsuite/gas/sparc/wrpr.d: Likewise. * testsuite/gas/sparc/rdhpr.s: Likewise for hyperprivileged registers. * testsuite/gas/sparc/rdhpr.d: Likewise. * testsuite/gas/sparc/wrhpr.s: Likewise. * testsuite/gas/sparc/wrhpr.d: Likewise.	10 years ago
Jose E. Marchesi	7a10c22feb	opcodes,gas: adjust sparc insns and make GAS aware of it This patch marks the SPARC instructions in the opcodes table with their proper opcode architectures, and makes the assembler aware of them. This allows the assembler to properly realize when a new instruction needs a higher architecture (after v9b) and to react accordingly emitting an error message or bumping the architecture. It also expands architecture mismatch tests to cover architectures higher than v9b, and fixes a couple of minor bugs in the GAS testsuite. opcodes/ChangeLog: 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com> * sparc-opc.c (sparc_opcodes): Adjust instructions opcode architecture according to the hardware capabilities they require. (sparc_priv_regs): New table. (sparc_hpriv_regs): Likewise. (sparc_asr_regs): Likewise. (v9anotv9m): Define. gas/ChangeLog: 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com> * config/tc-sparc.c (sparc_arch_table): adjust the GAS architectures to use the right opcode architecture. (sparc_md_end): Handle v9{c,d,e,v,m}. (sparc_ip): Fix some comments. * testsuite/gas/sparc/ldx_efsr.d: Fix the architecture of this instruction, which is v9d. * testsuite/gas/sparc/mwait.s: Remove the `rd %mwait,%g1' instruction from the test, as %mwait is not readable. * testsuite/gas/sparc/mwait.d: Likewise. * testsuite/gas/sparc/mism-1.s: Expand to check v9b and v9e mismatch architecture errors. * testsuite/gas/sparc/mism-2.s: New file.	10 years ago
Jose E. Marchesi	4f26fb3a1b	bfd,opcodes: sparc: new opcode v9{c,d,e,v,m} architectures and bfd machine numbers. This patch adds support for the opcode architectures SPARC_OPCODE_ARCH_V9{C,D,E,V,M} and its associated BFD machine numbers bfd_mach_sparc_v9{c,d,e,v,m} and bfd_mach_sparc_v8plus{c,d,e,v,m}. Note that for arches up to v9b (UltraSPARC III), the detection of the BFD machine type was based on the bits in the e_machine field of the ELF header. However, there are no more available bits in that field, so this patch takes the approach of using the hardware capabilities stored in the object attributes HWCAPS/HWCAPS2 in order to characterize the machine the object was built for. bfd/ChangeLog: 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com> * archures.c (bfd_mach_sparc_v8plusc): Define. (bfd_mach_sparc_v9c): Likewise. (bfd_mach_sparc_v8plusd): Likewise. (bfd_mach_sparc_v9d): Likewise. (bfd_mach_sparc_v8pluse): Likewise. (bfd_mach_sparc_v9e): Likewise. (bfd_mach_sparc_v8plusv): Likewise (bfd_mach_sparc_v9v): Likewise. (bfd_mach_sparc_v8plusm): Likewise. (bfd_mach_sparc_v9m): Likewise. (bfd_mach_sparc_v9_p): Adapt to v8plusm and v9m. (bfd_mach_sparc_64bit_p): Likewise. * bfd-in2.h: Regenerate. * cpu-sparc.c (arch_info_struct): Add entries for bfd_mach_sparc_v8plus{c,d,e,v,m} and bfd_mach_sparc_v9{c,d,e,v,m}. * aoutx.h (machine_type): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and bfd_mach_sparc_v9{c,d,e,v,m}. * elf32-sparc.c (elf32_sparc_final_write_processing): Likewise. * elfxx-sparc.c (_bfd_sparc_elf_object_p): Likewise. include/ChangeLog: 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com> * opcode/sparc.h (enum sparc_opcode_arch_val): Add SPARC_OPCODE_ARCH_V9C, SPARC_OPCODE_ARCH_V9D, SPARC_OPCODE_ARCH_V9E, SPARC_OPCODE_ARCH_V9V and SPARC_OPCODE_ARCH_V9M. opcodes/ChangeLog: 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com> * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}. (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and bfd_mach_sparc_v9{c,d,e,v,m}. * sparc-opc.c (MASK_V9C): Define. (MASK_V9D): Likewise. (MASK_V9E): Likewise. (MASK_V9V): Likewise. (MASK_V9M): Likewise. (v6): Add MASK_V9{C,D,E,V,M}. (v6notlet): Likewise. (v7): Likewise. (v8): Likewise. (v9): Likewise. (v9andleon): Likewise. (v9a): Likewise. (v9b): Likewise. (v9c): Define. (v9d): Likewise. (v9e): Likewise. (v9v): Likewise. (v9m): Likewise. (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.	10 years ago
Nick Clifton	3ee6e4fbec	Fix simple gas testsuite failures. binutils* readelf.c (is_24bit_abs_reloc): Add support for R_FT32_20 reloc. gas * config/tc-ft32.c (md_assemble): Call dwarf2_emit_insn with the instruction size. * config/tc-mcore.c (md_assemble): Likewise. * config/tc-mn10200.c (md_assemble): Likewise. * config/tc-moxie.c (md_assemble): Likewise. * config/tc-pj.c (md_apply_fix): Handle BFD_RELOC_PJ_CODE_REL32. * testsuite/gas/all/gas.exp (diff1 test): Alpha sort list of exception targets. Add alpha, hppa, microblaze and rl78 to list of exceptions. (forward): Add microblaze to list of exceptions. (fwdexp): Add alpha to list of exceptions. (redef2): Add arm-epoc-pe and rl78 to list of exceptions. (redef3): Add rl78 and x86_64 cygwin to list of exceptions. (do_930509a): Alpha sort list of exception targets. Add h8300 and mn10200 to list of exceptions. (align2): Expect to fail for nds32. (cond): Add alpha and rl78 to list of exceptions. * testsuite/gas/all/none.d: Skip for ft32 and hppa. * testsuite/gas/all/string.d: Skip for tic4x. * testsuite/gas/alpha/alpha.exp: Note that the alpha-linuxecoff target does not support ELF. * testsuite/gas/arm/blx-bl-convert.dL Skip for the nto target. * testsuite/gas/cfi/cfi-alpha-2.d: All extended format names. * testsuite/gas/cfi/cfi.exp: Alpha sort list of targets. Skip SH tests for sh-pe and sh-rtemscoff targets. * testsuite/gas/elf/elf.exp (redef): Add rl78, xgate and vax to list of exceptions. (type): Run the noifunc version for alpha-freebsd and visium. * testsuite/gas/elf/warn-2.s: Do not expect to fail on the mcore, mn10200 or moxie targets. * testsuite/gas/ft32/insn.d: Update expected disassembly. * testsuite/gas/i386/i386.exp (x86-64-pcrel): Skip for cygwin targets. * testsuite/gas/lns/lns.exp (lns-common-1): No longer skip for mcore and rx targets. * testsuite/gas/macros/macros.exp (dot): Add exceptions for ns32k, rl78 and vax. (purge): Expect to fail on the ns32k and vax. * testsuite/gas/nds32/alu-2.d: Update expected disassembly. * testsuite/gas/nds32/ls.d: Likewise. * testsuite/gas/nds32/sys-reg.d: Likewise. * testsuite/gas/nds32/usr-spe-reg.d: Likewise. * testsuite/gas/pe/aligncomm-d.d: Skip for the sh. * testsuite/gas/pe/section-align-3.d: Likewise. * testsuite/gas/pe/section-exclude.d: Likewise. * testsuite/gas/ppc/test2xcoff32.d: Pass once all the required data has been seen. * testsuite/gas/ppc/textalign-xcoff-001.d: Fix up regexp to allow for variations in whitespace. * testsuite/gas/tilepro/t_constants.d: Pass once all the required data has been seen. * testsuite/gas/tilepro/t_constants.s (.safe_word): New macro. Installs a 32-bit value without generating warnings on 64-bit hosts. Use the new macro to replace the .word directives. opcodes * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer constants to match expected behaviour. (nds32_parse_opcode): Likewise. Also for whitespace.	10 years ago
Andrew Burgess	02f3be19f6	opcodes/arc: Fix extract for some add_s instructions The extract function used for some arc_s instructions was not implemented, and instead always returned 0. Fixed in this commit. opcodes/ChangeLog: * arc-opc.c (extract_rhv1): Extract value from insn. gas/ChangeLog: * testsuite/gas/arc/add_s.d: New file. * testsuite/gas/arc/add_s.s: New file.	10 years ago

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2546 Commits (2442d8466e221ba6cf4ec4bd2a819fdcb1e5ea7e)