binutils-gdb

Commit Graph

Author	SHA1	Message	Date
Richard Sandiford	2442d8466e	[AArch64][SVE 24/32] Add AARCH64_OPND_SVE_PATTERN_SCALED Some SVE instructions count the number of elements in a given vector pattern and allow a scale factor of [1, 16] to be applied to the result. This scale factor is written ", MUL #n", where "MUL" is a new operator. E.g.: UQINCD X0, POW2, MUL #2 This patch adds support for this kind of operand. All existing operators were shifts of some kind, so there was a natural range of [0, 63] regardless of context. This was then narrowered further by later checks (e.g. to [0, 31] when used for 32-bit values). In contrast, MUL doesn't really have a natural context-independent range. Rather than pick one arbitrarily, it seemed better to make the "shift" amount a full 64-bit value and leave the range test to the usual operand-checking code. I've rearranged the fields of aarch64_opnd_info so that this doesn't increase the size of the structure (although I don't think its size is critical anyway). include/ * opcode/aarch64.h (AARCH64_OPND_SVE_PATTERN_SCALED): New aarch64_opnd. (AARCH64_MOD_MUL): New aarch64_modifier_kind. (aarch64_opnd_info): Make shifter.amount an int64_t and rearrange the fields. opcodes/ * aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for AARCH64_OPND_SVE_PATTERN_SCALED. * aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind. * aarch64-opc.c (fields): Add a corresponding entry. (set_multiplier_out_of_range_error): New function. (aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL. (operand_general_constraint_met_p): Handle AARCH64_OPND_SVE_PATTERN_SCALED. (print_register_offset_address): Use PRIi64 to print the shift amount. (aarch64_print_operand): Likewise. Handle AARCH64_OPND_SVE_PATTERN_SCALED. * aarch64-opc-2.c: Regenerate. * aarch64-asm.h (ins_sve_scale): New inserter. * aarch64-asm.c (aarch64_ins_sve_scale): New function. * aarch64-asm-2.c: Regenerate. * aarch64-dis.h (ext_sve_scale): New inserter. * aarch64-dis.c (aarch64_ext_sve_scale): New function. * aarch64-dis-2.c: Regenerate. gas/ * config/tc-aarch64.c (SHIFTED_MUL): New parse_shift_mode. (parse_shift): Handle it. Reject AARCH64_MOD_MUL for all other shift modes. Skip range tests for AARCH64_MOD_MUL. (process_omitted_operand): Handle AARCH64_OPND_SVE_PATTERN_SCALED. (parse_operands): Likewise.	10 years ago
Richard Sandiford	245d2e3fe8	[AArch64][SVE 23/32] Add SVE pattern and prfop operands The SVE instructions have two enumerated operands: one to select a vector pattern and another to select a prefetch operation. The latter is a cut-down version of the base AArch64 prefetch operation. Both types of operand can also be specified as raw enum values such as #31. Reserved values can only be specified this way. If it hadn't been for the pattern operand, I would have been tempted to use the existing parsing for prefetch operations and add extra checks for SVE. However, since the patterns needed new enum parsing code anyway, it seeemed cleaner to reuse it for the prefetches too. Because of the small number of enum values, I don't think we'd gain anything by using hash tables. include/ * opcode/aarch64.h (AARCH64_OPND_SVE_PATTERN): New aarch64_opnd. (AARCH64_OPND_SVE_PRFOP): Likewise. (aarch64_sve_pattern_array): Declare. (aarch64_sve_prfop_array): Likewise. opcodes/ * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP. * aarch64-opc.h (FLD_SVE_pattern): New aarch64_field_kind. (FLD_SVE_prfop): Likewise. * aarch64-opc.c: Include libiberty.h. (aarch64_sve_pattern_array): New variable. (aarch64_sve_prfop_array): Likewise. (fields): Add entries for FLD_SVE_pattern and FLD_SVE_prfop. (aarch64_print_operand): Handle AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP. * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Likewise. * aarch64-opc-2.c: Likewise. gas/ * config/tc-aarch64.c (parse_enum_string): New function. (po_enum_or_fail): New macro. (parse_operands): Handle AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP.	10 years ago
Richard Sandiford	d50c751e00	[AArch64][SVE 22/32] Add qualifiers for merging and zeroing predication This patch adds qualifiers to represent /z and /m suffixes on predicate registers. include/ * opcode/aarch64.h (AARCH64_OPND_QLF_P_Z): New aarch64_opnd_qualifier. (AARCH64_OPND_QLF_P_M): Likewise. opcodes/ * aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for AARCH64_OPND_QLF_P_[ZM]. (aarch64_print_operand): Print /z and /m where appropriate. gas/ * config/tc-aarch64.c (vector_el_type): Add NT_zero and NT_merge. (parse_vector_type_for_operand): Assert that the skipped character is a '.'. (parse_predication_for_operand): New function. (parse_typed_reg): Parse /z and /m suffixes for predicate registers. (vectype_to_qualifier): Handle NT_zero and NT_merge.	10 years ago
Richard Sandiford	f11ad6bc0f	[AArch64][SVE 21/32] Add Zn and Pn registers This patch adds the Zn and Pn registers, and associated fields and operands. include/ * opcode/aarch64.h (AARCH64_OPND_CLASS_SVE_REG): New aarch64_operand_class. (AARCH64_OPND_CLASS_PRED_REG): Likewise. (AARCH64_OPND_SVE_Pd, AARCH64_OPND_SVE_Pg3, AARCH64_OPND_SVE_Pg4_5) (AARCH64_OPND_SVE_Pg4_10, AARCH64_OPND_SVE_Pg4_16) (AARCH64_OPND_SVE_Pm, AARCH64_OPND_SVE_Pn, AARCH64_OPND_SVE_Pt) (AARCH64_OPND_SVE_Za_5, AARCH64_OPND_SVE_Za_16, AARCH64_OPND_SVE_Zd) (AARCH64_OPND_SVE_Zm_5, AARCH64_OPND_SVE_Zm_16, AARCH64_OPND_SVE_Zn) (AARCH64_OPND_SVE_Zn_INDEX, AARCH64_OPND_SVE_ZnxN) (AARCH64_OPND_SVE_Zt, AARCH64_OPND_SVE_ZtxN): New aarch64_opnds. opcodes/ * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands. * aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5) (FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt) (FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16) (FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds. * aarch64-opc.c (fields): Add corresponding entries here. (operand_general_constraint_met_p): Check that SVE register lists have the correct length. Check the ranges of SVE index registers. Check for cases where p8-p15 are used in 3-bit predicate fields. (aarch64_print_operand): Handle the new SVE operands. * aarch64-opc-2.c: Regenerate. * aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters. * aarch64-asm.c (aarch64_ins_sve_index): New function. (aarch64_ins_sve_reglist): Likewise. * aarch64-asm-2.c: Regenerate. * aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors. * aarch64-dis.c (aarch64_ext_sve_index): New function. (aarch64_ext_sve_reglist): Likewise. * aarch64-dis-2.c: Regenerate. gas/ * config/tc-aarch64.c (NTA_HASVARWIDTH): New macro. (AARCH64_REG_TYPES): Add ZN and PN. (get_reg_expected_msg): Handle them. (parse_vector_type_for_operand): Add a reg_type parameter. Skip the width for Zn and Pn registers. (parse_typed_reg): Extend vector handling to Zn and Pn. Update the call to parse_vector_type_for_operand. Set HASVARTYPE for Zn and Pn, expecting the width to be 0. (parse_vector_reg_list): Restrict error about [BHSD]nn operands to REG_TYPE_VN. (vectype_to_qualifier): Use S_[BHSD] qualifiers for NTA_HASVARWIDTH. (parse_operands): Handle the new Zn and Pn operands. (REGSET16): New macro, split out from... (REGSET31): ...here. (reg_names): Add Zn and Pn entries.	10 years ago
Richard Sandiford	0c608d6b62	[AArch64][SVE 20/32] Add support for tied operands SVE has some instructions in which the same register appears twice in the assembly string, once as an input and once as an output. This patch adds a general mechanism for that. The patch needs to add new information to the instruction entries. One option would have been to extend the flags field of the opcode to 64 bits (since we already rely on 64-bit integers being available on the host). However, the _INSN macros mean that it's easy to add new information as top-level fields without affecting the existing table entries too much. Going for that option seemed to give slightly neater code. include/ opcode/aarch64.h (aarch64_opcode): Add a tied_operand field. (AARCH64_OPDE_UNTIED_OPERAND): New aarch64_operand_error_kind. opcodes/ * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN) (_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN) (V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field. * aarch64-opc.c (aarch64_match_operands_constraint): Check for tied operands. gas/ * config/tc-aarch64.c (output_operand_error_record): Handle AARCH64_OPDE_UNTIED_OPERAND.	10 years ago
Richard Sandiford	01dbfe4c0e	[AArch64][SVE 19/32] Refactor address-printing code SVE adds addresses in which the base or offset are vector registers. The addresses otherwise have the same kind of form as normal AArch64 addresses, including things like SXTW with or without a shift, UXTW with or without a shift, and LSL. This patch therefore refactors the address-printing code so that it can cope with both scalar and vector registers. opcodes/ * aarch64-opc.c (get_offset_int_reg_name): New function. (print_immediate_offset_address): Likewise. (print_register_offset_address): Take the base and offset registers as parameters. (aarch64_print_operand): Update caller accordingly. Use print_immediate_offset_address.	10 years ago
Richard Sandiford	72e9f31937	[AArch64][SVE 18/32] Tidy definition of aarch64-opc.c:int_reg Use a macro to define 31 regular registers followed by a supplied value for 0b11111. The SVE code will also use this for vector base and offset registers. opcodes/ * aarch64-opc.c (BANK): New macro. (R32, R64): Take a register number as argument (int_reg): Use BANK.	10 years ago
Richard Sandiford	8a7f0c1b5a	[AArch64][SVE 17/32] Add a prefix parameter to print_register_list This patch generalises the interface to print_register_list so that it can print register lists involving SVE z registers as well as AdvSIMD v ones. opcodes/ * aarch64-opc.c (print_register_list): Add a prefix parameter. (aarch64_print_operand): Update accordingly.	10 years ago
Richard Sandiford	aa2aa4c694	[AArch64][SVE 16/32] Use specific insert/extract methods for fpimm FPIMM used the normal "imm" insert/extract methods, with a specific test for FPIMM in the extract method. SVE needs to use the same extractors, so rather than add extra checks for specific operand types, it seemed cleaner to use a separate insert/extract method. opcodes/ * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm for FPIMM. * aarch64-asm.h (ins_fpimm): New inserter. * aarch64-asm.c (aarch64_ins_fpimm): New function. * aarch64-asm-2.c: Regenerate. * aarch64-dis.h (ext_fpimm): New extractor. * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test. (aarch64_ext_fpimm): New function. * aarch64-dis-2.c: Regenerate.	10 years ago
Richard Sandiford	b5464a6825	[AArch64][SVE 15/32] Add {insert,extract}_all_fields helpers Several of the SVE operands use the aarch64_operand fields array to store the fields that make up the operand, rather than hard-coding the names in the C code. This patch adds helpers for inserting and extracting those fields. opcodes/ * aarch64-asm.c: Include libiberty.h. (insert_fields): New function. (aarch64_ins_imm): Use it. * aarch64-dis.c (extract_fields): New function. (aarch64_ext_imm): Use it.	10 years ago
Richard Sandiford	42408347b8	[AArch64][SVE 14/32] Make aarch64_logical_immediate_p take an element size SVE supports logical immediate operations on 8-bit, 16-bit and 32-bit elements, treating them as aliases of operations on 64-bit elements in which the immediate is replicated. This patch therefore replaces the "32-bit/64-bit" input to aarch64_logical_immediate_p with a more general "number of bytes" input. opcodes/ * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32 with an esize parameter. (operand_general_constraint_met_p): Update accordingly. Fix misindented code. * aarch64-asm.c (aarch64_ins_limm): Update call to aarch64_logical_immediate_p.	10 years ago
Richard Sandiford	4989adac84	[AArch64][SVE 13/32] Add an F_STRICT flag SVE predicate operands can appear in three forms: 1. unsuffixed: "Pn" 2. with a predication type: "Pn/[ZM]" 3. with a size suffix: "Pn.[BHSD]" No variation is allowed: unsuffixed operands cannot have a (redundant) suffix, and the suffixes can never be dropped. Unsuffixed Pn are used in LDR and STR, but they are also used for Pg operands in cases where the result is scalar and where there is therefore no choice to be made between "merging" and "zeroing". This means that some Pg operands have suffixes and others don't. It would be possible to use context-sensitive parsing to handle this difference. The tc-aarch64.c code would then raise an error if the wrong kind of suffix is used for a particular instruction. However, we get much more user-friendly error messages if we parse all three forms for all SVE instructions and record the suffix as a qualifier. The normal qualifier matching code can then report cases where the wrong kind of suffix is used. This is a slight extension of existing usage, which really only checks for the wrong choice of suffix within a particular kind of suffix. The only catch is a that a "NIL" entry in the qualifier list specifically means "no suffix should be present" (case 1 above). NIL isn't a wildcard here. It also means that an instruction that requires all-NIL qualifiers can fail to match (because a suffix was supplied when it shouldn't have been); this requires a slight change to find_best_match. This patch adds an F_STRICT flag to select this behaviour. The flag will be set for all SVE instructions. The behaviour for other instructions doesn't change. include/ * opcode/aarch64.h (F_STRICT): New flag. opcodes/ * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT. gas/ * config/tc-aarch64.c (find_best_match): Simplify, allowing an instruction with all-NIL qualifiers to fail to match.	10 years ago
Richard Sandiford	73866052f2	[AArch64][SVE 12/32] Remove boolean parameters from parse_address_main In the review of the original version of this series, Richard didn't like the use of boolean parameters to parse_address_main. I think we can just get rid of them and leave the callers to check the addressing modes. As it happens, the handling of ADDR_SIMM9{,_2} already did this for relocation operators (i.e. it used parse_address_reloc and then rejected relocations). The callers are already set up to reject invalid register post-indexed addressing, so we can simply remove the accept_reg_post_index parameter without adding any more checks. This again creates a corner case where: .equ x2, 1 ldr w0, [x1], x2 was previously an acceptable way of writing "ldr w0, [x1], #1" but is now rejected. Removing the "reloc" parameter means that two cases need to check explicitly for relocation operators. ADDR_SIMM9_2 appers to be unused. I'll send a separate patch to remove it. This patch makes parse_address temporarily equivalent to parse_address_main, but later patches in the series will need to keep the distinction. gas/ * config/tc-aarch64.c (parse_address_main): Remove reloc and accept_reg_post_index parameters. Parse relocations and register post indexes unconditionally. (parse_address): Remove accept_reg_post_index parameter. Update call to parse_address_main. (parse_address_reloc): Delete. (parse_operands): Call parse_address instead of parse_address_main. Update existing callers of parse_address and make them check inst.reloc.type where appropriate. * testsuite/gas/aarch64/diagnostic.s: Add tests for relocations in ADDR_SIMPLE, SIMD_ADDR_SIMPLE, ADDR_SIMM7 and ADDR_SIMM9 addresses. Also test for invalid uses of post-index register addressing. * testsuite/gas/aarch64/diagnostic.l: Update accordingly.	10 years ago
Richard Sandiford	e1b988bba6	[AArch64][SVE 11/32] Tweak aarch64_reg_parse_32_64 interface aarch64_reg_parse_32_64 is currently used to parse address registers, among other things. It returns two bits of information about the register: whether it's W rather than X, and whether it's a zero register. SVE adds addressing modes in which the base or offset can be a vector register instead of a scalar, so a choice between W and X is no longer enough. It's more convenient to pass the type of register around as a qualifier instead. As it happens, two callers of aarch64_reg_parse_32_64 already wanted the information in the form of a qualifier, so the change feels pretty natural even without SVE. Also, the function took two parameters to control whether {W}SP and (W\|X)ZR should be accepted. We tend to get slightly better error messages by accepting them regardless and getting the caller to do the check, rather than potentially treating "xzr", "sp" etc. as constants. This is easier to do if the function returns the reg_entry rather than just the register number. This does create a corner case where: .equ sp, 1 ldr w0, [x0, sp] was previously an acceptable way of writing "ldr w0, [x0, #1]", but I don't think it's important to continue supporting that. We already rejected things like: .equ sp, 1 add x0, x1, sp To ensure these new error messages "win" when matching against several candidate instruction entries, we need to use the same address-parsing code for all addresses, including ADDR_SIMPLE and SIMD_ADDR_SIMPLE. The next patch also relies on this. Finally, aarcch64_check_reg_type was written in a pretty conservative way. It should always be equivalent to a single bit test. gas/ * config/tc-aarch64.c (REG_TYPE_R_Z, REG_TYPE_R_SP): New register types. (get_reg_expected_msg): Handle them and REG_TYPE_R64_SP. (aarch64_check_reg_type): Simplify. (aarch64_reg_parse_32_64): Return the reg_entry instead of the register number. Return the type as a qualifier rather than an "isreg32" boolean. Remove reject_sp, reject_rz and isregzero parameters. (parse_shifter_operand): Update call to aarch64_parse_32_64_reg. Use get_reg_expected_msg. (parse_address_main): Likewise. Use aarch64_check_reg_type. (po_int_reg_or_fail): Replace reject_sp and reject_rz parameters with a reg_type parameter. Update call to aarch64_parse_32_64_reg. Use aarch64_check_reg_type to test the result. (parse_operands): Update after the above changes. Parse ADDR_SIMPLE addresses normally before enforcing the syntax restrictions. * testsuite/gas/aarch64/diagnostic.s: Add tests for a post-index zero register and for a stack pointer index. * testsuite/gas/aarch64/diagnostic.l: Update accordingly. Also update existing diagnostic messages after the above changes. * testsuite/gas/aarch64/illegal-lse.l: Update the error message for 32-bit register bases.	10 years ago
Richard Sandiford	874d7e6ef9	[AArch64][SVE 10/32] Move range check out of parse_aarch64_imm_float Since some SVE constants are no longer explicitly tied to the 8-bit FP immediate format, it seems better to move the range checks out of parse_aarch64_imm_float and into the callers. gas/ * config/tc-aarch64.c (parse_aarch64_imm_float): Remove range check. (parse_operands): Check the range of 8-bit FP immediates here instead.	10 years ago
Richard Sandiford	6a9deabec4	[AArch64][SVE 09/32] Improve error messages for invalid floats Previously: fmov d0, #2 would give an error: Operand 2 should be an integer register whereas the user probably just forgot to add the ".0" to make: fmov d0, #2.0 This patch reports an invalid floating point constant unless the operand is obviously a register. The FPIMM8 handling is only relevant for SVE. Without it: fmov z0, z1 would try to parse z1 as an integer immediate zero (the res2 path), whereas it's more likely that the user forgot the predicate. This is tested by the final patch. gas/ * config/tc-aarch64.c (parse_aarch64_imm_float): Report a specific low-severity error for registers. (parse_operands): Report an invalid floating point constant for if parsing an FPIMM8 fails, and if no better error has been recorded. * testsuite/gas/aarch64/diagnostic.s, testsuite/gas/aarch64/diagnostic.l: Add tests for integer operands to FMOV.	10 years ago
Richard Sandiford	04a3379ace	[AArch64][SVE 08/32] Generalise aarch64_double_precision_fmovable SVE has single-bit floating-point constants that don't really have any relation to the AArch64 8-bit floating-point encoding. (E.g. one of the constants selects between 0 and 1.) The easiest way of representing them in the aarch64_opnd_info seemed to be to use the IEEE float representation directly, rather than invent some new scheme. This patch paves the way for that by making the code that converts IEEE doubles to IEEE floats accept any value in the range of an IEEE float, not just zero and 8-bit floats. It leaves the range checking to the caller (which already handles it). gas/ * config/tc-aarch64.c (aarch64_double_precision_fmovable): Rename to... (can_convert_double_to_float): ...this. Accept any double-precision value that converts to single precision without loss of precision. (parse_aarch64_imm_float): Update accordingly.	10 years ago
Richard Sandiford	1799c0d064	[AArch64][SVE 07/32] Replace hard-coded uses of REG_TYPE_R_Z_BHSDQ_V To remove parsing ambiguities and to avoid register names being accidentally added to the symbol table, the immediate parsing routines reject things like: .equ x0, 0 add v0.4s, v0.4s, x0 An explicit '#' must be used instead: .equ x0, 0 add v0.4s, v0.4s, #x0 Of course, it wasn't possible to predict what other register names might be added in future, so this behaviour was restricted to the register names that were defined at the time. For backwards compatibility, we should continue to allow things like: .equ p0, 0 add v0.4s, v0.4s, p0 even though p0 is now an SVE register. However, it seems reasonable to extend the x0 behaviour above to SVE registers when parsing SVE instructions, especially since none of the SVE immediate formats are relocatable. Doing so removes the same parsing ambiguity for SVE instructions as the x0 behaviour removes for base AArch64 instructions. As a prerequisite, we then need to be able to tell the parsing routines which registers to reject. This patch changes the interface to make that possible, although the set of rejected registers doesn't change at this stage. gas/ * config/tc-aarch64.c (parse_immediate_expression): Add a reg_type parameter. (parse_constant_immediate): Likewise, and update calls. (parse_aarch64_imm_float): Likewise. (parse_big_immediate): Likewise. (po_imm_nc_or_fail): Update accordingly, passing down a new imm_reg_type variable. (po_imm_of_fail): Likewise. (parse_operands): Likewise.	10 years ago
Richard Sandiford	10d7665010	[AArch64][SVE 06/32] Generalise parse_neon_reg_list Rename parse_neon_reg_list to parse_vector_reg_list and take in the required register type as an argument. Later patches will reuse the function for SVE registers. gas/ * config/tc-aarch64.c (parse_neon_reg_list): Rename to... (parse_vector_reg_list): ...this and take a register type as input. (parse_operands): Update accordingly.	10 years ago
Richard Sandiford	53021dd1a0	[AArch64][SVE 05/32] Rename parse_neon_type_for_operand Generalise the name of parse_neon_type_for_operand to parse_vector_type_for_operand. Later patches will add SVEisms to it. gas/ * config/tc-aarch64.c (parse_neon_type_for_operand): Rename to... (parse_vector_type_for_operand): ...this. (parse_typed_reg): Update accordingly.	10 years ago
Richard Sandiford	8f9a77affe	[AArch64][SVE 04/32] Rename neon_type_el to vector_type_el Similar to the previous patch, but this time for the neon_type_el structure. gas/ * config/tc-aarch64.c (neon_type_el): Rename to... (vector_type_el): ...this. (parse_neon_type_for_operand): Update accordingly. (parse_typed_reg): Likewise. (aarch64_reg_parse): Likewise. (vectype_to_qualifier): Likewise. (parse_operands): Likewise. (eq_neon_type_el): Likewise. Rename to... (eq_vector_type_el): ...this. (parse_neon_reg_list): Update accordingly.	10 years ago
Richard Sandiford	f06935a5c1	[AArch64][SVE 03/32] Rename neon_el_type to vector_el_type Later patches will add SVEisms to neon_el_type, so this patch renames it to something more generic. gas/ * config/tc-aarch64.c (neon_el_type: Rename to... (vector_el_type): ...this. (neon_type_el): Update accordingly. (parse_neon_type_for_operand): Likewise. (vectype_to_qualifier): Likewise.	10 years ago
Richard Sandiford	bd11d5d837	[AArch64][SVE 02/32] Avoid hard-coded limit in indented_print The maximum indentation needed by aarch64-gen.c grows as more instructions are added to aarch64-tbl.h. Rather than having to increase the indentation limit to a higher value, it seemed better to replace it with "%s". opcodes/ aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.	10 years ago
Richard Sandiford	a235d3aece	[AArch64][SVE 01/32] Remove parse_neon_operand_type A false return from parse_neon_operand_type had an overloaded meaning: either the parsing failed, or there was nothing to parse (which isn't necessarily an error). The only caller, parse_typed_reg, would therefore not consume the suffix if it was invalid but instead (successfully) parse the register without a suffix. It would still leave inst.parsing_error with an error about the invalid suffix. It seems wrong for a successful parse to leave an error message, so this patch makes parse_typed_reg return PARSE_FAIL instead. The patch doesn't seem to make much difference in practice. Most possible follow-on errors use set_first_error and so the error about the suffix tended to win despite the successful parse. gas/ * config/tc-aarch64.c (parse_neon_operand_type): Delete. (parse_typed_reg): Call parse_neon_type_for_operand directly.	10 years ago
Maciej W. Rozycki	3d0ec88224	MIPS/testsuite: mips16-thunks: Use `standard_output_file' Correct a commit `2151ccc56c` ("Always organize test artifacts in a directory hierarchy") regression causing: Running .../gdb/testsuite/gdb.arch/mips16-thunks.exp ... gdb compile failed, Assembler messages: Fatal error: can't create .../gdb/testsuite/gdb.arch/mips16-thunks-inmain.o: No such file or directory gdb compile failed, Assembler messages: Fatal error: can't create .../gdb/testsuite/gdb.arch/mips16-thunks-main.o: No such file or directory gdb compile failed, mips-mti-linux-gnu-gcc: error: .../gdb/testsuite/gdb.arch/mips16-thunks-inmain.o: No such file or directory mips-mti-linux-gnu-gcc: error: .../gdb/testsuite/gdb.arch/mips16-thunks-main.o: No such file or directory UNSUPPORTED: gdb.arch/mips16-thunks.exp: No MIPS16 support in the toolchain. by using `standard_output_file' to construct output file names throughout. gdb/testsuite/ * gdb.arch/mips16-thunks.exp: Use `standard_output_file' throughout.	10 years ago
Yao Qi	fc6cda2ee8	Keep reserved bits in CPSR on write In patch https://sourceware.org/ml/gdb-patches/2016-04/msg00529.html I cleared reserved bits when reading CPSR. It makes a problem that these bits (zero) are written back to kernel through ptrace, and it changes the state of the processor on some recent kernel, which is unexpected. In this patch, I keep these reserved bits when write CPSR back to hardware. gdb: 2016-09-21 Yao Qi <yao.qi@linaro.org> * aarch32-linux-nat.c (aarch32_gp_regcache_collect): Keep bits 20 to 23. gdb/gdbserver: 2016-09-21 Yao Qi <yao.qi@linaro.org> * linux-aarch32-low.c (arm_fill_gregset): Keep bits 20 to 23.	10 years ago
GDB Administrator	44b8317a75	Automatic date update in version.in	10 years ago
Tom Tromey	12c58cd4dc	Avoid -Wduplicated-cond warnings in gdb/python I tried building gdb with -Wduplicated-cond. This patch fixes the simpler issue that was found. In Python 3, "int" and "long" are synonyms, so code like: else if (PyLong_Check (obj)) ... else if (PyInt_Check (obj)) .... will trigger this warning. The fix is to conditionalize the PyInt_Check branches on Python 2. Tested by rebuilding, with both version of Python, on x86-64 Fedora 24. 2016-09-20 Tom Tromey <tom@tromey.com> * python/py-value.c (convert_value_from_python): Make PyInt_Check conditional on Python 2. * python/py-arch.c (archpy_disassemble): Make PyInt_Check conditional on Python 2.	10 years ago
Edjunior Barbosa Machado	9f7efd5bf7	ppc: Fix record support of Store String Word instructions gdb/ChangeLog 2016-09-20 Edjunior Barbosa Machado <emachado@linux.vnet.ibm.com> * rs6000-tdep.c (ppc_process_record_op31): Fix record of Store String Word instructions.	10 years ago
Andrew Burgess	d4ed4da3f5	ld: Fix mistake in ChangeLog The previous commit contained a small mistake in the ChangeLog, fixed in this commit.	10 years ago
Andrew Burgess	a5bf7d4fe7	ld: Extend documentation for EXCLUDE_FILE There was a gap in the documentation of EXCLUDE_FILE that could cause confusion to a user. When writing an input section specifier like this: (EXCLUDE_FILE (somefile.o) .text .text.) this could mean one of the following: 1. All '.text' and '.text.' from all files except for 'somefile.o', or 2. All '.text' from all files except 'somefile.o', and all '.text.' sections from all files. It turns out that the second interpretation is correct, but the manual does not make this clear (to me at least). Hopefully this patch makes things clearer. ld/ChangeLog: * ld/ld.texinfo (Input Section Basics): Expand the description of EXCLUDE_FILE.	10 years ago
Sergio Durigan Junior	7d5adfe311	Use 'event_ptid' instead of 'resume_ptid' on startup_inferior (fix for regression on my last commit) Pedro pointed out a regression happening on gdb.mi/mi-exec-run.exp, and as it turned out, this was a thinko when dealing with some events on startup_inferior. Basically, one needs to pass 'event_ptid' to target_mourn_inferior, but I mistakenly passed 'resume_ptid'. This commit fixes it. Built and regtested on BuildBot, now with fixed e-mail notifications! gdb/ChangeLog: 2016-09-20 Sergio Durigan Junior <sergiodj@redhat.com> * fork-inferior.c (startup_inferior): Pass 'event_ptid' instead of 'resume_ptid' to 'target_mourn_inferior'. Fix regression introduced by my last commit.	10 years ago
GDB Administrator	e8eafa2bf8	Automatic date update in version.in	10 years ago
Pedro Alves	6679754127	gdb: Fix build breakage with GCC 4.1 and --disable-nls Ref: https://sourceware.org/ml/gdb-patches/2016-09/msg00203.html The std::{min,max} patch caused build failures when configuring GDB with with --disable-nls and using GCC 4.1. The reason is this bit in common/gdb_locale.h: #ifdef ENABLE_NLS ... #else # define gettext(Msgid) (Msgid) ... #endif This causes problems if the <libintl.h> header is first included at any point after "gdb_locale.h". Specifically, the gettext&co declarations in libintl.h: extern char gettext (__const char __msgid) __THROW __attribute_format_arg__ (1); end up broken after preprocessing: extern char (__const char __msgid) throw () __attribute__ ((__format_arg__ (1))); After the std::min/std::max change to include <algorithm>, this now happens with at least the GCC 4.1 copy of <algorithm>, which includes <libintl.h> via <bits/stl_algobase.h>, <iosfwd>, and <bits/c++locale.h>. The fix is to simply remove the troublesome gettext and textdomain macros, leaving only the _ and N_ ones. gdb/ChangeLog: 2016-09-19 Pedro Alves <palves@redhat.com> * common/gdb_locale.h [!ENABLE_NLS] (gettext, dgettext, dcgettext, textdomain, bindtextdomain): Delete macros. * main.c (captured_main) [!ENABLE_NLS]: Skip bintextdomain and textdomain calls.	10 years ago
Jose E. Marchesi	b19753ce31	bfd: allow negative offsets to _GLOBAL_OFFSET_TABLE_ in elf64 SPARC The code compiled with the -fpic model in SPARC uses 13-bit signed immediate PC-relative loads to fetch entries from the GOT table. In theory this would allow using a GOT table (.got section) containing up to 1024 entries in elf32 or 512 entries in elf64. However, in elf64 sparc GNU targets _GLOBAL_OFFSET_TABLE_ is always placed at the beginning of the .got section, making it impossible to use negative offsets. This limits the usage of -fpic to GOT tables containing a maximum of 257 entries in elf64. This patch activates an optimization that is already used in sparc-elf32 also in sparc-elf64, that sets _GLOBAL_OFFSET_TABLE_ to point 0x1000 into the .got section if the section size is bigger than 0x1000. 2016-09-19 Jose E. Marchesi <jose.marchesi@oracle.com> * elfxx-sparc.c (_bfd_sparc_elf_size_dynamic_sections): Allow negative offsets to _GLOBAL_OFFSET_TABLE_ if the .got section is bigger than 0x1000 bytes.	10 years ago
Alan Modra	2387dd9049	nm handling of synthetic symbols Symbol sorting means we can't assume that the last n symbols are synthetic. * nm.c (print_symbol): Remove is_synthetic param. Test sym->flags instead. (print_size_symbols, print_symbols): Adjust to suit, deleting now unused synth_count param and fromsynth var. (display_rel_file): Adjust, localizing synth_count.	10 years ago
Sergio Durigan Junior	bc1e6c81d5	Consolidate target_mourn_inferior between GDB and gdbserver This patch consolidates the API of target_mourn_inferior between GDB and gdbserver, in my continuing efforts to make sharing the fork_inferior function possible between both. GDB's version of the function did not care about the inferior's ptid being mourned, but gdbserver's needed to know this information. Since it actually makes sense to pass the ptid as an argument, instead of depending on a global value directly (which GDB's version did), I decided to make the generic API to accept it. I then went on and extended all calls being made on GDB to include a ptid argument (which ended up being inferior_ptid most of the times, anyway), and now we have a more sane interface. On GDB's side, after talking to Pedro a bit about it, we decided that just an assertion to make sure that the ptid being passed is equal to inferior_ptid would be enough for now, on the GDB side. We can remove the assertion and perform more operations later if we ever pass anything different than inferior_ptid. Regression tested on our BuildBot, everything OK. I'd appreciate a special look at gdb/windows-nat.c's modification because I wasn't really sure what to do there. It seemed to me that maybe I should build a ptid out of the process information there, but then I am almost sure the assertion on GDB's side would trigger. gdb/ChangeLog: 2016-09-19 Sergio Durigan Junior <sergiodj@redhat.com> * darwin-nat.c (darwin_kill_inferior): Adjusting call to target_mourn_inferior to include ptid_t argument. * fork-child.c (startup_inferior): Likewise. * gnu-nat.c (gnu_kill_inferior): Likewise. * inf-ptrace.c (inf_ptrace_kill): Likewise. * infrun.c (handle_inferior_event_1): Likewise. * linux-nat.c (linux_nat_attach): Likewise. (linux_nat_kill): Likewise. * nto-procfs.c (interrupt_query): Likewise. (procfs_interrupt): Likewise. (procfs_kill_inferior): Likewise. * procfs.c (procfs_kill_inferior): Likewise. * record.c (record_mourn_inferior): Likewise. * remote-sim.c (gdbsim_kill): Likewise. * remote.c (remote_detach_1): Likewise. (remote_kill): Likewise. * target.c (target_mourn_inferior): Change declaration to accept new ptid_t argument; use gdb_assert on it. * target.h (target_mourn_inferior): Move function prototype from here... * target/target.h (target_mourn_inferior): ... to here. Adjust it to accept new ptid_t argument. * windows-nat.c (get_windows_debug_event): Adjusting call to target_mourn_inferior to include ptid_t argument. gdb/gdbserver/ChangeLog: 2016-09-19 Sergio Durigan Junior <sergiodj@redhat.com> * server.c (start_inferior): Call target_mourn_inferior instead of mourn_inferior; pass ptid_t argument to it. (resume): Likewise. (handle_target_event): Likewise. * target.c (target_mourn_inferior): New function. * target.h (mourn_inferior): Delete macro.	10 years ago
GDB Administrator	73cca75e7b	Automatic date update in version.in	10 years ago
Pedro Alves	93689493b3	gdb/s390: Fix build breakage due to std::min/std::max usage without header [...] .../gdb/s390-linux-nat.c: In function 'void s390_prepare_to_resume(lwp_info)': .../gdb/s390-linux-nat.c:703:20: error: 'min' is not a member of 'std' watch_lo_addr = std::min (watch_lo_addr, area->lo_addr); [...] gdb/ChangeLog: 2016-09-18 Pedro Alves <palves@redhat.com> s390-linux-nat.c: Include <algorithm>.	10 years ago
Pedro Alves	768adc05c4	gdb: Fix std::{min, max}-related build breakage on 32-bit hosts Building on a 32-bit host fails currently with errors like: .../src/gdb/exec.c: In function ‘target_xfer_status section_table_read_available_memory(gdb_byte, ULONGEST, ULONGEST, ULONGEST)’: .../src/gdb/exec.c:801:54: error: no matching function for call to ‘min(ULONGEST, long unsigned int)’ end = std::min (offset + len, r->start + r->length); ^ In file included from /usr/include/c++/5.3.1/algorithm:61:0, from .../src/gdb/exec.c:46: /usr/include/c++/5.3.1/bits/stl_algobase.h:195:5: note: candidate: template<class _Tp> const _Tp& std::min(const _Tp&, const _Tp&) min(const _Tp& __a, const _Tp& __b) ^ /usr/include/c++/5.3.1/bits/stl_algobase.h:195:5: note: template argument deduction/substitution failed: .../src/gdb/exec.c:801:54: note: deduced conflicting types for parameter ‘const _Tp’ (‘long long unsigned int’ and ‘long unsigned int’) end = std::min (offset + len, r->start + r->length); ^ In file included from /usr/include/c++/5.3.1/algorithm:61:0, from .../src/gdb/exec.c:46: /usr/include/c++/5.3.1/bits/stl_algobase.h:243:5: note: candidate: template<class _Tp, class _Compare> const _Tp& std::min(const _Tp&, const _Tp&, _Compare) min(const _Tp& __a, const _Tp& __b, _Compare __comp) ^ The problem is that the std::min/std::max function templates use the same type for both parameters. When the argument types are different, the compiler can't automatically deduce which template specialization to pick from the arguments' types. Fix that by specifying the specialization we want explicitly. gdb/ChangeLog: 2016-09-18 Pedro Alves <palves@redhat.com> * breakpoint.c (hardware_watchpoint_inserted_in_range): Explicitly specify the std:min/std::max specialization. * exec.c (section_table_read_available_memory): Likewise. * remote.c (remote_read_qxfer): Likewise. * target.c (simple_verify_memory): Likewise.	10 years ago
GDB Administrator	498f644143	Automatic date update in version.in	10 years ago
Eli Zaretskii	7f3c5ec870	Improve MinGW support in Readline These changes were already accepted upstream in Readline, but GDB did not yet import a newer Readline version. readline/Changelog.gdb: * util.c: Include rlshell.h. (_rl_tropen) [_WIN32 && !__CYGWIN__]: Open the trace file in the user's temporary directory. * tcap.h [HAVE_NCURSES_TERMCAP_H]: Include ncurses/termcap.h. * input.c (w32_isatty) [_WIN32 && !__CYGWIN__]: New function, to replace isatty that is not reliable enough on MS-Windows. (isatty) [_WIN32 && !__CYGWIN__]: Redirect to w32_isatty. (rl_getc): Call _getch, not getch, which could be an ncurses function when linked with ncurses, in which case getch will return EOF for any keystroke, because there's no curses window. * tilde.c (tilde_expand_word) [_WIN32]: * histfile.c (history_filename) [_WIN32]: Windows-specific environment variable to replace HOME if that is undefined. * funmap.c (default_funmap): Compile rl_paste_from_clipboard on all Windows platforms, not just Cygwin. * readline.h (rl_paste_from_clipboard): Include declaration for all Windows platforms. * display.c (insert_some_chars, delete_chars): Don't use the MinGW-specific code if linked with ncurses. * configure.in: * config.h.in: Support ncurses/termcap.h. The configure script was updated accordingly. * complete.c [_WIN32 && !__CYGWIN__]: Initialize _rl_completion_case_fold to 1. (printable_part, rl_filename_completion_function) [_WIN32 && !__CYGWIN__]: Handle the drive letter.	10 years ago
GDB Administrator	a3fa21cadc	Automatic date update in version.in	10 years ago
Simon Marchi	cd94f6d535	Introduce cleanup to restore current_uiout Make a globally available cleanup from a pre-existing one in infrun.c. This is used in a following patch. gdb/ChangeLog: * infrun.c (restore_current_uiout_cleanup): Move to ui-out.c. (print_stop_event): Use make_cleanup_restore_current_uiout. * python/python.c (execute_gdb_command): Likewise. * ui-out.c (restore_current_uiout_cleanup): Move from infrun.c. (make_cleanup_restore_current_uiout): New function definition. * ui-out.h (make_cleanup_restore_current_uiout): New function declaration. * utils.c (do_restore_ui_out): Remove. (make_cleanup_restore_ui_out): Remove. * utils.h (make_cleanup_restore_ui_out): Remove.	10 years ago
Pedro Alves	325fac504a	gdb: Use std::min and std::max throughout Otherwise including <string> or some other C++ header is broken. E.g.: In file included from /opt/gcc/include/c++/7.0.0/bits/char_traits.h:39:0, from /opt/gcc/include/c++/7.0.0/string:40, from /home/pedro/gdb/mygit/cxx-convertion/src/gdb/infrun.c:68: /opt/gcc/include/c++/7.0.0/bits/stl_algobase.h:243:56: error: macro "min" passed 3 arguments, but takes just 2 min(const _Tp& __a, const _Tp& __b, _Compare __comp) ^ /opt/gcc/include/c++/7.0.0/bits/stl_algobase.h:265:56: error: macro "max" passed 3 arguments, but takes just 2 max(const _Tp& __a, const _Tp& __b, _Compare __comp) ^ In file included from .../src/gdb/infrun.c:21:0: To the best of my grepping abilities, I believe I adjusted all min/max calls. gdb/ChangeLog: 2016-09-16 Pedro Alves <palves@redhat.com> * defs.h (min, max): Delete. * aarch64-tdep.c: Include <algorithm> and use std::min and std::max throughout. * aarch64-tdep.c: Likewise. * alpha-tdep.c: Likewise. * amd64-tdep.c: Likewise. * amd64-windows-tdep.c: Likewise. * arm-tdep.c: Likewise. * avr-tdep.c: Likewise. * breakpoint.c: Likewise. * btrace.c: Likewise. * ctf.c: Likewise. * disasm.c: Likewise. * doublest.c: Likewise. * dwarf2loc.c: Likewise. * dwarf2read.c: Likewise. * environ.c: Likewise. * exec.c: Likewise. * f-exp.y: Likewise. * findcmd.c: Likewise. * ft32-tdep.c: Likewise. * gcore.c: Likewise. * hppa-tdep.c: Likewise. * i386-darwin-tdep.c: Likewise. * i386-tdep.c: Likewise. * linux-thread-db.c: Likewise. * lm32-tdep.c: Likewise. * m32r-tdep.c: Likewise. * m88k-tdep.c: Likewise. * memrange.c: Likewise. * minidebug.c: Likewise. * mips-tdep.c: Likewise. * moxie-tdep.c: Likewise. * nds32-tdep.c: Likewise. * nios2-tdep.c: Likewise. * nto-procfs.c: Likewise. * parse.c: Likewise. * ppc-sysv-tdep.c: Likewise. * probe.c: Likewise. * record-btrace.c: Likewise. * remote.c: Likewise. * rs6000-tdep.c: Likewise. * rx-tdep.c: Likewise. * s390-linux-nat.c: Likewise. * s390-linux-tdep.c: Likewise. * ser-tcp.c: Likewise. * sh-tdep.c: Likewise. * sh64-tdep.c: Likewise. * source.c: Likewise. * sparc-tdep.c: Likewise. * symfile.c: Likewise. * target-memory.c: Likewise. * target.c: Likewise. * tic6x-tdep.c: Likewise. * tilegx-tdep.c: Likewise. * tracefile-tfile.c: Likewise. * tracepoint.c: Likewise. * valprint.c: Likewise. * value.c: Likewise. * xtensa-tdep.c: Likewise. * cli/cli-cmds.c: Likewise. * compile/compile-object-load.c: Likewise.	10 years ago
Andreas Arnez	8193adea2f	S390: Hardware breakpoint support Add hardware breakpoint support for S390 targets. gdb/ChangeLog: * s390-linux-nat.c (PER_BIT, PER_EVENT_BRANCH, PER_EVENT_IFETCH) (PER_EVENT_STORE, PER_EVENT_NULLIFICATION) (PER_CONTROL_BRANCH_ADDRESS, PER_CONTROL_SUSPENSION) (PER_CONTROL_ALTERATION): New macros. (struct s390_debug_reg_state) <break_areas>: New member. (s390_forget_process): Free break_areas as well. (s390_linux_new_fork): Copy break_areas as well. (s390_prepare_to_resume): Install hardware breakpoints. (s390_can_use_hw_breakpoint): Indicate support for hardware breakpoints. (s390_insert_hw_breakpoint, s390_remove_hw_breakpoint): New linux_nat target methods. (_initialize_s390_nat): Register them. gdb/testsuite/ChangeLog: * lib/gdb.exp: No longer skip hardware breakpoint tests on s390.	10 years ago
Andreas Arnez	0e00e962c5	linux-nat: Add function lwp_is_stepping Add the function lwp_is_stepping which indicates whether the given LWP is currently single-stepping. This is a common interface, usable from native GDB as well as from gdbserver. gdb/gdbserver/ChangeLog: * linux-low.c (lwp_is_stepping): New function. gdb/ChangeLog: * nat/linux-nat.h (lwp_is_stepping): New declaration. * linux-nat.c (lwp_is_stepping): New function.	10 years ago
Andreas Arnez	169fe0df15	S390: Enable "maint set show-debug-regs" Implement a new function for dumping the S390 "debug registers" (actually, the PER info) and invoke it at appropriate places. Respect the variable show_debug_regs and make it settable by the user. gdb/ChangeLog: * s390-linux-nat.c (gdbcmd.h): New include. (s390_show_debug_regs): New function. (s390_stopped_by_watchpoint): Call it, if show_debug_regs is set. (s390_prepare_to_resume): Likewise. (_initialize_s390_nat): Register the command "maint set show-debug-regs".	10 years ago
Andreas Arnez	373c3dad74	S390: Multi-inferior watchpoint support Support different sets of watchpoints in multiple inferiors. gdb/ChangeLog: * s390-linux-nat.c (watch_areas): Remove variable. Replace by a member of... (struct s390_debug_reg_state): ...this. New struct. (struct s390_process_info): New struct. (s390_process_list): New variable. (s390_find_process_pid, s390_add_process, s390_process_info_get) (s390_get_debug_reg_state): New functions. (s390_stopped_by_watchpoint): Now access the watch_areas VEC via s390_get_debug_reg_state. (s390_prepare_to_resume): Likewise. (s390_insert_watchpoint): Likewise. (s390_remove_watchpoint): Likewise. (s390_forget_process, s390_linux_new_fork): New linux_nat target methods. (_initialize_s390_nat): Register them.	10 years ago
Andreas Arnez	17c84ccaf0	S390: Migrate watch areas from list to VEC type For S390, the list of active watchpoints is maintained in a list based at "watch_base". This refactors the list to a vector "watch_areas". gdb/ChangeLog: * s390-linux-nat.c (s390_watch_area): New typedef. Define a VEC. (watch_base): Remove variable. (watch_areas): New variable. (s390_stopped_by_watchpoint): Transform operations on the watch_base list to equivalent operations on the watch_areas VEC. (s390_prepare_to_resume): Likewise. (s390_insert_watchpoint): Likewise. (s390_remove_watchpoint): Likewise.	10 years ago

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