binutils-gdb

Commit Graph

Author	SHA1	Message	Date
Joern Rennecke	ae51a426eb	2003-03-03 Andrew Stubbs <andrew.stubbs@superh.com> opcodes: * sh-dis.c (print_insn_sh): Don't disassemble fp instructions in nofpu mode. Add BFD type bfd_mach_sh4_nommu_nofpu. * sh-opc.h: Add sh4_nommu_nofpu architecture and adjust instructions accordingly. bfd: * archures.c: Add bfd_mach_sh4_nommu_nofpu. * cpu-sh.c: Ditto. * elf32-sh.c: Ditto. * bfd-in2.h: Regenerate. include/elf: * sh.h: Add EF_SH4_NOMMU_NOFPU. gas: * config/tc-sh.c (md_parse_option): Add -isa=sh4-nofpu and -isa=sh4-nommu-nofpu options. Adjust help messages accordingly. (sh_elf_final_processing): Output BFD type sh4_nofpu if that is the most general type or the user specifically requested it. (md_assemble): Add a new error message for when an instruction is understood, but is not allowed due to an -isa option.	23 years ago
Joern Rennecke	ce11586c0b	2004-02-26 Andrew Stubbs <andrew.stubbs@superh.com> * sh-opc.h: Move fsca and fsrra instructions from sh4a to sh4. Also correct mistake in the comment.	23 years ago
Joern Rennecke	6a5709a5a1	2004-02-23 Andrew Stubbs <andrew.stubbs@superh.com> gas: * tc-sh.c (build_Mytes): Add REG_N_D and REG_N_B01 nibble types to assembler. opcodes: * sh-dis.c (print_insn_sh): Add REG_N_D nibble type to ensure that double registers have even numbers. Add REG_N_B01 for nn01 (binary 01) nibble to ensure that reserved instruction 0xfffd does not decode the same as 0xfdfd (ftrv). * sh-opc.h: Add REG_N_D nibble type and use it whereever REG_N refers to a double register. Add REG_N_B01 nibble type and use it instead of REG_NM in ftrv. Adjust the bit patterns in a few comments.	23 years ago
Michael Snyder	17707c23a8	2004-01-27 Michael Snyder <msnyder@redhat.com> * sh-opc.h (sh_table): "fsrra", not "fssra".	23 years ago
Michael Snyder	aeadede63f	2003-12-02 Alexandre Oliva <aoliva@redhat.com> * sh-opc.h: Add support for sh4a and no-fpu variants. * sh-dis.c: Ditto.	23 years ago
Nick Clifton	5177500f26	Add SH2E support	24 years ago
Klee Dienes	84037f8c66	2002-11-18 Klee Dienes <kdienes@apple.com> * arc.h (arc_ext_opcodes): Declare as extern. (arc_ext_operands): Declare as extern. * i860.h (i860_opcodes): Declare as const. 2002-11-18 Klee Dienes <kdienes@apple.com> * arc-opc.c (arc_ext_opcodes): Define. (arc_ext_operands): Define. * i386-dis.c (Suffix3DNow): Declare as const. * arm-opc.h (arm_opcodes): Declare as const. (thumb_opcodes): Declare as const. * h8500-opc.h (h8500_table): Declare as const. (h8500_table): Use a NULL for the opcode in the terminator, so that code testing (opcode->name) behaves correctly. * mcore-opc.h (mcore_table): Declare as const. * sh-opc.h (sh_table): Declare as const. * w65-opc.h (optable): Declare as const. * z8k-opc.h (z8k_table): Declare as const.	24 years ago
Alexandre Oliva	0b3301c329	* sh-opc.h (sh_arg_type): Added A_DISP_PC_ABS.	25 years ago
Nick Clifton	ddb682659b	fix encoding & decoding of DSP single data transfer instructions	25 years ago
Alexandre Oliva	bda22bbf15	* sh-opc.h (sh_table): Don't use empty initializers.	26 years ago
Alexandre Oliva	9ab433aae8	* sh-opc.h (sh_table): Complete last element entry to avoid compiler warning.	26 years ago
Nick Clifton	060d22b0d0	Fix typos in ChangeLogs; fix dates in copyright notices	26 years ago
Alexandre Oliva	54a4ca2e1d	* sh-opc.h: The operand of `mov.w r0, (<disp>,GBR)' is IMM1, not 0.	26 years ago
Joern Rennecke	52ccafd035	opcodes: * sh-opc.c (sh_table): Use A_DISP_PC / PCRELIMM_8BY2 for ldre & ldrs. stc GBR,@-<REG_N> is available for arch_sh1_up. Group parallel processing insn with identical mnemonics together. Make three-operand psha / pshl come first. gas: * config/tc-sh.c (get_operands): There's no third operand if the first operand is an immediate.	27 years ago
Joern Rennecke	015551fcfb	sh-dsp REPEAT support: opcodes: * sh-opc.h (sh_nibble_type): Remove DISP_8 and DISP_4. Split IMM_[48]{,BY[24]} into IMM[01]_[48]{,BY[24]}. Add REPEAT. (sh_arg_type): Add A_PC. (sh_table): Update entries using immediates. Add repeat. * sh-dis.c (print_insn_shx): Remove DISP_8 and DISP_4. Split IMM_[48]{,BY[24]} into IMM[01]_[48]{,BY[24]}. Add REPEAT. gas: * config/tc-sh.c (immediate): Delete. (sh_operand_info): Add immediate member. (parse_reg): Use A_PC for pc. (parse_exp): Add second argument 'op'. All callers changed. (parse_at): Expect pc to be coded as A_PC. Use immediate field in op. (insert): Add fourth argument 'op'. All callers changed. (build_relax): Add second argument 'op'. All callers changed. (insert_loop_bounds): New function. (build_Mytes): Remove DISP_4. Split IMM_[48]{,BY[24]} into IMM[01]_[48]{,BY[24]}. Add REPEAT. (assemble_ppi): Use immediate field in operand. (sh_force_relocation): Handle BFD_RELOC_SH_LOOP_{START,END}. (md_apply_fix): Likewise. (tc_gen_reloc): Likewise. Check for a pcrel BFD_RELOC_SH_LABEL. include/coff: * sh.h (R_SH_LOOP_START, R_SH_LOOP_END): Define. include/elf: * sh.h (R_SH_LOOP_START, R_SH_LOOP_END): New RELOC_NUMBERs. bfd: * reloc.c (_bfd_relocate_contents): Add BFD_RELOC_SH_LOOP_START and BFD_RELOC_SH_LOOP_END. * elf32-sh.c (sh_elf_howto_tab): Change special_func to sh_elf_ignore_reloc for all entries that sh_elf_reloc used to ignore. Add entries for R_SH_LOOP_START and R_SH_LOOP_END. (sh_elf_reloc_loop): New function. (sh_elf_reloc): No need to test for always-to-be-ignored relocs any more. (sh_rel): Add entries for BFD_RELOC_SH_LOOP_{START,END}. (sh_elf_relocate_section): Handle BFD_RELOC_SH_LOOP_{START,END}. * bfd-in2.h, libbfd.h: Regenerate.	27 years ago
Joern Rennecke	05102e700f	* sh-opc.h (sh_table): ldre and ldrs have a signed displacement.	27 years ago
Joern Rennecke	d4845d5762	bfd: Reinstate bits of sh4 support that got accidentally deleted. Add sh-dsp support. bfd: * archures.c (bfd_mach_sh2, bfd_mach_sh_dsp): New macros. (bfd_mach_sh3_dsp): Likewise. (bfd_mach_sh4): Reinstate. (bfd_default_scan): Recognize 7410, 7708, 7729 and 7750. * bfd-in2.h: Regenerate. * coff-sh.c (struct sh_opcode): flags is no longer short. (USESAS, USESAS_REG, USESR8, SETSAS, SETSAS_REG): New macros. (sh_opcode41, sh_opcode42): Integrate as sh_opcode41. (sh_opcode01, sh_opcode02, sh_opcode40): Add sh-dsp opcodes. (sh_opcode41, sh_opcode4, sh_opcode80): Likewise. (sh_opcodes): No longer const. (sh_dsp_opcodef0, sh_dsp_opcodef): New arrays. (sh_insn_uses_reg): Check for USESAS and USESR8. (sh_insn_sets_reg, sh_insns_conflict): Check for SETSAS. (_bfd_sh_align_load_span): Return early for SH4. Modify sh_opcodes lookup table for sh-dsp / sh3-dsp. Take into account that field b of a parallel processing insn could be mistaken for a separate insn. * cpu-sh.c (arch_info_struct): New array elements for sh2, sh-dsp and sh3-dsp. Reinstate element for sh4. (SH2_NEXT, SH_DSP_NEXT, SH3_DSP_NEXT): New macros. (SH4_NEXT): Reinstate. (SH3_NEXT, SH3E_NEXT): Adjust. * elf-bfd.h (_sh_elf_set_mach_from_flags): Declare. * elf32-sh.c (sh_elf_set_private_flags): New function. (sh_elf_copy_private_data, sh_elf_set_mach_from_flags): Likewise. (sh_elf_merge_private_data): New function. (elf_backend_object_p, bfd_elf32_bfd_set_private_bfd_flags): Define. (bfd_elf32_bfd_copy_private_bfd_data): Define. (bfd_elf32_bfd_merge_private_bfd_data): Change to sh_elf_merge_private_data. gas: * config/tc-sh.c ("elf/sh.h"): Include. (sh_dsp, valid_arch, reg_x, reg_y, reg_efg): New static variables. (md.begin): Initialize target_arch. Only include opcodes in has table that match selected architecture. (parse_reg): Recognize register names for sh-dsp. (parse_at): Recognize post-modify addressing. (get_operands): The leading space is now optional. (get_specific): Remove FDREG_N support. Add support for sh-dsp arguments. Update valid_arch. (build_Mytes): Add support for SDT_REG_N. (find_cooked_opcode): New function, broken out of md_assemble. (assemble_ppi, sh_elf_final_processing): New functions. (md_assemble): Use find_cooked_opcode and assemble_ppi. (md_longopts, md_parse_option): New option: -dsp. * config/tc-sh.h (elf_tc_final_processing): Define. (sh_elf_final_processing): Declare. include/elf: * sh.h: (EF_SH_MACH_MASK, EF_SH_UNKNOWN, EF_SH1, EF_SH2): New macros. (EF_SH3, EF_SH_HAS_DSP, EF_SH_DSP, EF_SH3_DSP): Likewise. (EF_SH_HAS_FP, EF_SH3E, EF_SH4, EF_SH_MERGE_MACH): Likewise. opcodes: * sh-dis.c (print_movxy, print_insn_ddt, print_dsp_reg): New functions. (print_insn_ppi): Likewise. (print_insn_shx): Use info->mach to select appropriate insn set. Add support for sh-dsp. Remove FD_REG_N support. * sh-opc.h (sh_nibble_type): Add new values for sh-dsp support. (sh_arg_type): Likewise. Remove FD_REG_N. (sh_dsp_reg_nums): New enum. (arch_sh1, arch_sh2, arch_sh3, arch_sh3e, arch_sh4): New macros. (arch_sh_dsp, arch_sh3_dsp, arch_sh1_up, arch_sh2_up): Likewise. (arch_sh3_up, arch_sh3e_up, arch_sh4_up, arch_sh_dsp_up): Likewise. (arch_sh3_dsp_up): Likewise. (sh_opcode_info): New field: arch. (sh_table): Split up insn with FD_REG_N into ones with F_REG_N and D_REG_N. Fill in arch field. Add sh-dsp insns.	27 years ago
Nick Clifton	abf4be04fa	Fix bit patterns of some load/store instructions to match latest docs.	27 years ago
Nick Clifton	f45812f66a	Add patterns with correct names for mulu and muls instructions (mulu.w and muls.w)	27 years ago
Richard Henderson	252b5132c7	19990502 sourceware import	28 years ago
Stan Shebs	071ea11e85	Initial creation of sourceware repository	28 years ago
J.T. Conklin	60da007931	* sh-opc.h (sh_arg_type): Added A_SSR and A_SPC. (sh_table): Added many SH3 opcodes. * sh-dis.c (print_insn_shx): Added cases for A_SSR and A_SPC.	31 years ago
Jim Wilson	db29ae72fc	Fix bug in SH3e ftrc instruction.	31 years ago
Jim Wilson	9b39b1a8f7	Add some blank lines to improve readability.	31 years ago
Jeff Law	1ca31557f5	* sh-dis.c (print_insn_shx): Handle new operand types F_REG_N, F_REG_M, FPSCR_M, FPSCR_N, FPUL_M and FPUL_N. * sh-opc.h (sh_arg_type): Add new operand types. (sh_table): Add new opcodes from SH3E Floating Point ISA. sh3e stuff. Sanitized out for now.	31 years ago
Steve Chamberlain	1ff71ed037	Wed May 24 14:16:08 1995 Steve Chamberlain <sac@slash.cygnus.com> * sh-opc.h: Added bsrf and braf.	32 years ago
Steve Chamberlain	a90a64c168	* sh-opc.h (mov.l gbr): Get direction right. * sh-dis.c (print_insn_shx): New function. (print_insn_shl, print_insn_sh): Call print_insn_shx to print opcodes with right byte order.	32 years ago

20 Commits (20135044c7ac6db1ae40cd8623d595fe7b8a2c6c)