binutils-gdb

Commit Graph

Author	SHA1	Message	Date
Jan Beulich	1424ad8677	x86: also optimize KXOR{D,Q} and KANDN{D,Q} These can be converted to 2-byte VEX encoding when both source registers are the same, by using KXORW / KANDNW as replacement.	8 years ago
Jan Beulich	ae2387feae	x86: fold various AVX512 templates with so far differing Masking attributes There's no insn allowing ZEROING_MASKING alone. Re-purpose its value for handling the not uncommon case of insns allowing either form of masking with register operands, but only merging masking with a memory operand.	8 years ago
Jan Beulich	6ff00b5e12	x86/Intel: correct permitted operand sizes for AVX512 scatter/gather AVX gather insns correctly allow the element size to be specified rather than the full vector size. Make AVX512 ones match.	8 years ago
Jan Beulich	e951d5ca3d	x86: drop CpuVREX It is fully redundant with CpuAVX512F.	8 years ago
Jim Wilson	eb41b24898	RISC-V: Set insn info fields correctly when disassembling. include/ * opcode/riscv.h (INSN_TYPE, INSN_BRANCH, INSN_CONDBRANCH, INSN_JSR) (INSN_DREF, INSN_DATA_SIZE, INSN_DATA_SIZE_SHIFT, INSN_1_BYTE) (INSN_2_BYTE, INSN_4_BYTE, INSN_8_BYTE, INSN_16_BYTE): New. opcodes/ * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size fields. * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.	8 years ago
Andrew Jenner	b8891f8d62	Add support for the C_SKY series of processors. This patch series is a new binutils port for C-SKY processors, including support for both the V1 and V2 processor variants. V1 is derived from the MCore architecture while V2 is substantially different, with mixed 16- and 32-bit instructions, a larger register set, a different (but overlapping) ABI, etc. There is support for bare-metal ELF targets and Linux with both glibc and uClibc. This code is being contributed jointly by C-SKY Microsystems and Mentor Graphics. C-SKY is responsible for the technical content and has proposed Lifang Xia and Yunhai Shang as port maintainers. (Note that C-SKY does have a corporate copyright assignment on file with the FSF.) Mentor Graphics' role has been cleaning up the code, adding documentation and additional test cases, etc, to address issues we anticipated reviewers would complain about. bfd * Makefile.am (ALL_MACHINES, ALL_MACHINES_CFILES): Add C-SKY. (BFD32_BACKENDS, BFD_BACKENDS_CFILES): Likewise. * Makefile.in: Regenerated. * archures.c (enum bfd_architecture): Add bfd_arch_csky and related bfd_mach defines. (bfd_csky_arch): Declare. (bfd_archures_list): Add C-SKY. * bfd-in.h (elf32_csky_build_stubs): Declare. (elf32_csky_size_stubs): Declare. (elf32_csky_next_input_section: Declare. (elf32_csky_setup_section_lists): Declare. * bfd-in2.h: Regenerated. * config.bfd: Add C-SKY. * configure.ac: Likewise. * configure: Regenerated. * cpu-csky.c: New file. * elf-bfd.h (enum elf_target_id): Add C-SKY. * elf32-csky.c: New file. * libbfd.h: Regenerated. * reloc.c: Add C-SKY relocations. * targets.c (csky_elf32_be_vec, csky_elf32_le_vec): Declare. (_bfd_target_vector): Add C-SKY target vector entries. binutils* readelf.c: Include elf/csky.h. (guess_is_rela): Handle EM_CSKY. (dump_relocations): Likewise. (get_machine_name): Likewise. (is_32bit_abs_reloc): Likewise. include * dis-asm.h (csky_symbol_is_valid): Declare. * opcode/csky.h: New file. opcodes * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c. * Makefile.in: Regenerated. * configure.ac: Add C-SKY. * configure: Regenerated. * csky-dis.c: New file. * csky-opc.h: New file. * disassemble.c (ARCH_csky): Define. (disassembler, disassemble_init_for_target): Add case for ARCH_csky. * disassemble.h (print_insn_csky, csky_get_disassembler): Declare. gas * Makefile.am (TARGET_CPU_CFILES): Add entry for C-SKY. (TARGET_CPU_HFILES, TARGET_ENV_HFILES): Likewise. * Makefile.in: Regenerated. * config/tc-csky.c: New file. * config/tc-csky.h: New file. * config/te-csky_abiv1.h: New file. * config/te-csky_abiv1_linux.h: New file. * config/te-csky_abiv2.h: New file. * config/te-csky_abiv2_linux.h: New file. * configure.tgt: Add C-SKY. * doc/Makefile.am (CPU_DOCS): Add entry for C-SKY. * doc/Makefile.in: Regenerated. * doc/all.texi: Set CSKY feature. * doc/as.texi (Overview): Add C-SKY options. (Machine Dependencies): Likewise. * doc/c-csky.texi: New file. * testsuite/gas/csky/: New test cases. ld Makefile.am (ALL_EMULATION_SOURCES): Add C-SKY emulations. (ecskyelf.c, ecskyelf_linux.c): New rules. * Makefile.in: Regenerated. * configure.tgt: Add C-SKY. * emulparams/cskyelf.sh: New file. * emulparams/cskyelf_linux.sh: New file. * emultempl/cskyelf.em: New file. * gen-doc.texi: Add C-SKY. * ld.texi: Likewise. (Options specific to C-SKY targets): New section. * testsuite/ld-csky/*: New tests.	8 years ago
Alan Modra	16065af1b0	Re: PowerPC Improve support for Gekko & Broadway PowerPC has replaced use of "long" for insns with "int64_t", in preparation for 64-bit power10 insns. * ppc-opc.c (insert_sprbat): Correct function parameter and return type. (extract_sprbat): Likewise, variable too.	8 years ago
Alex Chadwick	fa758a7046	PowerPC Improve support for Gekko & Broadway This is a relatively straightforward patch to improve support for the IBM Gekko and IBM Broadway processors. Broadway is functionally equivalent to the IBM 750CL, while Gekko's functionality is a subset of theirs. The patch simplifies this reality and adds -mgekko and -mbroadway as aliases for -m750cl. I didn't feel it was worth wasting a PPC_OPCODE_* bit to differentiate Gekko. The patch adds a number of simplified mnemonics for special purpose register access. Notably, Broadway adds 4 additional IBAT and DBAT registers but these are not assigned sequential SPR numbers. gas/ * config/tc-ppc.c (md_show_usage): Add -mgekko and -mbroadway. * doc/as.texi (Target PowerPC options): Add -mgekko and -mbroadway. * doc/c-ppc.texi (PowerPC-Opts): Likewise. * testsuite/gas/ppc/broadway.d, * testsuite/gas/ppc/broadway.s: New test for broadway. * testsuite/gas/ppc/ppc.exp: Run new test. include/ * opcode/ppc.h (PPC_OPCODE_750): Adjust comment. opcodes/ * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway. (powerpc_init_dialect): Handle bfd_mach_ppc_750. * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to support disjointed BAT. (powerpc_operands): Allow extra bit in SPRBAT_MASK. Add SPRGQR. (XSPRGQR_MASK, GEKKO, BROADWAY): Define. (powerpc_opcodes): Add 750cl extended mnemonics for spr access.	8 years ago
H.J. Lu	4a1b91eabb	x86: Expand Broadcast to 3 bits Expand Broadcast to 3 bits so that the number of bytes to broadcast can be computed as 1 << (Broadcast - 1). Use it to simplify x86 assembler. gas/ * config/tc-i386.c (Broadcast_Operation): Add bytes. (build_evex_prefix): Use i.broadcast->bytes. (match_broadcast_size): New function. (check_VecOperands): Use the broadcast field to compute the number of bytes to broadcast directly. Set i.broadcast->bytes. Use match_broadcast_size. opcodes/ * i386-gen.c (adjust_broadcast_modifier): New function. (process_i386_opcode_modifier): Add an argument for operands. Adjust the Broadcast value based on operands. (output_i386_opcode): Pass operand_types to process_i386_opcode_modifier. (process_i386_opcodes): Pass NULL as operands to process_i386_opcode_modifier. * i386-opc.h (BYTE_BROADCAST): New. (WORD_BROADCAST): Likewise. (DWORD_BROADCAST): Likewise. (QWORD_BROADCAST): Likewise. (i386_opcode_modifier): Expand broadcast to 3 bits. * i386-tbl.h: Regenerated.	8 years ago
Alan Modra	67ce483baa	PR23430, Indices misspelled PR 23430 include/ * elf/common.h (SHT_SYMTAB_SHNDX): Fix comment typo. bfd/ * dwarf2.c (dwarf_debug_section_enum): Fix comment typo. * elf.c (bfd_section_from_shdr, elf_sort_sections): Likewise. binutils/ * elfcomm.h (struct archive_info): Rename uses_64bit_indicies to uses_64bit_indices. * elfcomm.c (setup_archive): Update uses of above. * readelf.c (process_archive): Likewise. (get_section_type_name): Rename indicies to indices. (get_32bit_elf_symbols, get_64bit_elf_symbols): Likewise. (process_section_groups): Likewise. cpu/ * or1kcommon.cpu (spr-reg-indices): Fix description typo. opcodes/ * or1k-desc.h: Regenerate.	8 years ago
Jan Beulich	4174bfff8a	x86-64: correct AVX512F vcvtsi2s{d,s} handling Just like for their AVX counterparts and CVTSI2S{D,S}, a memory source here is ambiguous and hence - in source files should be qualified with a suitable suffix or operand size specifier (not doing so is an error in Intel mode, and will gain a diagnostic in AT&T mode in the future), - in disassembly should be properly suffixed (the Intel operand size specifiers were emitted correctly already).	8 years ago
Claudiu Zissulescu	04e65276fa	[ARC] Fix decoding of w6 signed short immediate. gas/ Claudiu Zissulescu <claziss@synopsys.com> * testsuite/gas/arc/st.d: Fix test. opcodes/ Claudiu Zissulescu <claziss@synopsys.com> * arc-opc.c (extract_w6): Fix extending the sign.	8 years ago
Claudiu Zissulescu	47e6f81c7c	[ARC] Allow vewt instruction for ARC EM family. opcode/ Claudiu Zissulescu <claziss@synopsys.com> * arc-tbl.h (vewt): Allow it for ARC EM family.	8 years ago
Alan Modra	bb71536f28	power9 mfupmc/mtupmc PR 23419 * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended opcode variants for mtspr/mfspr encodings.	8 years ago
Chenghua Xu	8095d2f70e	MIPS/GAS: Split Loongson MMI Instructions from loongson2f/3a The MMI instruction set has been implemented in many Loongson processors. There is a lot of software optimized for MMI. This patch splits MMI from loongson2f/3a, and adds GAS and disassembler options for MMI instructions. 2018-07-20 Chenghua Xu <paul.hua.gm@gmail.com> Maciej W. Rozycki <macro@mips.com> bfd/ * elfxx-mips.c (print_mips_ases): Add MMI extension. binutils/ * readelf.c (print_mips_ases): Add MMI extension. gas/ * NEWS: Mention MultiMedia extensions Instructions (MMI) support. * config/tc-mips.c (options): Add OPTION_LOONGSON_MMI and OPTION_NO_LOONGSON_MMI. (md_longopts): Likewise. (mips_ases): Define availability for MMI. (mips_convert_ase_flags): Map ASE_LOONGSON_MMI to AFL_ASE_LOONGSON_MMI. (mips_cpu_info_table): Add ASE_LOONGSON_MMI for loongson2f/3a. (md_show_usage): Add help for -mloongson-mmi and -mno-loongson-mmi. * doc/as.texi: Document -mloongson-mmi, -mno-loongson-mmi. * doc/c-mips.texi: Document -mloongson-mmi, -mno-loongson-mmi, .set loongson-mmi and .set noloongson-mmi. * testsuite/gas/mips/loongson-2f.d: Move mmi test to ... * testsuite/gas/mips/loongson-2f-mmi.d: Here. Add ISA/ASE flag verification. * testsuite/gas/mips/loongson-2f.s: Move mmi test to ... * testsuite/gas/mips/loongson-2f-mmi.s: Here. * testsuite/gas/mips/loongson-3a.d: Move mmi test to ... * testsuite/gas/mips/loongson-3a-mmi.d: Here. Add ISA/ASE flag verification. * testsuite/gas/mips/loongson-3a.s: Move mmi test to ... * testsuite/gas/mips/loongson-3a-mmi.s: Here. * testsuite/gas/mips/mips.exp: Run loongson-2f-mmi and loongson-3a-mmi tests. include/ * elf/mips.h (AFL_ASE_MMI): New macro. (AFL_ASE_MASK): Update to include AFL_ASE_LOONGSON_MMI. * opcode/mips.h (ASE_LOONGSON_MMI): New macro. opcodes/ * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and loongson3a descriptors. (parse_mips_ase_option): Handle -M loongson-mmi option. (print_mips_disassembler_options): Document -M loongson-mmi. * mips-opc.c (LMMI): New macro. (mips_opcodes): Replace IL2F\|IL3A marking with LMMI for MMI instructions.	8 years ago
Jan Beulich	5f32791e1e	x86: fold narrowing VCVT* templates When multiple (here: two) forms of an insn take different width inputs but produce identical size outputs (here: RegXMM), the templates can be combined. Also drop IgnoreSize (and the now redundant size specifiers) wherever applicable.	8 years ago
Jan Beulich	625cbd7ac1	x86: fold VFPCLASSP{D,S} templates These are special because they may not have a register operand to derive the vector length from, which requires to also deal with the braodcast case when determining vector length in build_evex_prefix(). Also drop IgnoreSize (and the now redundant size specifiers) from their suffixed counterparts.	8 years ago
Jan Beulich	86b15c3204	x86: fold various AVX512* templates	8 years ago
Jan Beulich	cf769ed505	x86: fold various AVX512DQ templates	8 years ago
Jan Beulich	8282b7ad0d	x86: fold various AVX512BW templates	8 years ago
Jan Beulich	755908cce5	x86: fold various AVX512CD templates	8 years ago
Jan Beulich	7091c61201	x86: fold various AVX512VL templates into their AVX512F counterparts	8 years ago
Jan Beulich	c30be56ebf	x86: pre-process opcodes table before parsing Instead of expanding macro-like constructs in i386-gen, have the C pre- processor do this for us. Besides being a prerequisite for the next template folding steps, this also paves the way for removing various hidden dependencies between #define-s in i386-opc.h and plain literal numbers used in i386-opc.tbl. The #undef of None is solely to leave the generated i386-tbl.h entirely unchanged.	8 years ago
H.J. Lu	11a322db5c	x86: Split vcvtps2{,u}qq and vcvttps2{,u}qq After commit `1b54b8d7e4` Author: Jan Beulich <jbeulich@novell.com> Date: Mon Dec 18 09:36:14 2017 +0100 x86: fold RegXMM/RegYMM/RegZMM into RegSIMD ... qualified by their respective sizes, allowing to drop FirstXmm0 at the same time. folded RegXMM, RegYMM and RegZMM into RegSIMD, it's no longer impossible to distinguish if Xmmword can represent a memory reference when operand specification contains SIMD register. For example, template operands specification like these RegXMM\|...\|Xmmword\|... and RegXMM\|... The Xmmword bitfield is always set by RegXMM which is represented by "RegSIMD\|Xmmword". This patch splits each of vcvtps2qq, vcvtps2uqq, vcvttps2qq and vcvttps2uqq into 2 templates: one template only has RegXMM source operand and the other only has mempry source operand. gas/ PR gas/23418 * testsuite/gas/i386/xmmword.s: Add tests for vcvtps2qq, vcvtps2uqq, vcvttps2qq and vcvttps2uqq. * testsuite/gas/i386/xmmword.l: Updated. opcodes/ PR gas/23418 * i386-opc.h (Byte): Update comments. (Word): Likewise. (Dword): Likewise. (Fword): Likewise. (Qword): Likewise. (Tbyte): Likewise. (Xmmword): Likewise. (Ymmword): Likewise. (Zmmword): Likewise. * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and vcvttps2uqq. * i386-tbl.h: Regenerated.	8 years ago
Nick Clifton	cde3679eb5	This patch adds support for the SSBB and PSSBB speculation barrier instructions to the AArch64 assembler and disassembler. For more details see: https://static.docs.arm.com/ddi0596/a/DDI_0596_ARM_a64_instruction_set_architecture.pdf opcodes * aarch64-tbl.h (aarch64_opcode_table): Add entry for ssbb and pssbb and update dsb flags to F_HAS_ALIAS. * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate. * aarch64-opc-2.c: Regenerate. gas * testsuite/gas/aarch64/system.s: Add test for ssbb and pssbb. * testsuite/gas/aarch64/system.d: Update accordingly and remove explicit addresses.	8 years ago
Tamar Christina	45a28947f3	Add remainder of Em16 restrictions for AArch64 gas. This adds the missing Em16 constraints the rest of the instructions requiring them and also adds a testcase to test all the instructions so these are checked from now on. The Em16 operand constrains the valid registers to the lower 16 registers when used with a half precision qualifier. The list has been cross checked (by hand) through the Arm ARM version Ca. opcodes/ PR binutils/23192 * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2, mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal, umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull, sqdmulh, sqrdmulh): Use Em16. gas/ PR binutils/23192 * testsuite/gas/aarch64/illegal-by-element.s: New. * testsuite/gas/aarch64/illegal-by-element.d: New. * testsuite/gas/aarch64/illegal-by-element.l: New.	8 years ago
Sudakshina Das	c597cc3d6e	Adds the speculation barrier instructions to the ARM assembler and disassembler. See: https://developer.arm.com/support/arm-security-updates/speculative-processor-vulnerability/download-the-whitepaper opcodes * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move csdb together with them. (thumb32_opcodes): Likewise. gas * config/tc-arm.c (insns): Add new ssbb and pssbb instructions. * testsuite/gas/arm/csdb.s: Add new tests for ssbb and pssbb. * testsuite/gas/arm/csdb.d: Likewise * testsuite/gas/arm/thumb2_it_bad.s: Likewise. * testsuite/gas/arm/thumb2_it_bad.l: Likewise. * testsuite/gas/arm/barrier.d: Update with ssbb. * testsuite/gas/arm/barrier-thumb.d: Likewise.	8 years ago
Jan Beulich	a79eaed6a5	x86: adjust monitor/mwait templates Architecturally, MONITOR's and MONITORX'es memory operand is a 16- or 32-bit register outside of 64-bit mode, and a 64- or 32-bit register inside 64-bit mode. The other register operands, including all of them for MWAIT and MWAITX, are uniformly 32-bit, irrespective of mode. Retain the original 64-bit MONITOR{,X} templates for compatibility only, and fold the MWAIT{,X} ones.	8 years ago
Jan Beulich	2fb5be8dac	x86: drop {,reg16_}inoutportreg variables The checking against reg16_inoutportreg can be had with a simple test of a bit, and the value setting from inoutportreg can be replaced by using the actual register's reg_type field. Note that the so far redundant 2nd instance of OPERAND_TYPE_INOUTPORTREG is left in place, for its use in type_names[].	8 years ago
Jan Beulich	7f5cad3047	x86/Intel: accept memory operand size specifiers for CET insns	8 years ago
Jan Beulich	f0a85b0706	x86: replace off-by-one OTMax With its name it should equal to the largest prior enumerator, which is not very helpful as that will change every once in a while. Rename it to OTNum instead to make name and value match, and correct use sites to no longer use one too large a value.	8 years ago
Maciej W. Rozycki	9dcb0ba445	S12Z/opcodes: Correct a `reg' global shadowing error for pre-4.8 GCC Remove `-Wshadow' compilation errors: cc1: warnings being treated as errors .../opcodes/s12z-dis.c: In function 'lea_reg_xys_opr': .../opcodes/s12z-dis.c:814: error: declaration of 'reg' shadows a global declaration .../opcodes/s12z-dis.c:783: error: shadowed declaration is here .../opcodes/s12z-dis.c: In function 'lea_reg_xys': .../opcodes/s12z-dis.c:843: error: declaration of 'reg' shadows a global declaration .../opcodes/s12z-dis.c:783: error: shadowed declaration is here .../opcodes/s12z-dis.c: In function 'print_insn_loop_primitive': .../opcodes/s12z-dis.c:2206: error: declaration of 'reg' shadows a global declaration .../opcodes/s12z-dis.c:783: error: shadowed declaration is here which for versions of GCC before 4.8 prevent support for S12Z targets from being built. See also GCC PR c/53066. opcodes/ * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to `reg_xys'. (lea_reg_xys): Likewise. (print_insn_loop_primitive): Rename `reg' local variable to `reg_dxy'.	8 years ago
Tamar Christina	f311ba7ed8	Fix SBO bit in disassembly mask for ldrah on AArch64. The disassembly mask for ldarh incorrectly didn't mask out bit 20 which is part of the SBO part of the instruction and shouldn't be considered input. This fixes the wrong bit fixing the disassembly of instructions to ldarh and makes the behavior consistent. opcodes/ PR binutils/23242 * aarch64-tbl.h (ldarh): Fix disassembly mask.	8 years ago
Tamar Christina	cba05feb51	Fix the read/write flag for these registers on AArch64 The previous constraints were based on information already in opcodes and it seems that a few of them were wrong. I have now hand verified the ones changed by the previous patch and corrected where needed. This prevents a warning to be issued when one shouldn't be. opcodes/ PR binutils/23369 * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1, vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1. gas/testsuite/ PR binutils/23369 * gas/aarch64/msr.d (csselr_el1, vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1): New. * gas/aarch64/msr.s: Likewise.	8 years ago
Maciej W. Rozycki	471b9d1507	GDB PR tdep/8282: MIPS: Wire in `set disassembler-options' Implement MIPS target support for passing options to the disassembler, complementing commit `65b48a8140` ("GDB: Add support for the new set/show disassembler-options commands."). This includes options that expect an argument, so adjust the generic code and data structures used so as to handle such options. So as to give backends syntax flexibility no specific delimiter has been defined to separate options from their respective arguments, so it has to be included as the last character of the option name. Completion code however has not been adjusted and consequently option arguments cannot be completed at this time. Also the MIPS target has non-empty defaults for the options, so that ABI names for the general-purpose registers respect our `set mips abi ...' setting rather than always being determined from the ELF headers of the binary file selected. Handle these defaults as implicit options, never shown to the user and always prepended to the user-specified options, so that the latters can override the defaults. The resulting output for the MIPS target is as follows: (gdb) show disassembler-options The current disassembler options are '' The following disassembler options are supported for use with the 'set disassembler-options <option>[,<option>...]' command: no-aliases Use canonical instruction forms. msa Recognize MSA instructions. virt Recognize the virtualization ASE instructions. xpa Recognize the eXtended Physical Address (XPA) ASE instructions. ginv Recognize the Global INValidate (GINV) ASE instructions. gpr-names=ABI Print GPR names according to specified ABI. Default: based on binary being disassembled. fpr-names=ABI Print FPR names according to specified ABI. Default: numeric. cp0-names=ARCH Print CP0 register names according to specified architecture. Default: based on binary being disassembled. hwr-names=ARCH Print HWR names according to specified architecture. Default: based on binary being disassembled. reg-names=ABI Print GPR and FPR names according to specified ABI. reg-names=ARCH Print CP0 register and HWR names according to specified architecture. For the options above, the following values are supported for "ABI": numeric 32 n32 64 For the options above, the following values are supported for "ARCH": numeric r3000 r3900 r4000 r4010 vr4100 vr4111 vr4120 r4300 r4400 r4600 r4650 r5000 vr5400 vr5500 r5900 r6000 rm7000 rm9000 r8000 r10000 r12000 r14000 r16000 mips5 mips32 mips32r2 mips32r3 mips32r5 mips32r6 mips64 mips64r2 mips64r3 mips64r5 mips64r6 interaptiv-mr2 sb1 loongson2e loongson2f loongson3a octeon octeon+ octeon2 octeon3 xlr xlp (gdb) which corresponds to what `objdump --help' used to print for the MIPS target, with minor formatting changes, most notably option argument lists being wrapped, but also the amount of white space separating options from the respective descriptions. The relevant part the new code is now also used by `objdump --help', which means these formatting changes apply to both outputs, except for argument list wrapping, which is GDB-specific. This also adds a separating new line between the heading and option lists where descriptions are provided, hence: (gdb) set architecture s390:31-bit (gdb) show disassembler-options The current disassembler options are '' The following disassembler options are supported for use with the 'set disassembler-options <option>[,<option>...]' command: esa Disassemble in ESA architecture mode zarch Disassemble in z/Architecture mode insnlength Print unknown instructions according to length from first two bits (gdb) but: (gdb) set architecture powerpc:common (gdb) show disassembler-options The current disassembler options are '' The following disassembler options are supported for use with the 'set disassembler-options <option>[,<option>...]' command: 403, 405, 440, 464, 476, 601, 603, 604, 620, 7400, 7410, 7450, 7455, 750cl, 821, 850, 860, a2, altivec, any, booke, booke32, cell, com, e200z4, e300, e500, e500mc, e500mc64, e5500, e6500, e500x2, efs, efs2, power4, power5, power6, power7, power8, power9, ppc, ppc32, 32, ppc64, 64, ppc64bridge, ppcps, pwr, pwr2, pwr4, pwr5, pwr5x, pwr6, pwr7, pwr8, pwr9, pwrx, raw, spe, spe2, titan, vle, vsx (gdb) Existing affected target backends have been adjusted accordingly. This has been verified manually with: (gdb) set architecture arm (gdb) set architecture powerpc:common (gdb) set architecture s390:31-bit to cause no issues with the `show disassembler-options' and `set disassembler-options' commands. A test case for the MIPS target has also been provided, covering the default settings with ABI overrides as well as disassembler option overrides. 2018-07-02 Maciej W. Rozycki <macro@mips.com> Simon Marchi <simon.marchi@polymtl.ca> include/ PR tdep/8282 * dis-asm.h (disasm_option_arg_t): New typedef. (disasm_options_and_args_t): Likewise. (disasm_options_t): Add `arg' member, document members. (disassembler_options_mips): New prototype. (disassembler_options_arm, disassembler_options_powerpc) (disassembler_options_s390): Update prototypes. opcodes/ PR tdep/8282 * mips-dis.c (mips_option_arg_t): New enumeration. (mips_options): New variable. (disassembler_options_mips): New function. (print_mips_disassembler_options): Reimplement in terms of `disassembler_options_mips'. * arm-dis.c (disassembler_options_arm): Adapt to using the `disasm_options_and_args_t' structure. * ppc-dis.c (disassembler_options_powerpc): Likewise. * s390-dis.c (disassembler_options_s390): Likewise. gdb/ PR tdep/8282 * disasm.h (gdb_disassembler): Add `m_disassembler_options_holder'. member * disasm.c (get_all_disassembler_options): New function. (gdb_disassembler::gdb_disassembler): Use it. (gdb_buffered_insn_length_init_dis): Likewise. (gdb_buffered_insn_length): Adjust accordingly. (set_disassembler_options): Handle options with arguments. (show_disassembler_options_sfunc): Likewise. Add a leading new line if showing options with descriptions. (disassembler_options_completer): Adapt to using the `disasm_options_and_args_t' structure. * mips-tdep.c (mips_disassembler_options): New variable. (mips_disassembler_options_o32): Likewise. (mips_disassembler_options_n32): Likewise. (mips_disassembler_options_n64): Likewise. (gdb_print_insn_mips): Don't set `disassembler_options'. (gdb_print_insn_mips_n32, gdb_print_insn_mips_n64): Remove functions. (mips_gdbarch_init): Always set `gdbarch_print_insn' to `gdb_print_insn_mips'. Set `gdbarch_disassembler_options', `gdbarch_disassembler_options_implicit' and `gdbarch_valid_disassembler_options'. * arm-tdep.c (_initialize_arm_tdep): Adapt to using the `disasm_options_and_args_t' structure. * gdbarch.sh (disassembler_options_implicit): New `gdbarch' method. (valid_disassembler_options): Switch from `disasm_options_t' to the `disasm_options_and_args_t' structure. * NEWS: Document `set disassembler-options' support for the MIPS target. * gdbarch.h: Regenerate. * gdbarch.c: Regenerate. gdb/doc/ PR tdep/8282 * gdb.texinfo (Source and Machine Code): Document `set disassembler-options' support for the MIPS target. gdb/testsuite/ PR tdep/8282 * gdb.arch/mips-disassembler-options.exp: New test. * gdb.arch/mips-disassembler-options.s: New test source.	8 years ago
Thomas Preud'homme	c0c468d562	[ARM] Update bfd's Tag_CPU_arch knowledge BFD's bfd_get_mach () function returns a bfd specific value representing the architecture of the target which is populated from the Tag_CPU_arch build attribute value of that target. Among other users of that interfacem, objdump which uses it to print the architecture version of the binary being examinated and to decide what instruction is available if run with "-m arm" via its own mapping from bfd_mach_arm_X values to feature bits available. However, both BFD and objdump's most recent known architecture is Armv5TE. When encountering a newer architecture bfd_get_mach will return bfd_mach_arm_unknown. This is unfortunate since objdump uses that value to allow all instructions on all architectures which is already what it does by default, making the "-m arm" trick useless. This patch updates BFD and objdump's knowledge of Arm architecture versions up to the latest Armv8-M Baseline and Mainline, Armv8-R and Armv8.4-A architectures. Since several architecture versions (eg. 8.X-A) share the same Tag_CPU_arch build attribute value and bfd_mach_arm values, the mapping from bfd machine value to feature bits need to return the most featureful feature bits that would yield the given bfd machine value otherwise some instruction would not disassemble under "-m arm" mode. The patch rework that mapping to make this clearer and simplify writing the mapping rules. In particular, for simplicity all FPU instructions are allowed in all cases. Finally, the patch also rewrite the cpu_arch_ver table in GAS to use the TAG_CPU_ARCH_X macros rather than hardcode their value. 2018-07-02 Thomas Preud'homme <thomas.preudhomme@arm.com> bfd/ * archures.c (bfd_mach_arm_5TEJ, bfd_mach_arm_6, bfd_mach_arm_6KZ, bfd_mach_arm_6T2, bfd_mach_arm_6K, bfd_mach_arm_7, bfd_mach_arm_6M, bfd_mach_arm_6SM, bfd_mach_arm_7EM, bfd_mach_arm_8, bfd_mach_arm_8R, bfd_mach_arm_8M_BASE, bfd_mach_arm_8M_MAIN): Define. * bfd-in2.h: Regenerate. * cpu-arm.c (arch_info_struct): Add entries for above new bfd_mach_arm values. * elf32-arm.c (bfd_arm_get_mach_from_attributes): Add Tag_CPU_arch to bfd_mach_arm mapping logic for pre Armv4 and Armv5TEJ and later architectures. Force assert failure for any new Tag_CPU_arch value. gas/ * config/tc-arm.c (cpu_arch_ver): Use symbolic TAG_CPU_ARCH macros rather than hardcode their values. ld/ * arm-dis.c (select_arm_features): Fix typo in heading comment. Allow all FPU features and add mapping from new bfd_mach_arm values to allowed CPU feature bits. opcodes/ * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in expected result. * testsuite/ld-arm/tls-descrelax-v7.d: Likewise. * testsuite/ld-arm/tls-longplt-lib.d: Likewise. * testsuite/ld-arm/tls-longplt.d: Likewise.	8 years ago
Tamar Christina	369c9167d4	Fix AArch64 encodings for by element instructions. Some instructions in Armv8-a place a limitation on FP16 registers that can be used as the register from which to select an element from. e.g. fmla restricts Rm to 4 bits when using an FP16 register. This restriction does not apply for all instructions, e.g. fcmla does not have this restriction as it gets an extra bit from the M field. Unfortunately, this restriction to S_H was added for all _Em operands before, meaning for a large number of instructions you couldn't use the full register file. This fixes the issue by introducing a new operand _Em16 which applies this restriction only when paired with S_H and leaves the _Em and the other qualifiers for _Em16 unbounded (i.e. using the full 5 bit range). Also the patch updates all instructions that should be affected by this. opcodes/ PR binutils/23192 * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Likewise. * aarch64-opc-2.c: Likewise. * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint. * aarch64-opc.c (operand_general_constraint_met_p, aarch64_print_operand): Likewise. * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal, smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl, fmlal2, fmlsl2. (AARCH64_OPERANDS): Add Em2. gas/ PR binutils/23192 * config/tc-aarch64.c (process_omitted_operand, parse_operands): Add AARCH64_OPND_Em16 * testsuite/gas/aarch64/advsimd-armv8_3.s: Expand tests to cover upper 16 registers. * testsuite/gas/aarch64/advsimd-armv8_3.d: Likewise. * testsuite/gas/aarch64/advsimd-compnum.s: Likewise. * testsuite/gas/aarch64/advsimd-compnum.d: Likewise. * testsuite/gas/aarch64/sve.d: Likewise. include/ PR binutils/23192 *opcode/aarch64.h (aarch64_opnd): Add AARCH64_OPND_Em16.	8 years ago
Nick Clifton	30aa13067f	Updated translations. gas * po/uk.po: Updated Ukranian translation. bfd * po/uk.po: Updated Ukranian translation. ld * po/uk.po: Updated Ukranian translation. gold * po/uk.po: Updated Ukranian translation. opcodes * po/uk.po: Updated Ukranian translation. * po/de.po: Updated German translation. * po/pt_BR.po: Updated Brazilian Portuguese translation. binutils* po/sv.po: Updated Swedish translation. * po/uk.po: Updated Ukranian translation.	8 years ago
Nick Clifton	eca4b72146	Fix spelling mistakes. opcodes * nfp-dis.c: Fix spelling mistake. ld * emultempl/aarch64elf.em: Fix spelling mistake. * emultempl/avrelf.em: Likewise. * emultempl/elf32.em: Likewise. binutils* doc/binutils.texi: Fix spelling mistakes. * README--how-to-make-a-release: Likewise.	8 years ago
Nick Clifton	71300e2c0c	Regenerate configure and pot files with updated binutils version number.	8 years ago
Nick Clifton	719d828850	Add 2.30 branch notes to ChangeLogs and NEWS files.	8 years ago
Tamar Christina	514cd3a0f5	Correct negs aliasing on AArch64. This patch fixes a disassembly issue with the aliases to subs with a shifted register. The subs instruction with the zero register as destination is supposed to alias to cmp and when the first input register is the zero register the subs is supposed to be aliased to negs. This means that a subs with destination and first input registers the zero register is supposed to be a cmp. This is done by raising the priority of the cmp alias. opcodes/ * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Likewise. gas/ * testsuite/gas/aarch64/addsub.s: Add negs to zero reg test. * testsuite/gas/aarch64/addsub.d: Likewise.	8 years ago
Maciej W. Rozycki	385e4d0f27	MIPS/opcodes: Fix a typo in `-M ginv' option description opcodes/ * mips-dis.c (print_mips_disassembler_options): Fix a typo in `-M ginv' option description.	8 years ago
Sebastian Huber	160d1b3d74	RISC-V: Accept constant operands in la and lla opcodes/ PR gas/23305 * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for la and lla. gas/ PR gas/23305 * config/tc-riscv.c (riscv_ip): Add format specifier 'B' for constants and symbols. * testsuite/gas/riscv/lla32.d: New file. * testsuite/gas/riscv/lla32.s: Likewise. * testsuite/gas/riscv/lla64-fail.d: Likewise. * testsuite/gas/riscv/lla64-fail.l: Likewise. * testsuite/gas/riscv/lla64-fail.s: Likewise. * testsuite/gas/riscv/lla64.d: Likewise. * testsuite/gas/riscv/lla64.s: Likewise.	8 years ago
Simon Marchi	d0ac1c4488	Bump to autoconf 2.69 and automake 1.15.1 When trying to run the update-gnulib.sh script in gdb, I get this: Error: Wrong automake version (Unescaped left brace in regex is deprecated, passed through in regex; marked by <-- HERE in m/\${ <-- HERE ([^ =:+{}]+)}/ at /opt/automake/1.11.1/bin/automake line 4113.), we need 1.11.1. Aborting. Apparently, it's an issue with a regex in automake that triggers a warning starting with Perl 5.22. It has been fixed in automake 1.15.1. So I think it's a good excuse to bump the versions of autoconf and automake used in the gnulib import. And to avoid requiring multiple builds of autoconf/automake, it was suggested that we bump the required version of those tools for all binutils-gdb. For autoconf, the 2.69 version is universally available, so it's an easy choice. For automake, different distros and distro versions have different automake versions. But 1.15.1 seems to be the most readily available as a package. In any case, it's easy to build it from source. I removed the version checks from AUTOMAKE_OPTIONS and AC_PREREQ, because I don't think they are useful in our case. They only specify a lower bound for the acceptable version of automake/autoconf. That's useful if you let the user choose the version of the tool they want to use, but want to set a minimum version (because you use a feature that was introduced in that version). In our case, we force people to use a specific version anyway. For the autoconf version, we have the check in config/override.m4 that enforces the version we want. It will be one less thing to update next time we change autotools version. I hit a few categories of problems that required some changes. They are described below along with the chosen solutions. Problem 1: configure.ac:17: warning: AM_INIT_AUTOMAKE: two- and three-arguments forms are deprecated. For more info, see: configure.ac:17: http://www.gnu.org/software/automake/manual/automake.html#Modernize-AM_005fINIT_005fAUTOMAKE-invocation Solution 1: Adjust the code based on the example at that URL. Problem 2 (in zlib/): Makefile.am: error: required file './INSTALL' not found Makefile.am: 'automake --add-missing' can install 'INSTALL' Makefile.am: error: required file './NEWS' not found Makefile.am: error: required file './AUTHORS' not found Makefile.am: error: required file './COPYING' not found Makefile.am: 'automake --add-missing' can install 'COPYING' Solution 2: Add the foreign option to AUTOMAKE_OPTIONS. Problem 3: doc/Makefile.am:20: error: support for Cygnus-style trees has been removed Solution 3: Remove the cygnus options. Problem 4: Makefile.am:656: warning: 'INCLUDES' is the old name for 'AM_CPPFLAGS' (or '_CPPFLAGS') Solution 4: Rename "INCLUDES = " to "AM_CPPFLAGS += " (because AM_CPPFLAGS is already defined earlier). Problem 5: doc/Makefile.am:71: warning: suffix '.texinfo' for Texinfo files is discouraged; use '.texi' instead doc/Makefile.am: warning: Oops! doc/Makefile.am: It appears this file (or files included by it) are triggering doc/Makefile.am: an undocumented, soon-to-be-removed automake hack. doc/Makefile.am: Future automake versions will no longer place in the builddir doc/Makefile.am: (rather than in the srcdir) the generated '.info' files that doc/Makefile.am: appear to be cleaned, by e.g. being listed in CLEANFILES or doc/Makefile.am: DISTCLEANFILES. doc/Makefile.am: If you want your '.info' files to be placed in the builddir doc/Makefile.am: rather than in the srcdir, you have to use the shiny new doc/Makefile.am: 'info-in-builddir' automake option. Solution 5: Rename .texinfo files to .texi. Problem 6: doc/Makefile.am: warning: Oops! doc/Makefile.am: It appears this file (or files included by it) are triggering doc/Makefile.am: an undocumented, soon-to-be-removed automake hack. doc/Makefile.am: Future automake versions will no longer place in the builddir doc/Makefile.am: (rather than in the srcdir) the generated '.info' files that doc/Makefile.am: appear to be cleaned, by e.g. being listed in CLEANFILES or doc/Makefile.am: DISTCLEANFILES. doc/Makefile.am: If you want your '.info' files to be placed in the builddir doc/Makefile.am: rather than in the srcdir, you have to use the shiny new doc/Makefile.am: 'info-in-builddir' automake option. Solution 6: Remove the hack at the bottom of doc/Makefile.am and use the info-in-builddir automake option. Problem 7: doc/Makefile.am:35: error: required file '../texinfo.tex' not found doc/Makefile.am:35: 'automake --add-missing' can install 'texinfo.tex' Solution 7: Use the no-texinfo.tex automake option. We also have one in texinfo/texinfo.tex, not sure if we should point to that, or move it (or a newer version of it added with automake --add-missing) to top-level. Problem 8: Makefile.am:131: warning: source file 'config/tc-aarch64.c' is in a subdirectory, Makefile.am:131: but option 'subdir-objects' is disabled automake: warning: possible forward-incompatibility. automake: At least a source file is in a subdirectory, but the 'subdir-objects' automake: automake option hasn't been enabled. For now, the corresponding output automake: object file(s) will be placed in the top-level directory. However, automake: this behaviour will change in future Automake versions: they will automake: unconditionally cause object files to be placed in the same subdirectory automake: of the corresponding sources. automake: You are advised to start using 'subdir-objects' option throughout your automake: project, to avoid future incompatibilities. Solution 8: Use subdir-objects, that means adjusting references to some .o that will now be in config/. Problem 9: configure.ac:375: warning: AC_LANG_CONFTEST: no AC_LANG_SOURCE call detected in body ../../lib/autoconf/lang.m4:193: AC_LANG_CONFTEST is expanded from... ../../lib/autoconf/general.m4:2601: _AC_COMPILE_IFELSE is expanded from... ../../lib/autoconf/general.m4:2617: AC_COMPILE_IFELSE is expanded from... ../../lib/m4sugar/m4sh.m4:639: AS_IF is expanded from... ../../lib/autoconf/general.m4:2042: AC_CACHE_VAL is expanded from... ../../lib/autoconf/general.m4:2063: AC_CACHE_CHECK is expanded from... configure.ac:375: the top level Solution 9: Use AC_LANG_SOURCE, or use proper quoting. Problem 10 (in intl/): configure.ac:7: warning: AC_COMPILE_IFELSE was called before AC_USE_SYSTEM_EXTENSIONS /usr/share/aclocal/threadlib.m4:36: gl_THREADLIB_EARLY_BODY is expanded from... /usr/share/aclocal/threadlib.m4:29: gl_THREADLIB_EARLY is expanded from... /usr/share/aclocal/threadlib.m4:318: gl_THREADLIB is expanded from... /usr/share/aclocal/lock.m4:9: gl_LOCK is expanded from... /usr/share/aclocal/intl.m4:211: gt_INTL_SUBDIR_CORE is expanded from... /usr/share/aclocal/intl.m4:25: AM_INTL_SUBDIR is expanded from... /usr/share/aclocal/gettext.m4:57: AM_GNU_GETTEXT is expanded from... configure.ac:7: the top level Solution 10: Add AC_USE_SYSTEM_EXTENSIONS in configure.ac. ChangeLog: libtool.m4: Use AC_LANG_SOURCE. * configure.ac: Remove AC_PREREQ, use AC_LANG_SOURCE. * README-maintainer-mode: Update version requirements. * ar-lib: New file. * test-driver: New file. * configure: Re-generate. bfd/ChangeLog: * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11. (INCLUDES): Rename to ... (AM_CPPFLAGS): ... this. * configure.ac: Remove AC_PREREQ. * doc/Makefile.am (AUTOMAKE_OPTIONS): Remove 1.9, cygnus, add info-in-builddir no-texinfo.tex. (info_TEXINFOS): Rename bfd.texinfo to bfd.texi. * doc/bfd.texinfo: Rename to ... * doc/bfd.texi: ... this. * Makefile.in: Re-generate. * aclocal.m4: Re-generate. * config.in: Re-generate. * configure: Re-generate. * doc/Makefile.in: Re-generate. binutils/ChangeLog: * configure.ac: Remove AC_PREREQ. * doc/Makefile.am (AUTOMAKE_OPTIONS): Remove cygnus, add info-in-builddir no-texinfo.tex. * Makefile.in: Re-generate. * aclocal.m4: Re-generate. * config.in: Re-generate. * configure: Re-generate. * doc/Makefile.in: Re-generate. config/ChangeLog: * override.m4 (_GCC_AUTOCONF_VERSION): Bump from 2.64 to 2.69. etc/ChangeLog: * configure.in: Remove AC_PREREQ. * configure: Re-generate. gas/ChangeLog: * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11, add subdir-objects. (TARG_CPU_O, OBJ_FORMAT_O, ATOF_TARG_O): Add config/ prefix. * configure.ac (TARG_CPU_O, OBJ_FORMAT_O, ATOF_TARG_O, emfiles, extra_objects): Add config/ prefix. * doc/as.texinfo: Rename to... * doc/as.texi: ... this. * doc/Makefile.am: Rename as.texinfo to as.texi throughout. Remove DISTCLEANFILES hack. (AUTOMAKE_OPTIONS): Remove 1.8, cygnus, add no-texinfo.tex and info-in-builddir. * Makefile.in: Re-generate. * aclocal.m4: Re-generate. * config.in: Re-generate. * configure: Re-generate. * doc/Makefile.in: Re-generate. gdb/ChangeLog: * common/common-defs.h (PACKAGE_NAME, PACKAGE_VERSION, PACKAGE_STRING, PACKAGE_TARNAME): Undefine. * configure.ac: Remove AC_PREREQ, add missing quoting. * gnulib/configure.ac: Modernize usage of AC_INIT/AM_INIT_AUTOMAKE. Remove AC_PREREQ. * gnulib/update-gnulib.sh (AUTOCONF_VERSION): Bump to 2.69. (AUTOMAKE_VERSION): Bump to 1.15.1. * configure: Re-generate. * config.in: Re-generate. * aclocal.m4: Re-generate. * gnulib/aclocal.m4: Re-generate. * gnulib/config.in: Re-generate. * gnulib/configure: Re-generate. * gnulib/import/Makefile.in: Re-generate. gdb/gdbserver/ChangeLog: * configure.ac: Remove AC_PREREQ, add missing quoting. * configure: Re-generate. * config.in: Re-generate. * aclocal.m4: Re-generate. gdb/testsuite/ChangeLog: * configure.ac: Remove AC_PREREQ. * configure: Re-generate. gold/ChangeLog: * configure.ac: Remove AC_PREREQ, add missing quoting and usage of AC_LANG_SOURCE. * Makefile.in: Re-generate. * aclocal.m4: Re-generate. * configure: Re-generate. * testsuite/Makefile.in: Re-generate. gprof/ChangeLog: * configure.ac: Remove AC_PREREQ. * Makefile.am: Remove DISTCLEANFILES hack. (AUTOMAKE_OPTIONS): Remove 1.11, add info-in-builddir. * Makefile.in: Re-generate. * aclocal.m4: Re-generate. * configure: Re-generate. * gconfig.in: Re-generate. intl/ChangeLog: * configure.ac: Add AC_USE_SYSTEM_EXTENSIONS, remove AC_PREREQ. * configure: Re-generate. * config.h.in: Re-generate. * aclocal.m4: Re-generate. ld/ChangeLog: * configure.ac: Remove AC_PREREQ. * Makefile.am: Remove DISTCLEANFILES hack, rename ld.texinfo to ld.texi, ldint.texinfo to ldint.texi throughout. (AUTOMAKE_OPTIONS): Add info-in-builddir. * README: Rename ld.texinfo to ld.texi, ldint.texinfo to ldint.texi throughout. * gen-doc.texi: Likewise. * h8-doc.texi: Likewise. * ld.texinfo: Rename to ... * ld.texi: ... this. * ldint.texinfo: Rename to ... * ldint.texi: ... this. * Makefile.in: Re-generate. * aclocal.m4: Re-generate. * config.in: Re-generate. * configure: Re-generate. libdecnumber/ChangeLog: * configure.ac: Remove AC_PREREQ. * configure: Re-generate. * aclocal.m4. libiberty/ChangeLog: * configure.ac: Remove AC_PREREQ. * configure: Re-generate. * config.in: Re-generate. opcodes/ChangeLog: * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11. * configure.ac: Remove AC_PREREQ. * Makefile.in: Re-generate. * aclocal.m4: Re-generate. * configure: Re-generate. readline/ChangeLog.gdb: * configure: Re-generate. * examples/rlfe/configure: Re-generate. sim/ChangeLog: * All configure.ac: Remove AC_PREREQ. * All configure: Re-generate. zlib/ChangeLog.bin-gdb: * configure.ac: Modernize AC_INIT call, remove AC_PREREQ. * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.8, cygnus, add foreign. * Makefile.in: Re-generate. * aclocal.m4: Re-generate. * configure: Re-generate.	8 years ago
Faraz Shahbazker	6f20c942c3	MIPS: Add Global INValidate ASE support Add support for the Global INValidate Application Specific Extension for Release 6 of the MIPS Architecture. [1] "MIPS Architecture for Programmers Volume II-A: The MIPS32 Instruction Set Manual", Imagination Technologies Ltd., Document Number: MD00086, Revision 6.06, December 15, 2016, Section 3.2 "Alphabetical List of Instructions", pp. 187-191 bfd/ * elfxx-mips.c (print_mips_ases): Add GINV extension. binutils/ * readelf.c (print_mips_ases): Add GINV extension. gas/ * NEWS: Mention MIPS Global INValidate ASE support. * config/tc-mips.c (options): Add OPTION_GINV and OPTION_NO_GINV. (md_longopts): Likewise. (mips_ases): Define availability for GINV. (mips_convert_ase_flags): Map ASE_GINV to AFL_ASE_GINV. (md_show_usage): Add help for -mginv and -mno-ginv. * doc/as.texinfo: Document -mginv, -mno-ginv. * doc/c-mips.texi: Document -mginv, -mno-ginv, .set ginv and .set noginv. * testsuite/gas/mips/ase-errors-1.s: Add error checks for GINV ASE. * testsuite/gas/mips/ase-errors-2.s: Likewise. * testsuite/gas/mips/ase-errors-1.l: Likewise. * testsuite/gas/mips/ase-errors-2.l: Likewise. * testsuite/gas/mips/ginv.d: New test. * testsuite/gas/mips/ginv-err.d: New test. * testsuite/gas/mips/ginv-err.l: New test stderr output. * testsuite/gas/mips/ginv.s: New test source. * testsuite/gas/mips/ginv-err.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests. include/ * elf/mips.h (AFL_ASE_GINV, AFL_ASE_RESERVED1): New macros. (AFL_ASE_MASK): Update to include AFL_ASE_GINV. * opcode/mips.h: Document "+\" operand format. (ASE_GINV): New macro. opcodes/ * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and mips64r6 descriptors. (parse_mips_ase_option): Handle -Mginv option. (print_mips_disassembler_options): Document -Mginv. * mips-opc.c (decode_mips_operand) <+\>: New operand format. (GINV): New macro. (mips_opcodes): Define ginvi and ginvt.	8 years ago
Scott Egerton	730c31740a	MIPS: Add CRC ASE support Add support for the CRC Application Specific Extension for Release 6 of the MIPS Architecture. [1] "MIPS Architecture for Programmers Volume II-A: The MIPS32 Instruction Set Manual", Imagination Technologies Ltd., Document Number: MD00086, Revision 6.06, December 15, 2016, Section 3.2 "Alphabetical List of Instructions", pp. 143-148 [2] "MIPS Architecture for Programmers Volume II-A: The MIPS64 Instruction Set Manual", Imagination Technologies Ltd., Document Number: MD00087, Revision 6.06, December 15, 2016, Section 3.2 "Alphabetical List of Instructions", pp. 165-170 ChangeLog: bfd/ 2018-06-13 Scott Egerton <scott.egerton@imgtec.com> Faraz Shahbazker <Faraz.Shahbazker@mips.com> * elfxx-mips.c (print_mips_ases): Add CRC. binutils/ 2018-06-13 Scott Egerton <scott.egerton@imgtec.com> Faraz Shahbazker <Faraz.Shahbazker@mips.com> * readelf.c (print_mips_ases): Add CRC. gas/ 2018-06-13 Scott Egerton <scott.egerton@imgtec.com> Faraz Shahbazker <Faraz.Shahbazker@mips.com> Maciej W. Rozycki <macro@mips.com> * config/tc-mips.c (options): Add OPTION_CRC and OPTION_NO_CRC. (md_longopts): Likewise. (md_show_usage): Add help for -mcrc and -mno-crc. (mips_ases): Define availability for CRC and CRC64. (mips_convert_ase_flags): Map ASE_CRC to AFL_ASE_CRC. * doc/as.texinfo: Document -mcrc, -mno-crc. * doc/c-mips.texi: Document -mcrc, -mno-crc, .set crc and .set no-crc. * testsuite/gas/mips/ase-errors-1.l: Add error checks for CRC ASE. * testsuite/gas/mips/ase-errors-2.l: Likewise. * testsuite/gas/mips/ase-errors-1.s: Likewise. * testsuite/gas/mips/ase-errors-2.s: Likewise. * testsuite/gas/mips/crc.d: New test. * testsuite/gas/mips/crc64.d: New test. * testsuite/gas/mips/crc-err.d: New test. * testsuite/gas/mips/crc64-err.d: New test. * testsuite/gas/mips/crc-err.l: New test stderr output. * testsuite/gas/mips/crc64-err.l: New test stderr output. * testsuite/gas/mips/crc.s: New test source. * testsuite/gas/mips/crc64.s: New test source. * testsuite/gas/mips/crc-err.s: New test source. * testsuite/gas/mips/crc64-err.s: New test source. * testsuite/gas/mips/mips.exp: Run the new tests. include/ 2018-06-13 Scott Egerton <scott.egerton@imgtec.com> Faraz Shahbazker <Faraz.Shahbazker@mips.com> * elf/mips.h (AFL_ASE_CRC): New macro. (AFL_ASE_MASK): Update to include AFL_ASE_CRC. * opcode/mips.h (ASE_CRC): New macro. * opcode/mips.h (ASE_CRC64): Likewise. opcodes/ 2018-06-13 Scott Egerton <scott.egerton@imgtec.com> Faraz Shahbazker <Faraz.Shahbazker@mips.com> * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs. * mips-opc.c (CRC, CRC64): New macros. (mips_builtin_opcodes): Define crc32b, crc32h, crc32w, crc32cb, crc32ch and crc32cw for CRC. Define crc32d and crc32cd for CRC64.	8 years ago
Egeyar Bagcioglu	cb36699271	Prevent undefined FMOV instructions being accepted by the AArch64 assembler. Detect illegal FMOV instructions that changes the size from 32 bits to 64 bits and vice versa. Add tests for these and other undefined FMOV instructions. PR 20319 gas * testsuite/gas/aarch64/illegal-3.s: Test if unallocated FMOV encodings are detected as undefined. * testsuite/gas/aarch64/illegal-3.d: Likewise. * testsuite/gas/aarch64/illegal.s: Test if FMOV instructions that are changing the size from 32 bits to 64 bits and vice versa trigger an error. * testsuite/gas/aarch64/illegal.l: Likewise. opcodes * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV. (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.	8 years ago
Alan Modra	ce72cd46ec	Fix xtensa "clobbered by longjmp" warnings .../opcodes/xtensa-dis.c: In function ‘print_insn_xtensa’: .../opcodes/xtensa-dis.c:257:17: error: variable ‘fmt’ might be clobbered by ‘longjmp’ or ‘vfork’ [-Werror=clobbered] xtensa_format fmt; ^~~ .../opcodes/xtensa-dis.c:262:26: error: variable ‘valid_insn’ might be clobbered by ‘longjmp’ or ‘vfork’ [-Werror=clobbered] int first, first_slot, valid_insn = 0; ^~~~~~~~~~ * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after setjmp. Move init for some other vars later too.	8 years ago
Max Filippov	4b8e28c793	xtensa: use property tables for correct disassembly xtensa disassembler does not use information from the .xt.prop sections to switch between code/data disassembly in text sections. This may result in incorrect disassembly when data is interpreted as code and disassembler loses synchronization with instruction stream. Use .xt.prop section information to correctly interpret code and data and synchronize with instruction stream. 2018-06-04 Max Filippov <jcmvbkbc@gmail.com> bfd/ * elf32-xtensa.c (xtensa_read_table_entries): Make global. (compute_fill_extra_space): Drop declaration. Rename function to xtensa_compute_fill_extra_space. (compute_ebb_actions, remove_dead_literal): Update references to compute_fill_extra_space. include/ * elf/xtensa.h (xtensa_read_table_entries) (xtensa_compute_fill_extra_space): New declarations. opcodes/ * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes. (dis_private): Add new fields for property section tracking. (xtensa_coalesce_insn_tables, xtensa_find_table_entry) (xtensa_instruction_fits): New functions. (fetch_data): Bump minimal fetch size to 4. (print_insn_xtensa): Make struct dis_private static. Load and prepare property table on section change. Don't disassemble literals. Don't disassemble instructions that cross property table boundaries.	8 years ago

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2897 Commits (11cfdeb3863c5ddf8e773147e6cf5a14de15aee8)