binutils-gdb

Commit Graph

Author	SHA1	Message	Date
Matthew Gretton-Dann	6844b2c2db	2010-09-27 Tejas Belagod <tejas.belagod@arm.com> * gas/config/tc-arm.c (do_neon_ldr_str): Deprecate ARM-mode PC-relative VSTR, issue an error in THUMB mode. * opcodes/arm_dis.c (print_insn_coprocessor): Apply off-by-alignment correction to unaligned PCs while printing comment. * gas/testsuite/gas/arm/vldr.s: New test for pc-relative VLDR disassembly comment. * gas/testsuite/gas/arm/vldr.d: Likewise. * gas/testsuite/gas/arm/vstr-bad.s: New test for PC-relative VSTR. * gas/testsuite/gas/arm/vstr-thumb-bad.l: Likewise. * gas/testsuite/gas/arm/vstr-thumb-bad.d: Likewise. * gas/testsuite/gas/arm/vstr-arm-bad.l: Likewise. * gas/testsuite/gas/arm/vstr-arm-bad.d: Likewise.	16 years ago
Matthew Gretton-Dann	90ec0d684e	* bfd/bfd-in2.h (BFD_RELOC_ARM_HVC): New enum value. * gas/config/tc-arm.c (arm_ext_virt): New variable. (arm_reg_type): Add REG_TYPE_RNB for banked registers. (reg_entry): Allow registers to be larger than a byte. (reg_alias): Fix type warning. (parse_operands): Parse banked registers when appropriate. (do_mrs): Add support for Virtualization Extensions. (do_hvc): New function. (do_t_mrs): Add support for Virtualization Extensions. (do_t_msr): Likewise. (do_t_hvc): New function. (SPLRBANK): New define. (reg_names): Add banked registers. (insns): Add support for Virtualization Extensions. (md_apply_fixup): Likewise. (arm_cpus): -mcpu=cortex-a15 implies the Virtualization Extensions. (arm_extensions): Add 'virt' extension. (aeabi_set_public_attributes): Add support for Virtualization Extensions. * gas/doc/c-arm.texi: Document 'virt' extension. * gas/testsuite/gas/arm/armv7-a+virt.d: New test. * gas/testsuite/gas/arm/armv7-a+virt.s: Likewise. * gas/testsuite/gas/arm/attr-march-all.d: Update for Virtualization Extensions. * gas/testsuite/gas/arm/attr-march-armv7-a+sec+virt.d: New test. * gas/testsuite/gas/arm/attr-march-armv7-a+virt.d: Likewise. * include/opcode/arm.h (ARM_EXT_VIRT): New define. (ARM_ARCH_V7A_IDIV_MP_SEC): Rename... (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization Extensions. * opcodes/arm-dis.c (arm_opcodes): Add Virtualiztion Extensions support. (thumb32_opcodes): Likewise. (banked_regname): New function. (print_insn_arm): Add Virtualization Extensions support. (print_insn_thumb32): Likewise.	16 years ago
Matthew Gretton-Dann	eea54501f7	* gas/config/tc-arm.c (arm_ext_adiv): New variable. (do_div): New function. (insns): Accept UDIV and SDIV in ARM state. (arm_cpus): The cortex-a15 option has all current v7-A extensions. (arm_extensions): Add 'idiv' extension. (aeabi_set_public_attributes): Update Tag_DIV_use values for the Integer Divide extension. * gas/doc/c-arm.texi: Document the idiv extension. * gas/testsuite/gas/arm/armv7-a+idiv.d: New test. * gas/testsuite/gas/arm/armv7-a+idiv.s: Likewise. * gas/testsuite/gas/arm/attr-march-all.d: Update for Integer divide extension. * gas/testsuite/gas/arm/attr-march-armv7-a+idiv.d: New test. * include/opcode/arm.h (ARM_AEXT_ADIV): New define. (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise. * opcodes/arm-dis.c (arm_opcodes): Support disassembly of UDIV and SDIV in ARM state.	16 years ago
Matthew Gretton-Dann	f4c65163c7	* gas/config/tc-arm.c (arm_ext_v6z): Remove. (arm_ext_sec): New variable. (do_t_smc): In Thumb state SMC requires v7-A. (insns): Make SMC depend on Security Extensions. (arm_cpus): All -mcpu=cortex-a* options have the Security Extensions. (arm_extensions): Add 'sec' extension. (cpu_arch_ver): Reorder. (aeabi_set_public_attributes): Emit Tag_Virtualization_use as appropriate. * gas/doc/c-arm.texi: Document Security Extensions. * gas/testsuite/gas/arm/attr-march-all.d: Update for Security Extensions.. * gas/testsuite/gas/arm/attr-march-armv6k+sec.d: New test. * gas/testsuite/gas/arm/attr-march-armv6z.d: Update for Security Extensions. * gas/testsuite/gas/arm/attr-march-armv6zk.d: Likewise. * gas/testsuite/gas/arm/attr-march-armv6zkt2.d: Likewise. * gas/testsuite/gas/arm/attr-march-armv6zt2.d: Likewise. * gas/testsuite/gas/arm/attr-march-armv7-a+sec.d: New test. * gas/testsuite/gas/arm/attr-mcpu.d: Update for Security Extensions. * gas/testsuite/gas/arm/thumb32.d: Likewise. * gas/testsuite/gas/arm/thumb32.s: Likewise. * include/opcode/arm.h (ARM_EXT_V6Z): Remove. (ARM_EXT_SEC): New define. (ARM_AEXT_V6Z): Use Security Extensions. (ARM_AEXT_V6ZK): Likeiwse. (ARM_AEXT_V6ZT2): Likewise. (ARM_AEXT_V6ZKT2): Likewise. (ARM_AEXT_V7_ARM): Base v7 does not have Security Extensions. (ARM_ARCH_V7A_SEC): New define. (ARM_ARCH_V7A_MP): Rename... (ARM_ARCH_V7A_MP_SEC): ...to this and add Security Extensions. * ld/testsuite/ld-arm/attr-merge-6.attr: Update for Security Extensions. * ld/testsuite/ld-arm/attr-merge-7.attr: Likewise. * opcodes/arm-dis.c (arm_opcodes): SMC implies Security Extensions. (thumb32_opcodes): Likewise.	16 years ago
Matthew Gretton-Dann	60e5ef9f19	* gas/config/tc-arm.c (arm_ext_mp): Add. (do_pld): Update comment. (insns): Add support for pldw. (arm_cpus): Update cortex-a5, cortex-a9, and cortex-a15 to support MP extension. (arm_extensions): Add 'mp' extension. (aeabi_set_public_attributes): Emit correct build attribute when MP extension is enabled. * gas/doc/c-arm.texi: Update for MP extensions. * gas/testsuite/gas/arm/arch7a-mp.d: Add. * gas/testsuite/gas/arm/arch7ar-mp.s: Likewise. * gas/testsuite/gas/arm/arch7r-mp.d: Likewise. * gas/testsuite/gas/arm/armv2-mp-bad.d: Likewise. * gas/testsuite/gas/arm/armv2-mp-bad.l: Likewise. * gas/testsuite/gas/arm/attr-march-all.d: Update for MP extension. * gas/testsuite/gas/arm/attr-march-armv7-a+mp.d: Add. * gas/testsuite/gas/arm/attr-march-armv7-r+mp.d: Likewise. * include/opcode/arm.h (ARM_EXT_MP): Add. (ARM_ARCH_V7A_MP): Likewise. * opcodes/arm-dis.c (arm_opcodes): Add support for pldw. (thumb32_opcodes): Likewise.	16 years ago
Matthew Gretton-Dann	db472d6ff0	2010-09-17 Tejas Belagod <tejas.belagod@arm.com> * config/tc-arm.c (insns): Change MRC entry to accept APSR_RR instead of just RR. 2010-09-17 Tejas Belagod <tejas.belagod@arm.com> * gas/arm/copro.s: Add test for APSR_nzcv as a MRC operand. * gas/arm/copro.d: Change pc in MRC to disassemble as APSR_nzcv. Also add disassembly for test added in copro.s 2010-09-17 Tejas Belagod <tejas.belagod@arm.com> * arm_dis.c (coprocessor_opcodes): Add MRC entry for APSR_nzcv.	16 years ago
Richard Earnshaw	52e7f43db0	2010-07-08 Tejas Belagod <tejas.belagod@arm.com> gas/testsuite * gas/arm/barrier.s: New file. * gas/arm/barrier.d: New file. * gas/arm/barrier-thumb.s: New file. * gas/arm/barrier-thumb.d: New file. * gas/arm/barrier-bad.s: New file. * gas/arm/barrier-bad.d: New file. * gas/arm/barrier-bad.l: New file. * gas/arm/barrier-bad-thumb.s: New file. * gas/arm/barrier-bad-thumb.d: New file. * gas/arm/barrier-bad-thumb.l: New file. gas/config * tc-arm.c (OP_oBARRIER): Remove. (OP_oBARRIER_I15): Add. (po_barrier_or_imm): Add macro. (parse_operands): Improve OP_oBARRIER_I15 operand parsing. (do_barrier): Check correct immediate range. (do_t_barrier): Likewise. (barrier_opt_names): Add entries for more symbolic operands. (insns): Replace OP_oBARRIER with OP_oBARRIER_I15 for barriers. opcodes/ * arm-dis.c (print_insn_arm): Add cases for printing more symbolic operands. (print_insn_thumb32): Likewise.	16 years ago
Matthew Gretton-Dann	8e56076649	* gas/config/tc-arm.c (parse_neon_alignment): New function. (parse_address_main): Fix Neon load/store alignment parsing. * gas/testsuite/gas/arm/neon-ldst-align-bad.l: Update for Neon alignment syntax fix. * gas/testsuite/gas/arm/neon-ldst-align-bad.s: Likewise. * gas/testsuite/gas/arm/neon-ldst-es.d: Likewise. * gas/testsuite/gas/arm/neon-ldst-es.s: Likewise. * opcodes/arm-disc.c (parse_insn_neon): Fix Neon alignment syntax.	16 years ago
Matthew Gretton-Dann	1f4e495053	* gas/testsuite/gas/arm/thumb-eabi.d: Add case for divided syntax encoding of movs. * gas/testsuite/gas/arm/thumb.d: Likewise. * gas/testsuite/gas/arm/thumb.s: Likewise. * gas/testsuite/gas/arm/thumb2_it.d: Update for change in lsls/movs disassembly. * gas/testsuite/gas/arm/thumb2_it_auto.d: Liekwise. * gas/testsuite/gas/arm/thumb32.d: Likewise. * ld/testsuite/ld-arm/arm-call.d: Handle change in lsls/movs disassembly. * ld/testsuite/ld-arm/farcall-thumb-arm-short.d: Likewise. * ld/testsuite/ld-arm/farcall-thumb-thumb-blx-pic-veneer.d: Likewise. * ld/testsuite/ld-arm/farcall-thumb-thumb-blx.d: Likewise. * ld/testsuite/ld-arm/farcall-thumb-thumb-m-pic-veneer.d: Likewise. * ld/testsuite/ld-arm/farcall-thumb-thumb-m.d: Likewise. * ld/testsuite/ld-arm/farcall-thumb-thumb-pic-veneer.d: Likewise. * ld/testsuite/ld-arm/farcall-thumb-thumb.d: Likewise. * ld/testsuite/ld-arm/thumb2-bl-as-thumb1-bad-noeabi.d: Likewise. * ld/testsuite/ld-arm/thumb2-bl-as-thumb1-bad.d: Likewise. * ld/testsuite/ld-arm/thumb2-bl-bad-noeabi.d: Likewise. * ld/testsuite/ld-arm/thumb2-bl-bad.d: Likewise. * opcodes/arm-dis.c (thumb-opcodes): Add disassembly for movs.	16 years ago
Matthew Gretton-Dann	9d82ec3801	* opcodes/arm-dis.c (print_insn_neon): Ensure disassembly of Neon constants is the same on 32-bit and 64-bit hosts.	16 years ago
Nick Clifton	4547cb569c	2010-05-10 Andrew Stubbs <ams@codesourcery.com> gas/ * config/tc-arm.c (aeabi_set_public_attributes): Set Tag_DIV_use. gas/testsuite/ * gas/arm/attr-cpu-directive.d: Add Tag_DIV_use. * gas/arm/attr-default.d: Likewise. * gas/arm/attr-march-armv1.d: Likewise. * gas/arm/attr-march-armv2.d: Likewise. * gas/arm/attr-march-armv2a.d: Likewise. * gas/arm/attr-march-armv2s.d: Likewise. * gas/arm/attr-march-armv3.d: Likewise. * gas/arm/attr-march-armv3m.d: Likewise. * gas/arm/attr-march-armv4.d: Likewise. * gas/arm/attr-march-armv4t.d: Likewise. * gas/arm/attr-march-armv4txm.d: Likewise. * gas/arm/attr-march-armv4xm.d: Likewise. * gas/arm/attr-march-armv5.d: Likewise. * gas/arm/attr-march-armv5t.d: Likewise. * gas/arm/attr-march-armv5te.d: Likewise. * gas/arm/attr-march-armv5tej.d: Likewise. * gas/arm/attr-march-armv5texp.d: Likewise. * gas/arm/attr-march-armv5txm.d: Likewise. * gas/arm/attr-march-armv6-m.d: Likewise. * gas/arm/attr-march-armv6.d: Likewise. * gas/arm/attr-march-armv6j.d: Likewise. * gas/arm/attr-march-armv6k.d: Likewise. * gas/arm/attr-march-armv6kt2.d: Likewise. * gas/arm/attr-march-armv6t2.d: Likewise. * gas/arm/attr-march-armv6z.d: Likewise. * gas/arm/attr-march-armv6zk.d: Likewise. * gas/arm/attr-march-armv6zkt2.d: Likewise. * gas/arm/attr-march-armv6zt2.d: Likewise. * gas/arm/attr-march-armv7-a.d: Likewise. * gas/arm/attr-march-armv7.d: Likewise. * gas/arm/attr-march-armv7a.d: Likewise. * gas/arm/attr-march-iwmmxt.d: Likewise. * gas/arm/attr-march-iwmmxt2.d: Likewise. * gas/arm/attr-march-marvell-f.d: Likewise. * gas/arm/attr-march-xscale.d: Likewise. * gas/arm/attr-mcpu.d: Likewise. * gas/arm/attr-mfpu-arm1020e.d: Likewise. * gas/arm/attr-mfpu-arm1020t.d: Likewise. * gas/arm/attr-mfpu-arm1136jf-s.d: Likewise. * gas/arm/attr-mfpu-arm1136jfs.d: Likewise. * gas/arm/attr-mfpu-arm7500fe.d: Likewise. * gas/arm/attr-mfpu-fpa.d: Likewise. * gas/arm/attr-mfpu-fpa10.d: Likewise. * gas/arm/attr-mfpu-fpa11.d: Likewise. * gas/arm/attr-mfpu-fpe.d: Likewise. * gas/arm/attr-mfpu-fpe2.d: Likewise. * gas/arm/attr-mfpu-fpe3.d: Likewise. * gas/arm/attr-mfpu-maverick.d: Likewise. * gas/arm/attr-mfpu-neon-fp16.d: Likewise. * gas/arm/attr-mfpu-neon.d: Likewise. * gas/arm/attr-mfpu-softfpa.d: Likewise. * gas/arm/attr-mfpu-softvfp+vfp.d: Likewise. * gas/arm/attr-mfpu-softvfp.d: Likewise. * gas/arm/attr-mfpu-vfp.d: Likewise. * gas/arm/attr-mfpu-vfp10-r0.d: Likewise. * gas/arm/attr-mfpu-vfp10.d: Likewise. * gas/arm/attr-mfpu-vfp3.d: Likewise. * gas/arm/attr-mfpu-vfp9.d: Likewise. * gas/arm/attr-mfpu-vfpv2.d: Likewise. * gas/arm/attr-mfpu-vfpv3-d16.d: Likewise. * gas/arm/attr-mfpu-vfpv3.d: Likewise. * gas/arm/attr-mfpu-vfpv4-d16.d: Likewise. * gas/arm/attr-mfpu-vfpv4.d: Likewise. * gas/arm/attr-mfpu-vfpxd.d: Likewise. * gas/arm/attr-order.d: Likewise. * gas/arm/attr-override-cpu-directive.d: Likewise. * gas/arm/attr-override-mcpu.d: Likewise. * gas/arm/eabi_attr_1.d: Likewise. ld/testsuite/ * ld-arm/attr-merge-2.attr: Add Tag_DIV_use. * ld-arm/attr-merge-2a.s: Likewise. * ld-arm/attr-merge-2b.s: Likewise. * ld-arm/attr-merge-3a.s: Likewise. * ld-arm/attr-merge-3b.s: Likewise. * ld-arm/attr-merge-4.attr: Likewise. * ld-arm/attr-merge-5.attr: Likewise. * ld-arm/attr-merge-6.attr: Likewise. * ld-arm/attr-merge-7.attr: Likewise. * ld-arm/attr-merge-arch-1.attr: Likewise. * ld-arm/attr-merge-arch-2.attr: Likewise. * ld-arm/attr-merge-unknown-2.d: Likewise. * ld-arm/attr-merge-unknown-2r.d: Likewise. * ld-arm/attr-merge-unknown-3.d: Likewise. * ld-arm/attr-merge-vfp-1.d: Likewise. * ld-arm/attr-merge-vfp-1r.d: Likewise. * ld-arm/attr-merge-vfp-2.d: Likewise. * ld-arm/attr-merge-vfp-2r.d: Likewise. * ld-arm/attr-merge-vfp-3.d: Likewise. * ld-arm/attr-merge-vfp-3r.d: Likewise. * ld-arm/attr-merge-vfp-4.d: Likewise. * ld-arm/attr-merge-vfp-4r.d: Likewise. * ld-arm/attr-merge-vfp-5.d: Likewise. * ld-arm/attr-merge-vfp-5r.d: Likewise. * ld-arm/attr-merge-wchar-00-nowarn.d: Likewise. * ld-arm/attr-merge-wchar-00.d: Likewise. * ld-arm/attr-merge-wchar-02-nowarn.d: Likewise. * ld-arm/attr-merge-wchar-02.d: Likewise. * ld-arm/attr-merge-wchar-04-nowarn.d: Likewise. * ld-arm/attr-merge-wchar-04.d: Likewise. * ld-arm/attr-merge-wchar-20-nowarn.d: Likewise. * ld-arm/attr-merge-wchar-20.d: Likewise. * ld-arm/attr-merge-wchar-22-nowarn.d: Likewise. * ld-arm/attr-merge-wchar-22.d: Likewise. * ld-arm/attr-merge-wchar-24-nowarn.d: Likewise. * ld-arm/attr-merge-wchar-40-nowarn.d: Likewise. * ld-arm/attr-merge-wchar-40.d: Likewise. * ld-arm/attr-merge-wchar-42-nowarn.d: Likewise. * ld-arm/attr-merge-wchar-44-nowarn.d: Likewise. * ld-arm/attr-merge-wchar-44.d: Likewise. * ld-arm/attr-merge.attr: Likewise. 2010-04-07 Jie Zhang <jie@codesourcery.com> gas/ * config/tc-arm.c (aeabi_set_public_attributes): Set Tag_ABI_HardFP_use to 1 if a single precision FPU is selected. gas/testsuite/ * gas/arm/attr-mfpu-vfpxd.d: New test. bfd/ * elf32-arm.c (elf32_arm_merge_eabi_attributes): Merge Tag_ABI_HardFP_use correctly. ld/testsuite/ * ld-arm/attr-merge-vfp-6.d: New test. * ld-arm/attr-merge-vfp-6r.d: New test. * ld-arm/attr-merge-vfpv3xd.s: New test. * ld-arm/arm-elf.exp: Add attr-merge-vfp-6 and attr-merge-vfp-6r. 2010-05-11 Matthew Gretton-Dann <matthew.gretton-dann@arm.com> * arm-dis.c (thumb_opcodes): Update ldmia entry to use new %W format. (print_insn_thumb16): Add support for new %W format. * gas/arm/thumb32.d: Fix expected disassembly of ldmia instruction.	17 years ago
Nick Clifton	c060226ad0	PR binutils/6773 * arm-dis.c (arm_opcodes): Replace <prefix>addsubx with <prefix>asx. Replace <prefix>subaddx with <prefix>sax. (thumb32_opcodes): Likewise. * gas/arm/arch7em.d: Replace expected disassembly of <prefix>addsubx with <prefix>asx. Also replace <prefix>subaddx with <prefix>sax. * gas/arm/archv6.d: Likewise. * gas/arm/thumb32.d: Likewise.	17 years ago
Daniel Jacobowitz	b0e28b39b7	gas/testsuite/ * gas/arm/dis-data.d: Update test name. Do not expect .word output. * gas/arm/dis-data2.d, gas/arm/dis-data2.s, gas/arm/dis-data3.d, gas/arm/dis-data3.s: New tests. opcodes/ * opcodes/arm-dis.c (struct arm_private_data): New. (print_insn_coprocessor, print_insn_arm): Update to use struct arm_private_data. (is_mapping_symbol, get_map_sym_type): New functions. (get_sym_code_type): Check the symbol's section. Do not check mapping symbols. (print_insn): Default to disassembling ARM mode code. Check for mapping symbols separately from other symbols. Use struct arm_private_data.	17 years ago
Nick Clifton	99ea83aac3	PR 11170 * arm-dis.c (print_arm_address): Do not ignore negative bit in PC based post-indexed addressing.	17 years ago
Nick Clifton	e3e535bc58	* arm-dis.c (print_insn): Fixed search for next symbol and data dumping condition, and the initial mapping symbol state. * gas/arm/dis-data.d: New test case. * gas/arm/dis-data.s: New file.	17 years ago
Nick Clifton	2edcd24424	PR 11123 * arm-dis.c (print_insn_coprocessor): Initialise value.	17 years ago
Nick Clifton	ff4a8d2b93	PR binutils/10924 * config/tc-arm.c (do_ldstv4): Do not allow r15 as the destination register. (do_mrs): Likewise. (do_mul): Likewise. * arm-dis.c: Add support for %<>ru and %<>rU formats to enforce unique register numbers. Extend support for %<>R format to thumb32 and coprocessor instructions. * gas/arm/unpredictable.s: Add more unpredictable instructions. * gas/arm/unpredictable.d: Add expected disassemblies.	17 years ago
Nick Clifton	ab8e2090b6	PR binutils/10924 * arm-dis.c (arm_opcodes): Specify %R in cases where using r15 results in unpredictable behaviour. (print_insn_arm): Handle %R. * gas/arm/unpredictable.s: New test case - checks the disassembly of instructions with unpredictable behaviour. * gas/arm/unpredictable.d: New file - expected disassembly.	17 years ago
Nick Clifton	91d6fa6a03	Add -Wshadow to the gcc command line options used when compiling the binutils. Fix up all warnings generated by the addition of this switch.	17 years ago
Nick Clifton	07a28fab11	PR 10924 * arm-dis.c (print_insn_arm): Mark insns that use the PC in post-indexed addressing as unpredictable.	17 years ago
Nick Clifton	03ee1b7f8e	PR gas/11013 * arm-dis.c (thumb32_opc): Adjust disassembly of QADD, QDADD, QSUB and QDSUB. * gas/arm/arch7em.d: Update expected disassembly. * gas/arm/thumb32.d: Likewise. * config/tc-arm.c (do_t_simd2): New function. (insns): Use do_t_simd2 for QADD, QDADD, QSUB and QDSUB.	17 years ago
Nick Clifton	945ee43039	PR binutils/10924 * gas/arm/arch4t-eabi.d: Restore previous expected dissambly of instructions using Immediate Offset addressing with an offset of zero. * gas/arm/arch4t.d: Likewise. * gas/arm/arm7t.d: Likewise. * gas/arm/xscale.d: Likewise. * gas/arm/wince-inst.d: Remove 'p' suffix from cmp, cmn, teq and tst instructions. PR binutils/10924 * arm-dis.c (print_insn_arm): Do not print an offset of zero when decoding Immediaate Offset addressing.	17 years ago
Nick Clifton	aefd8a406c	* gas/arm/vfma1.d: Only run on ELF based targets. PR binutils/10924 * gas/arm/arch4t-eabi.d: Update expected disassembly. * gas/arm/arch4t.d: Likewise. * gas/arm/archv6t2.d: Likewise. * gas/arm/arm7t.d: Likewise. * gas/arm/inst.d: Likewise. * gas/arm/xscale.d: Likewise. PR binutils/10924 * arm-dis.c (arm_opcodes): Add patterns to match undefined LDRB instruction variants. Add pattern for MRS variant that was being confused with CMP. (arm_decode_shift): Place error message in a comment. (print_insn_arm): Note that writing back to the PC is unpredictable. Only print 'p' variants of cmp/cmn/teq/tst instructions if decoding for pre-V6 architectures.	17 years ago
Ramana Radhakrishnan	0bb027fd62	2009-11-17 Edward Nevill <edward.nevill@arm.com> * arm-dis.c (print_insn_thumb32): Handle undefined instruction.	17 years ago
Daniel Jacobowitz	79862e4574	gas/testsuite/ * gas/arm/copro.d, gas/arm/fp-save.d, gas/arm/float.d, gas/arm/fpa-mem.d: Update for removed generic coprocessor instructions and expanded PC-relative offsets. opcodes/ * arm-dis.c (coprocessor_opcodes): Use %A instead of %C. Remove generic coprocessor instructions for FPA loads and stores. (print_insn_coprocessor): Remove %C support. Display address for PC-relative offsets in %A.	17 years ago
Nick Clifton	c1e2689731	PR binutils/10924 * arm-dis.c (UNPREDICTABLE_INSTRUCTION): New macro. (print_insn_arm): Extend %s format control code to check for unpredictable addressing modes. Add support for %S format control code which suppresses this check. (W_BIT, I_BIT, U_BIT, P_BIT): New macros. (WRITEBACK_BIT_SET, IMMEDIATE_BIT_SET, NEGATIVE_BIT_SET, PRE_BIT_SET): New macros. (print_insn_coprocessor): Use the new macros instead of magic constants. (print_arm_address): Likewise. (pirnt_insn_arm): Likewise. (print_insn_thumb32): Likewise.	17 years ago
Paul Brook	62f3b8c867	2009-11-02 Paul Brook <paul@codesourcery.com> ld/testsuite/ * ld-arm/arm-elf.exp: Add new attr-merge-vfp tests. * ld-arm/attr-merge-vfp-1.d: New test. * ld-arm/attr-merge-vfp-1r.d: New test. * ld-arm/attr-merge-vfp-2.d: New test. * ld-arm/attr-merge-vfp-2r.d: New test. * ld-arm/attr-merge-vfp-3.d: New test. * ld-arm/attr-merge-vfp-3r.d: New test. * ld-arm/attr-merge-vfp-4.d: New test. * ld-arm/attr-merge-vfp-4r.d: New test. * ld-arm/attr-merge-vfp-5.d: New test. * ld-arm/attr-merge-vfp-5r.d: New test. * ld-arm/attr-merge-vfp-2.s: New test. * ld-arm/attr-merge-vfp-3.s: New test. * ld-arm/attr-merge-vfp-3-d16.s: New test. * ld-arm/attr-merge-vfp-4.s: New test. * ld-arm/attr-merge-vfp-4-d16.s: New test. gas/ * doc/c-arm.texi: Document new -mfpu options. * config/tc-arm.c (fpu_vfp_ext_v3xd, fpu_vfp_fp16, fpu_neon_ext_fma, fpu_vfp_ext_fma): New. (NEON_ENC_TAB): Add vfma, vfms, vfnma and vfnms. (do_vfp_nsyn_fma_fms, do_neon_fmac): New functions. (insns): Move double precision load/store. Split out double precision VFPv3 instrucitons. Add VFPv4 instructions. (arm_fpus): Add VFPv3-FP16, VFPv3xD and VFPv4 variants. (aeabi_set_public_attributes): Set VFPv4 variants gas/testsuite/ * gas/arm/attr-mfpu-vfpv4.d: New test. * gas/arm/attr-mfpu-vfpv4-d16.d: New test. * gas/arm/neon-fma-cov.d: New test. * gas/arm/neon-fma-cov.s: New test. * gas/arm/vfp-fma-inc.s: New test. * gas/arm/vfp-fma-arm.d: New test. * gas/arm/vfp-fma-arm.s: New test. * gas/arm/vfp-fma-thumb.d: New test. * gas/arm/vfp-fma-thumb.s: New test. * gas/arm/vfma1.d: New test. * gas/arm/vfma1.s: New test. * gas/arm/vfpv3xd.d: New test. * gas/arm/vfpv3xd.s: New test. include/opcode/ * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA, FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define. (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD, FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16, FPU_ARCH_NEON_VFP_V4): Define. binutils/ * readelf.c (arm_attr_tag_VFP_arch): Add VFPv4 and VFPv4-D16. bfd/ * elf32-arm.c (elf32_arm_merge_eabi_attributes): Handle VFPv4 attributes. opcodes/ * arm-dis.c (coprocessor_opcodes): Update to use new feature flags. Add VFPv4 instructions.	17 years ago
Alan Modra	8977d4b219	* arm-dis.c (print_insn): Check symtab_size not *symtab.	17 years ago
Nick Clifton	21d799b5c4	Update soruces to make alpha, arc and arm targets compile cleanly with -Wc++-compat: * config/tc-alpha.c: Add casts. (extended_bfd_reloc_code_real_type): New type. Used to avoid enumeration conversion warnings. (struct alpha_fixup, void assemble_insn, assemble_insn) (assemble_tokens): Use new type. * ecoff.c: Add casts. (mark_stabs): Use enumeration names. * config/obj-elf.c: Add cast * config/tc-arc.c: Add casts. * config/obj-aout.h (text_section,data_section,bss_section): Make extern. * config/obj-elf.c: Add cast. * config/tc-arm.c: Add casts. (X, TxCE, TxCE, TxC3, TxC3w, TxCM_, TxCM, TUE, TUF, CE, CL, cCE) (cCL, C3E, xCM_, nUF, nCE_tag): Change input format to avoid the need for keywords as arguments. * ecoff.c: Add casts. * ecofflink.c: Add casts. * elf64-alpha.c: Add casts. (struct alpha_elf_got_entry, struct alpha_elf_reloc_entry): Move to top level. (SKIP_HOWTO): Use enum name. * elf32-arm.c: Add casts. (elf32_arm_vxworks_bed): Update code to avoid multiple declarations. (struct map_stub): Move to top level. * arc-dis.c Fix casts. * arc-ext.c: Add casts. * arm-dis.c (enum opcode_sentinel_enum): Gave name to anonymous enum. * emultempl/armelf.em: Add casts.	17 years ago
Alan Modra	aa820537ea	update copyright dates	17 years ago
Nick Clifton	7769efb28e	PR 10288 * arm-dis.c (arm_opcodes): Catch non-zero bits 8-11 in register offset or indexed based addressing mode 3.	17 years ago
Nick Clifton	74bdfecf08	PR 10288 * arm-dis.c (arm_opcodes): Catch illegal Addressing Mode 1 patterns. (arm_decode_shift): Catch illegal register based shifts. (print_insn_arm): Properly handle negative register r0 post-indexed addressing.	17 years ago
Doug Kwan	d1aaab3c71	2009-07-10 Doug Kwan <dougkwan@google.com> * arm-disc.c (print_insn_coprocessor, print_insn_arm): Print only lower 32 bits of long types to make hexadecimal output consistent on both 32-bit and 64-bit hosts.	17 years ago
Nick Clifton	1103f72c0f	gas/ * config/tc-arm.c (insns): Fix encoding for torvsc. gas/testsuite/ * gas/arm/iwmmxt2.d: Fix insn pattern for torvsc, add patterns for waddsubhx. * gas/arm/iwmmxt2.s: Add tests for waddsubhx. opcodes/ * arm-dis.c (coprocessor_opcodes): Fix mask for waddbhus.	17 years ago
Nick Clifton	78c66db84c	PR 10288 * arm-dis.c (arm_opcodes): Be more strict about decoding scaled addressing modes.	17 years ago
Nick Clifton	fe56b6cece	PR 10288 * arm-dis.c (coprocessor): Print the LDC and STC versions of the LFM and SFM instructions as comments,. Improve consistency of formatting for instructions displayed as comments and decimal values displayed with their hexadecimal equivalents. Formatting tidy ups. Updated expected disassembler regexps.	17 years ago
Nick Clifton	05413229fd	PR 10288 * arm-dis.c (enum opcode_sentinels): New: Used to mark the boundary between variaant and generic coprocessor instuctions. (coprocessor): Use it. Fix architecture version of MCRR and MRRC instructions. (arm_opcdes): Fix patterns for STRB and STRH instructions. (print_insn_coprocessor): Check architecture and extension masks. Print a hexadecimal version of any decimal constant that is outside of the range of -16 to +32. (print_arm_address): Add a return value of the offset used in the adress, if it is worth printing a hexadecimal version of it. (print_insn_neon): Print a hexadecimal version of any decimal constant that is outside of the range of -16 to +32. (print_insn_arm): Likewise. (print_insn_thumb16): Likewise. (print_insn_thumb32): Likewise. PR 10297 * arm-dis.c (UNDEFINED_INSTRUCTION): New macro for a description of an undefined instruction. (arm_opcodes): Use it. (thumb_opcod): Use it. (thumb32_opc): Use it. Update expected disassembly regrexps in GAS and LD testsuites.	17 years ago
Nick Clifton	0313a2b8d2	PR 10288 * arm-dis.c (print_insn_coprocessor): Check that a user specified ARM architecture supports the matched instruction. (print_insn_arm): Likewise. (select_arm_features): New function. Fills in the fields of an arm_feature_set structure based on a given arm machine number. (print_insn): Initialise an arm_feature_set structure. * objdump.c (disassemble_bytes): Set the USER_SPECIFIED_MACHINE_TYPE flag in the disassemble_info structure if the user has invoked the -m switch. * doc/binutils.texi: Document the additional behaviour of objdump's -m switch for ARM targets. * dis-asm.h (USER_SPECIFIED_MACHINE_TYPE): New value for the flags field of struct disassemble_info. * gas/arm/align.s: Add labels so that COFF based targets can correctly locate THUMB code. * gas/arm/copro.d: Do not pass --architecture switch to objdump.	17 years ago
Nick Clifton	fe2ceba101	PR 10186 * arm-dis.c (thumb32_opcodes): Fix binary value of SEV.W instruction. * gas/arm/thumb32.d: Fix expected binary value of SEV.W instruction. * config/tc-arm.c (T16_32_TAB): Fix binary value of SEV.W instruction.	17 years ago
Nick Clifton	1316c8b37f	PR 10263 * arm-dis.c (print_insn): Ignore is_data if the user has requested the disassembly of data as well as instructions. * objdump.c (disassemble_bytes): Set the DISASSEMBLE_DATA bit in the flags field of the disassemble_info structure if the -D switch is in operation. * dis-asm.h (struct disassemble_info): New value for the flags field.	17 years ago
Christophe Lyon	b8f9ee44f9	2009-04-01 Christophe Lyon <christophe.lyon@st.com> opcodes/ * arm-dis.c (print_insn): Print BE8 opcodes in little endianness. ld/testsuite/ * ld-arm/arm-elf.exp: BE8 tests expect the same output as the default ones. * ld-arm/arm-be8.d: Print opcodes in little endian. * ld-arm/farcall-thumb-arm-be8.d: Removed useless expected result. * ld-arm/farcall-arm-arm-be8.d: Likewise.	18 years ago
Joseph Myers	d460e92e41	gas/testsuite: * gas/arm/mapsecs.d, gas/arm/mapsecs.s: New. opcodes: * arm-dis.c (print_insn): Also check section matches in backwards search for mapping symbol.	18 years ago
Richard Earnshaw	4ce8808b2c	* arm-dis.c (neon_opcodes): Correct bit-mask and patterns for vq{r}shr{u}n.s64 insnstructions.	18 years ago
Joseph Myers	087b80de6e	gas: 2009-01-29 Mark Mitchell <mark@codesourcery.com> * config/tc-arm.c (insns): Correct encoding of qadd, qdadd, qsub, qdsub in Thumb-2 mode. gas/testsuite: 2009-01-29 Mark Mitchell <mark@codesourcery.com> * gas/arm/thumb32.s (qadd): Add qadd, qdadd, qsub, and qdsub. * gas/arm/thumb32.d: Likewise. opcodes: 2009-01-29 Mark Mitchell <mark@codesourcery.com> * arm-dis.c (thumb32_opcodes): Correct decoding for qadd, qdadd, qsub, and qdsub.	18 years ago
Richard Earnshaw	7df76b802e	opcodes: * arm-dis.c (coprocessor_opcodes): Disassemble VFP instructions using unified syntax. gas/testsuite: * gas/arm/group-reloc-ldc.d: Disassembly of VFP instructions now uses unified syntax. * gas/arm/vfp-non-overlap.d: Likewise. * gas/arm/vfp-neon-syntax.d: Likewise. * gas/arm/vfp-neon-syntax_t2.d: Likewise. * gas/arm/vfp1.d: Likewise. * gas/arm/vfp1_t2.d: Likewise. * gas/arm/vfp1xD.d: Likewise. * gas/arm/vfp1xD_t2.d: Likewise. * gas/arm/vfp2.d: Likewise. * gas/arm/vfp2_t2.d: Likewise. * gas/arm/vfpv3-32drs.d: Likewise. * gas/arm/vfpv3-const-conv.d: Likewise. ld/testsuite: * ld-arm/vfp11-fix-scalar.d: Disassembly of VFP instructions now uses unified syntax. * ld-arm/vfp11-fix-vector.d: Likewise.	18 years ago
Catherine Moore	8e79c3df51	Add support for ARM half-precision conversion instructions.	18 years ago
Stan Shebs	bd2e25575c	2008-07-07 Stan Shebs <stan@codesourcery.com> * dis-init.c (init_disassemble_info): Init endian_code field. * arm-dis.c (print_insn): Disassemble code according to setting of endian_code. (print_insn_big_arm): Detect when BE8 extension flag has been set.	18 years ago
Nick Clifton	92c8bd791d	* arm-dis.c (arm_opcodes): Remove superflous escapes of percent operators.	19 years ago
Nick Clifton	2cc7bb5dcf	* arm-dis.c (print_insn): Check for a symtab that exists but is empty.	19 years ago
Nick Clifton	9b201bb5e5	Change source files over to GPLv3.	19 years ago

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