binutils-gdb

Commit Graph

Author	SHA1	Message	Date
Jaydeep Patil	3224e32fb8	sim: riscv: Add support for compressed integer instructions Added support for simulation of compressed integer instruction set ("c"). Added test file sim/testsuite/riscv/c-ext.s to test compressed instructions. The compressed instructions are available for models implementing C extension. Such as RV32IC, RV64IC, RV32GC, RV64GC etc. Approved-By: Andrew Burgess <aburgess@redhat.com>	2 years ago
Jose E. Marchesi	920d9f0b39	sim: bpf: remove support for ldinddw and ldabsdw instructions This patch removes support for the two instructions above from the GNU simulator, including the corresponding tests. These instructions do not really exist in BPF and are not recognized as such by the kernel verifier. This has now been pointed out during the standardization of the BPF ISA. Signed-off-by: Jose E. Marchesi <jose.marchesi@oracle.com>	2 years ago
Dimitar Dimitrov	b83808a8a2	sim: Fix compile errors The following change broke simulator testsuite with host GCC 13: commit `435ad222b3` sim: warnings: compile build tools with -Werror too Host GCC13 complains about missing function prototypes: binutils/sim/testsuite/common/bits-gen.c:26:1: error: no previous prototype for ‘gen_struct’ [-Werror=missing-prototypes] 26 \| gen_struct (void) \| ^~~~~~~~~~ Fix by making the functions static, which instructs the compiler that there is no need for a prototype. Signed-off-by: Dimitar Dimitrov <dimitar@dinux.eu>	2 years ago
Andrew Burgess	1d506c26d9	Update copyright year range in header of all files managed by GDB This commit is the result of the following actions: - Running gdb/copyright.py to update all of the copyright headers to include 2024, - Manually updating a few files the copyright.py script told me to update, these files had copyright headers embedded within the file, - Regenerating gdbsupport/Makefile.in to refresh it's copyright date, - Using grep to find other files that still mentioned 2023. If these files were updated last year from 2022 to 2023 then I've updated them this year to 2024. I'm sure I've probably missed some dates. Feel free to fix them up as you spot them.	2 years ago
Dimitar Dimitrov	fcd5cdd5ae	sim: pru: Fix emulation of carry bit The PRU architecture documentation [1] was used for the initial GNU simulator implementation. But recently [2] TI confirmed the carry behaviour was wrongly documented. In reality, the PRU carry behaves like the carry in ARM processors. This patch fixes simulator to align with latest recommendations from TI. The new carry.s test was also validated to pass on real hardware - a BeaglePlay board [3]. That test is a bit long because TI still has not released official updates for the PRU documents. And I wanted to ensure simulator handles all edge cases exactly as the real hardware does. [1] https://www.ti.com/lit/pdf/spruij2 [2] https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1244359/sk-am64b-am64x-pru-assembler-how-works-this-bloody-carry [3] https://www.beagleboard.org/boards/beagleplay Signed-off-by: Dimitar Dimitrov <dimitar@dinux.eu>	2 years ago
Jeff Law	b3fa92f12a	Yet another fix for mcore-sim (rotli) This came up testing the CRC optimization work from Mariam@RAU. Basically to optimize some CRC loops into table lookups or carryless multiplies, we may need to do a bit reflection, which on the mcore processor is done using a rotate instruction. Unfortunately the simulator implementation of rotates has the exact same problem as we saw with right shifts. The input value may have been sign extended from 32 to 64 bits. When we rotate the extended value, we get those sign extension bits and thus the wrong result. The fix is the same. Rather than using a "long", use a uint32_t for the type of the temporary. This fixes a handful of tests in the GCC testsuite:	2 years ago
Jeff Law	37d6ee9350	Fix right shifts in mcore simulator on 64 bit hosts. If the value to be shifted has the sign bit set, the sign bit would get copied into bits 32..63 of the temporary. Those would then be right shifted into the final value giving an incorrect final result. This was observed with upcoming GCC improvements which eliminate unnecessary extensions.	2 years ago
Jose E. Marchesi	9d4db627b2	sim: bpf: do not use semicolon to begin comments The BPF assembler has been updated to follow the clang convention in the interpretation of semicolons: they separate statements and directives, and do not start line comments.	2 years ago
Jaydeep Patil	1c37b30945	sim/riscv: fix JALR instruction simulation Fix 32bit 'jalr rd,ra,imm' integer instruction, where RD was written before using it to calculate destination address. This commit also improves testutils.inc for riscv; make use of pushsection and popsection when adding things to .data, and setup the %gp global pointer register within the 'start' macro. Approved-By: Andrew Burgess <aburgess@redhat.com>	2 years ago
Jeff Law	c524b5f2f6	[RFA] Fix for mcore simulator I was looking for cases where a GCC patch under evaluation would cause test results to change. Quite surprisingly the mcore-elf port showed test differences. After a fair amount of digging my conclusion was the sequences before/after the patch should have been semantically the same. Of course if the code is supposed to behave the same, then that points to problems elsewhere (assembler, linker, simulator). Sure enough the mcore simulator was mis-handling the sign extension instructions. The simulator implementation of sextb is via paired shift-by-24 operations. Similarly the simulator implements sexth via paired shift-by-16 operations. The temporary holding the value was declared as a "long" thus this approach worked fine for hosts with a 32 bit wide long and failed miserably for hosts with a 64 bit wide long. This patch makes the shift count automatically adjust based on the size of the temporary. It includes a simple test for sextb and sexth. I have _not_ done a full audit of the mcore simulator for more 32->64 bit issues. This also fixes 443 execution tests in the GCC testsuite	3 years ago
Stafford Horne	8eb7b3a7db	sim: or1k: Eliminate dangerous RWX load segments This fixes test failures caused by the new linker warning which report: ./ld/ld-new: warning: load.S.x has a LOAD segment with RWX permissions Fix this by splitting the linker MEMORY into ram and rom to avoid generating RWX sections. This required tests to be adjusted to fix issues with the move. Namely: - fpu tests: were incorrectly using l.ori with ha(anchor) which now that we pushed the anchor up in memory it exposes the bug. Update to used the correct l.movhi instruction instead. - adrp test: the test reports ram offset addresses, now that we have moved memory layout around a bit I adjusted the test output. Some padding is added before pi to show that the actual address of pi and the adrp page offset are not the same. Bug: https://sourceware.org/PR29957	3 years ago
Alan Modra	0e1b3420fb	sim prune_warnings Remove some of the warnings generated by newer versions of ld. * testsuite/lib/sim-defs.exp (prune_warnings_extra): New. Arrange to run it from prune_warnings.	3 years ago
Jose E. Marchesi	3b2ffd32d2	bpf: sim: do not overflow instruction immediates in tests This patch fixes some instructions in the BPF tests that overflow the signed immediates. Note that this happened to work before by chance, as GAS would silently truncate. Tested in bpf-unknown-none. Signed-off-by: Jose E. Marchesi <jose.marchesi@oracle.com>	3 years ago
Jose E. Marchesi	4200337219	bpf: fix neg and neg32 BPF instructions in simulator This patch fixes the semantics of the neg and neg32 BPF instructions in the simulator, and also updates the corresponding tests accordingly. Tested in target bpf-unknown-none.	3 years ago
Jose E. Marchesi	7bb9f0c2be	sim/bpf: desCGENization of the BPF simulator The BPF port in binutils has been rewritten (commit `d218e7fedc`) in order to not be longer based on CGEN. Please see that commit log for more information. This patch updates the BPF simulator accordingly. The new implementation is much simpler and it is based on the new BPF opcodes. Tested with target bpf-unknown-none with both 64-bit little-endian host and 32-bit little-endian host. Note that I have not tested in a big-endian host yet. I will do so once this lands upstream so I can use the GCC compiler farm.	3 years ago
Jose E. Marchesi	873a1ec405	sim: bpf: update to new BPF relocations This patch updates the BPF GNU sim testsuite in order to match the new BPF relocations introduced in binutils in a recent patch [1]. [1] https://sourceware.org/pipermail/binutils/2023-March/126429.html	3 years ago
Guillermo E. Martinez	7cbf35923d	sim: bpf: fix testsuite due to linker warnings [PR sim/29954] On a bpf-- testsuite fails: ./ld/ld-new: warning: test has a LOAD segment with RWX permissions Adjusting `--memory-size=10Mb' to the simulator bpf testsuite passes. Tested on bpf--: Bug: https://sourceware.org/PR29954 sim/testsuite: * bpf/allinsn.exp (SIMFLAGS_FOR_TARGET): Adjust sim flags.	3 years ago
Joel Brobecker	213516ef31	Update copyright year range in header of all files managed by GDB This commit is the result of running the gdb/copyright.py script, which automated the update of the copyright year range for all source files managed by the GDB project to be updated to include year 2023.	3 years ago
Dimitar Dimitrov	7bee555bb7	sim: pru: Fix behaviour when loop count is zero If the counter for LOOP instruction is provided by a register with value zero, then the instruction must cause a PC jump directly to the loop end. But in that particular case simulator must not initialize its internal loop variables, because loop body will not be executed. Instead, simulator must obtain the loop's end address directly from the LOOP instruction. Signed-off-by: Dimitar Dimitrov <dimitar@dinux.eu>	3 years ago
Mike Frysinger	7b3dd7b9b3	sim: testsuite: fix cris stat3 in diff setups This test uses the test itself as an input to stating regular files. This gets funky though: when we run check in parallel, the output object dir is the subdir that matches the .exp file. When we run with -j1, the output object dir is the sim builddir itself. The old test would append argv[0] to find the file, while the new test uses basename on it. Each method works in only one of the aforementioned build scenarios. Rather than complicate this any more, switch to a different file that we know will always exist: the Makefile.	3 years ago
Mike Frysinger	4ce3ba0865	sim: testsuite: fix cris badarch in multi-target builds This test assumes that /bin/sh will never be a CRIS ELF by way of assuming that the current bfd cannot load it (since a basic cris cross-compiler only understands CRIS ELFs). In a multi-target build though, bfd understands just about every ELF out there, so we're able to read the /bin/sh format before failing at a diff point in the cris code. Let's switch to using / instead since it'll fail for a similar reason (at least similar enough for what this test is testing).	3 years ago
Mike Frysinger	8f97b519fb	sim: testsuite: improve parallel test processing The current logic limits itself to a maxdepth of 4 when looking for results. This wouldn't be a problem if cris didn't have a testsuite at a depth of 5 which we end up ignoring when summarizing. Rather than bump the number from 4 to 5, rework the code so that we gather the exact set of tests that we tried to run.	3 years ago
Mike Frysinger	e60091e4d3	sim: testsuite: update ignored .exp files [PR sim/29596] Now that we run `check/foo.exp` instead of `check/./foo.exp`, update the config/ & lib/ exceptions to cover both paths. Bug: https://sourceware.org/PR29596	3 years ago
Mike Frysinger	86ef36f655	sim: testsuite: tweak parallel find invocation [PR sim/29596] Make sure we invoke runtest with the same exp filenames when running in parallel as it will find when run single threaded. When `runtest` finds files itself, it will use paths like "aarch64/allinsn.exp". When we run `find .` with the %p option, it produces "./aarch64/allinsn.exp". Switch to %P to get "aarch64/allinsn.exp". Bug: https://sourceware.org/PR29596	3 years ago
Tsukasa OI	c6422d7be7	sim/riscv: fix multiply instructions on simulator After this commit: commit `0938b032da` Date: Wed Feb 2 10:06:15 2022 +0900 RISC-V: Add 'Zmmul' extension in assembler. some instructions in the RISC-V simulator stopped working as a new instruction class 'INSN_CLASS_ZMMUL' was added, and some existing instructions were moved into this class. The simulator doesn't currently handle this instruction class, and so the instructions will now cause an illegal instruction trap. This commit adds support for INSN_CLASS_ZMMUL, and adds a test that ensures the affected instructions can be executed by the simulator. Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com> Reviewed-by: Andrew Burgess <aburgess@redhat.com>	4 years ago
Jeff Law	477904ca75	Fix for v850e divq instruction This is the last of the correctness fixes I've been carrying around for the v850. Like the other recent fixes, this is another case where we haven't been as careful as we should WRT host vs target types. For the divq instruction both operands are 32 bit types. Yet in the simulator code we convert them from unsigned int to signed long by assignment. So 0xfffffffb (aka -5) turns into 4294967291 and naturally that changes the result of our division. The fix is simple, insert a cast to int32_t to force interpretation as a signed value. Testcase for the simulator is included. It has a trivial dependency on the bins patch.	4 years ago
Jeff Law	49fffa58f7	Fix "bins" simulation for v850e3v5 I've been carrying this for a few years. One test in the GCC testsuite is failing due to a bug in the handling of the v850e3v5 instruction "bins". When the "bins" instruction specifies a 32bit bitfield size, the simulator exhibits undefined behavior by trying to shift a 32 bit quantity by 32 bits. In the case of a 32 bit shift, we know what the resultant mask should be. So we can just set it. That seemed better than using 1UL for the constant (on a 32bit host unsigned long might still just be 32 bits) or needlessly forcing everything to long long types. Thankfully the case where this shows up is only bins <src>, 0, 32, <dest> which would normally be encoded as a simple move. * testsuite/v850/allinsns.exp: Add v850e3v5. * testsuite/v850/bins.cgs: New test. * v850/simops.c (v850_bins): Avoid undefined behavior on left shift.	4 years ago
Jeff Law	5321c31bc7	Fix for MUL instruction on the v850 * sim/v850/simops.c (Multiply64): Properly test if we need to negate either of the operands. * sim/testsuite/v850/mul.cgs: New test.	4 years ago
Hans-Peter Nilsson	7443cb7479	sim/testsuite/cris/c/stat3.c: Fix formatting nit * c/stat3.c (main): Fix formatting nit.	4 years ago
Mike Frysinger	d0b2f561a1	sim: testsuite: cleanup the istarget * logic Now that the multitarget testing has settled, clean up the cases where istarget * is used. This ends up being mostly style unindenting.	5 years ago
Hans-Peter Nilsson	e63f65fea9	sim/testsuite: Default global_cc_os and global_cc_works properly There was an omission on `3e6dc39ed7` "sim/testsuite: Set global_cc_os also when no compiler is found"; global_cc_os wasn't set for other than the primary target, which means that the "unguarded" use of global_cc_os in testsuite/cris/c/c.exp caused the dreaded "ERROR: can't read "global_cc_os": no such variable" when e.g. configuring for pru-elf and doing "make check-sim". Better initializing both variables at the top to default values, rather than adding another single 'set global_cc_os ""', to reduce the risk of not setting them properly if or when that if-statement-chain is made longer. sim/testsuite: * lib/sim-defs.exp (sim_init_toolchain): Default global_cc_os and global_cc_works properly, before if-chain.	4 years ago
Hans-Peter Nilsson	234f5865fa	sim/testsuite/cris: If failing compilation, mark C tests as errors ...when we know we have a working compiler. This will reduce the risk of faulty edits by exposing them rather than hiding them as "unresolved". It also harmonizes behavior with that of run_sim_test. * c/c.exp: Mark C tests failing compilation test errors.	4 years ago
Hans-Peter Nilsson	4b0e74fd18	sim/testsuite/cris: Remove faulty use of basename in C tests Calls to basename were added here as part of commit `e1e1ae6e9b` "sim: testsuite: fix objdir handling", but that commit missed adding "#include <libgen.h>" or the equivalent GNU extension, see basename(3). Fixing that shows a logical error in the change to openpf1.c; the non-/-prefixed code-path was changed instead of the "/"-prefixed code-path, which is the one executed after that commit. For "newlib" these tests failed linking after that commit. Recent newlib has the (asm-renamed) GNU-extension-variant of basename, but we're better off not using it at all. Unfortunately, compilation failures for C tests run by the machinery in c.exp are currently just marked "unresolved", in contrast to C and assembler tests run by calling run_sim_test. The interaction of calling with the full program-path vs. use of --sysroot exposes a consistency problem: when --sysroot is used, argv[0] isn't the path by which the program can find itself. It's undecided whether argv[0] for the program running in the simulator should be edited (related to the naked argument to the simulator before passing on to the simulated program) to remove a leading --sysroot. Either way, such a change would be out of scope for this commit. * c/stat3.c (mybasename): New macro. Use it instead of basename. * c/openpf1.c: Correct basename-related change and update related comment.	4 years ago
Hans-Peter Nilsson	6f62dbfb12	sim/testsuite/cris: As applicable, require simoption --cris-900000xx Apply the new run_sim_test option "require" as in "#require simoption --cris-900000xx" for all tests using that option. This allows a clean test-suite-run for a build with --disable-sim-hardware, where that option is not supported, by skipping those tests as "untested". sim/testsuite/cris: * asm/io1.ms, asm/io2.ms, asm/io3.ms, asm/io6.ms, asm/io7.ms: Call "#require: simoption --cris-900000xx".	4 years ago
Hans-Peter Nilsson	81064d7abc	sim/testsuite: Support "requires: simoption <--name-of-option>" Simulator features can be present or not, typically depending on different-valued configure options, like --enable-sim-hardware[=off\|=on]. To avoid failures in test-suite-runs when testing such configurations, a new predicate is needed, as neither "target", "progos" nor "mach" fits cleanly. The immediate need was to check for presence of a simulator option, but rather than a specialized "requires-simoption:" predicate I thought I'd handle the general (parametrized) need, so here's a generic predicate machinery and a (first) predicate to use together with it; checking whether a particular option is supported, by looking at "run --help" output. This was inspired by the check_effective_target_ machinery in the gcc test-suite. Multiple "requires: <requirement> <parameter>" form a list of predicates (with parameters), to be used as a conjunction. sim/testsuite: * lib/sim-defs.exp (sim_check_requires_simoption): New function. (run_sim_test): Support "requires: <requirement> <parameter>".	4 years ago
Hans-Peter Nilsson	46f238477f	sim/testsuite/cris/hw/rv-n-cris/irq1.ms: Disable due to randomness For reasons that remain largely to be investigated (besides the apparent lack of synchronization between two processes), this test fails randomly, with two different sets of common outputs. Curiously, that doesn't happen for the other similar tests. There's a comment that mentions this, though that doesn't make it a sustainable part of a test-suite. (Known-blinking tests should be disabled until fixed.) sim/testsuite/cris: * hw/rv-n-cris/irq1.ms: Disable by use of a never-matched "progos" value.	4 years ago
Hans-Peter Nilsson	56ba3848dc	sim/testsuite/cris/c: Use -sim3 but only for newlib targets Commit `a39487c668` "sim: cris: use -sim with C tests for cris-elf targets" caused " -sim" to be appended to CFLAGS_FOR_TARGET for cris--elf, where testing had until then relied on "RUNTESTFLAGS=--target_board=cris-sim" being passed when running "make check-sim", adding the right options. While "-sim" happens to work, the baseboard-file cris-sim.exp uses "-sim3" so for consistency use that instead. Then commit `b42f20d2ac` "sim: testsuite: drop most specific istarget checks" caused " -sim" to be appended for all targets, which just doesn't work. For example, for crisv32-linux-gnu, that's not a recognized option and will cause a dejagnu error and further testing in c.exp will be aborted. While cris-sim.exp appends "-static" for -linux-gnu, further changes in the test-suite have caused "linux"-specific tests to break, so that part will be tended to separately. But, save and restore CFLAGS_FOR_TARGET around the modification and use where needed, to not have the CRIS-specific modification affect a continuing test-run (possibly for other targets). sim/testsuite/cris: c/c.exp (CFLAGS_FOR_TARGET): Replace appended option " -sim" with " -sim3", but do it conditionally for newlib targets. Save and restore CFLAGS_FOR_TARGET in saved_CFLAGS_FOR_TARGET such that it doesn't affect the value of CFLAGS_FOR_TARGET outside c.exp.	4 years ago
Hans-Peter Nilsson	3e6dc39ed7	sim/testsuite: Set global_cc_os also when no compiler is found If we don't set this variable, it doesn't exist, and using "#progos:" in an assembler-file will cause an error rather than just skipping the test, viz: Running /src/sim/testsuite/cris/hw/rv-n-cris/rvc.exp ... ERROR: tcl error sourcing /src/sim/testsuite/cris/hw/rv-n-cris/rvc.exp. ERROR: can't read "global_cc_os": no such variable while executing "if { $opts(progos) != "" && $opts(progos) != $global_cc_os } { untested $subdir/$name return }" (procedure "run_sim_test" line 102) Neither the commit introducing progos, nor the top comment in run_sim_test, mentions progos as intended only for C tests, or that its use must be gated on $global_cc_works != 0, so (not) setting it in the no-working-compiler path seems just overlooked. Allowing it to be used for assembler tests makes it usable for e.g. an always-false predicate and in expressions in .exp files without gating on $global_cc_works != 0. With this patch, global_cc_os is set to "", just as for "unknown OS". sim/testsuite: * lib/sim-defs.exp (sim_init_toolchain): Set global_cc_os also when no working target C compiler is found.	4 years ago
Hans-Peter Nilsson	3293b4f667	sim/testsuite/cris: Assembler testcase for PRIx32 usage bug Several C test-cases exposed the bug, but let's have one for people who test using just the assembler and linker. * asm/endmem1.ms: New test.	4 years ago
Faraz Shahbazker	06c441ccef	sim: mips: Add simulator support for mips32r6/mips64r6 2022-02-01 Ali Lown <ali.lown@imgtec.com> Andrew Bennett <andrew.bennett@imgtec.com> Dragan Mladjenovic <dragan.mladjenovic@rt-rk.com> Faraz Shahbazker <fshahbazker@wavecomp.com> sim/common/ChangeLog: * sim-bits.h (EXTEND9, EXTEND18 ,EXTEND19, EXTEND21, EXTEND26): New macros. sim/mips/ChangeLog: * Makefile.in (IGEN_INCLUDE): Add mips3264r6.igen. * configure: Regenerate. * configure.ac: Support mipsisa32r6 and mipsisa64r6. (sim_engine_run): Pick simulator model from processor specified in e_flags. * cp1.c (value_fpr): Handle fmt_dc32. (fp_unary, fp_binary): Zero initialize locals. (update_fcsr, fp_classify, fp_rint, fp_r6_cmp, inner_fmac, fp_fmac, fp_min, fp_max, fp_mina, fp_maxa, fp_fmadd, fp_fmsub): New functions. (sim_fpu_class_mips_mapping): New. * cp1.h (fcsr_ABS2008_mask, fcsr_ABS2008_shift): New define. * interp.c (MIPSR6_P): New. (load_word): Allow unaligned memory access for MIPSR6. * micromips.igen (sc, scd): Adapt to new do_sc* helper signature. * mips.igen: Add r6 models. (signal_if_cti, forbiddenslot32): New helpers. (delayslot32): Use signal_if_cti. (do_sc, do_scd); Add store_ll_bit parameter. (sc, scd): Adapt to previous change. (nal, beq, bal): New definitions for r6. (sll): Split nop and ssnop cases into ... (nop, ssnop): New definitions. (loadstore_ea): Use the 32-bit compatibility adressing. (cache): Split logic into ... (do_cache): New helper. (check_fpu): Select IEEE 754-2008 mode for R6. (not_word_value, unpredictable, check_mt_hilo, check_mf_hilo, check_multi_hilo, check_div_hilo, check_u64, do_dmfc1b, add, li, addu, and, andi, bgez, bgtz, blez, bltz, bne, break, dadd, daddiu, daddu, dror, dror32, drorv, dsll, dsll32, dsllv, dsra, dsra32, dsrav, dsrl, dsrl32, dsub, dsubu, j, jal, jalr, jalr.hb, lb, lbu, ld, lh, lhu, lui, lw, lwu, nor, or, ori, ror, rorv, sb, sd, sh, sll, sllv, slt, slti, sltiu, sltu, sra, srav, srl, srlv, sub, subu, sw, sync, syscall, teq, tge, tgeu, tlt, tltu, tne, xor, xori, check_fmt_p, do_load_double, do_store_double, abs.FMT, add.FMT, ceil.l.FMT, ceil.w.FMT, cfc1, ctc1, cvt.d.FMT, cvt.l.FMT, cvt.w.FMT, div.FMT, dfmc1, dmtc1, floor.l.FMT, floor.w.FMT, ldc1, lwc1, mfc1, mov.FMT, mtc1, mul.FMT, recip.FMT, round.l.FMT, round.w.FMT, rsqrt.FMT, sdc1, sqrt.FMT, sub.FMT, swc1, trunc.l.FMT, trunc.w.FMT, bc0f, bc0fl, bc0t, bc0tl, dmfc0, dmtc0, eret, mfc0, mtc0, cop, tlbp, tlbr, tlbwi, tlbwr): Enable on r6 models. mips3264r2.igen (dext, dextm, dextu, di, dins, dinsm, dinsu, dsbh, dshd, ei, ext, mfhc1, mthc1, ins, seb, seh, synci, rdhwr, wsbh): Likewise. * mips3264r6.igen: New file. * sim-main.h (FP_formats): Add fmt_dc32. (FORBIDDEN_SLOT): New macros. (simFORBIDDENSLOT, FP_R6CMP_, FP_R6CLASS_): New defines. (fp_r6_cmp, fp_classify, fp_rint, fp_min, fp_max, fp_mina, fp_maxa, fp_fmadd, fp_fmsub): New declarations. (R6Compare, Classify, RoundToIntegralExact, Min, Max, MinA, MaxA, FusedMultiplyAdd, FusedMultiplySub): New macros. Wrapping previous declarations. sim/testsuite/mips/ChangeLog: * basic.exp: Add r6-.s tests. (run_r6_removed_test): New function. (run_endian_tests): New function. hilo-hazard-3.s: Skip for mipsr6. r2-fpu.s: New test. * r6-64.s: New test. * r6-branch.s: New test. * r6-forbidden.s: New test. * r6-fpu.s: New test. * r6-llsc-dp.s: New test. * r6-llsc-wp.s: New test. * r6-removed.csv: New test. * r6-removed.s: New test. * r6.s: New test. * utils-r6.inc: New inc.	4 years ago
Mike Frysinger	39a5fdbc65	sim: testsuite: migrate to standard uintXX_t types This old code setup its own uintXX types, but since we require C11 now, we can assume the standard uintXX_t types exist and use them.	4 years ago
Joel Brobecker	4a94e36819	Automatic Copyright Year update after running gdb/copyright.py This commit brings all the changes made by running gdb/copyright.py as per GDB's Start of New Year Procedure. For the avoidance of doubt, all changes in this commits were performed by the script.	4 years ago
Mike Frysinger	de8a2781a5	sim: use ## for automake comments The ## marker tells automake to not include the comment in its generated output, so use that in most places where the comment only makes sense in the inputs.	4 years ago
Mike Frysinger	3daaa003d2	sim: frv: split up testsuite a bit Running frv's allinsn in serial is quite slow due to the sheer number of tests it contains. By splitting it up and running in parallel, the execution time on my system goes from ~100sec to ~60sec.	4 years ago
Mike Frysinger	b42f20d2ac	sim: testsuite: drop most specific istarget checks We'll rely on the toolchain probing to determine whether each arch's tests can be run rather the current configure target. This allows testing all of the ports in a multitarget configuration. For now, we don't reformat the files entirely to make it easier to review, and in case we need to make adjustments. Once this feels like it's stable, we can flatten the code a bit by removing the if statement entirely.	4 years ago
Mike Frysinger	804de1faf4	sim: testsuite: support parallel execution Break up the dejagnu logic so that we can parallelize the testsuite. This takes a page from gcc & gdb where each .exp is run in isolation instead of in serial. For most targets, this doesn't make much of a difference as they only have a single .exp. A few (like cris & frv) have multiple .exp though and will see a bit of a speed up. The real gain is when testing a multitarget build. This way we can run all the targets in parallel and cut the execution time a bit. On my system, it goes from ~155sec to ~100sec. We can gain further speedups by splitting up some of the larger .exp files into smaller groups. We'll do that in a followup though.	4 years ago
Mike Frysinger	7a259895bb	sim: testsuite: expand arch specific toolchain settings Leverage the new per-port toolchain settings to initialize the env for eeach set of tests. This allows us to run all the tests in a multitarget build if the user sets up the vars. If they don't, we can still skip all the tests.	4 years ago
Mike Frysinger	8996c21067	sim: testsuite: setup per-port toolchain settings for multitarget build Gas does not support multitarget builds -- it still only supports a single input & output format. ld is a bit better, but requires manual flags to select the right output. This makes it impossible to run the complete testsuite in a multitarget build. To address this limitation, create a suite of FOR_TARGET variables so these can be set to precompiled as & ld programs. It requires a bit of setup ahead of time, but it's a one-time cost, and makes running the full testsuite at once much easier.	5 years ago
Mike Frysinger	6916d9e65c	sim: testsuite: add dedicated flag for init toolchain tests As we setup more reliable CC_FOR_TARGET variables for each target, the bfin way of overriding it to stuff custom CFLAGS doesn't scale well. Add a dedicated CFLAGS_FOR_TARGET_init setting that each set of tests can setup if they want to add custom options.	4 years ago
Mike Frysinger	2b9c7c262e	sim: testsuite: clean up arch specific toolchain settings In a multitarget build, we process all targets in order, so make sure the toolchain settings from one don't leak into the next.	4 years ago

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594 Commits (master)