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* ld-mips-elf/elf-rel-xgot-n64-linux.d: New file. * ld-mips-elf/mips-elf.exp: Use the new files for Linux.ezannoni_pie-20030916-branch
Thiemo Seufer
23 years ago
6 changed files with 1000 additions and 69 deletions
@ -0,0 +1,365 @@ |
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#objdump: -dr --prefix-addresses -mmips:sb1 |
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#name: \.set arch=FOO |
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dump\.o: file format .*mips |
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Disassembly of section \.text: |
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00000000 <[^>]*> cache 0x1,0\(zero\) |
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00000004 <[^>]*> cache 0x2,0\(zero\) |
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00000008 <[^>]*> cache 0x3,0\(zero\) |
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0000000c <[^>]*> dmult a0,a1 |
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00000010 <[^>]*> dmultu a1,a2 |
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00000014 <[^>]*> movn a2,a3,zero |
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00000018 <[^>]*> movz a3,t0,zero |
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0000001c <[^>]*> ddiv zero,t0,t1 |
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00000020 <[^>]*> ddivu zero,t1,t2 |
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00000024 <[^>]*> 0x16c5005 |
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00000028 <[^>]*> movt t3,t4,\$fcc3 |
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0000002c <[^>]*> wait |
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00000030 <[^>]*> cache 0x4,16\(t6\) |
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00000034 <[^>]*> 0x71ee0010 |
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00000038 <[^>]*> c0 0x23 |
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0000003c <[^>]*> c0 0x21 |
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00000040 <[^>]*> c0 0x22 |
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00000044 <[^>]*> madd a0,a1 |
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00000048 <[^>]*> maddu a1,a2 |
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0000004c <[^>]*> mul a2,a3,t0 |
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00000050 <[^>]*> bc1f 00000050 <[^>]*> |
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00000054 <[^>]*> bc1f \$fcc1,00000050 <[^>]*> |
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00000058 <[^>]*> bc1fl \$fcc1,00000050 <[^>]*> |
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0000005c <[^>]*> bc1t \$fcc1,00000050 <[^>]*> |
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00000060 <[^>]*> bc1tl \$fcc2,00000050 <[^>]*> |
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00000064 <[^>]*> c\.f\.d \$f4,\$f6 |
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00000068 <[^>]*> c\.f\.d \$fcc1,\$f4,\$f6 |
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0000006c <[^>]*> ldxc1 \$f2,a0\(a1\) |
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00000070 <[^>]*> lwxc1 \$f2,a0\(a1\) |
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00000074 <[^>]*> madd\.d \$f0,\$f2,\$f4,\$f6 |
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00000078 <[^>]*> madd\.s \$f0,\$f2,\$f4,\$f6 |
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0000007c <[^>]*> movf a0,a1,\$fcc4 |
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00000080 <[^>]*> movf\.d \$f4,\$f6,\$fcc0 |
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00000084 <[^>]*> movf\.s \$f4,\$f6,\$fcc0 |
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00000088 <[^>]*> movn a0,a2,a2 |
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0000008c <[^>]*> movn\.d \$f4,\$f6,a2 |
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00000090 <[^>]*> movn\.s \$f4,\$f6,a2 |
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00000094 <[^>]*> movt a0,a1,\$fcc4 |
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00000098 <[^>]*> movt\.d \$f4,\$f6,\$fcc0 |
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0000009c <[^>]*> movt\.s \$f4,\$f6,\$fcc0 |
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000000a0 <[^>]*> movz a0,a2,a2 |
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000000a4 <[^>]*> movz\.d \$f4,\$f6,a2 |
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000000a8 <[^>]*> movz\.s \$f4,\$f6,a2 |
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000000ac <[^>]*> msub\.d \$f0,\$f2,\$f4,\$f6 |
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000000b0 <[^>]*> msub\.s \$f0,\$f2,\$f4,\$f6 |
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000000b4 <[^>]*> nmadd\.d \$f0,\$f2,\$f4,\$f6 |
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000000b8 <[^>]*> nmadd\.s \$f0,\$f2,\$f4,\$f6 |
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000000bc <[^>]*> nmsub\.d \$f0,\$f2,\$f4,\$f6 |
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000000c0 <[^>]*> nmsub\.s \$f0,\$f2,\$f4,\$f6 |
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000000c4 <[^>]*> prefx 0x4,a0\(a1\) |
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000000c8 <[^>]*> recip\.d \$f4,\$f6 |
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000000cc <[^>]*> recip\.s \$f4,\$f6 |
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000000d0 <[^>]*> rsqrt\.d \$f4,\$f6 |
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000000d4 <[^>]*> rsqrt\.s \$f4,\$f6 |
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000000d8 <[^>]*> sdxc1 \$f4,a0\(a1\) |
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000000dc <[^>]*> swxc1 \$f4,a0\(a1\) |
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000000e0 <[^>]*> abs\.ps \$f0,\$f2 |
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000000e4 <[^>]*> add\.ps \$f2,\$f4,\$f6 |
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000000e8 <[^>]*> alnv\.ps \$f6,\$f8,\$f10,v1 |
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000000ec <[^>]*> c\.eq\.ps \$f8,\$f10 |
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000000f0 <[^>]*> c\.eq\.ps \$fcc2,\$f10,\$f12 |
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000000f4 <[^>]*> c\.f\.ps \$f8,\$f10 |
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000000f8 <[^>]*> c\.f\.ps \$fcc2,\$f10,\$f12 |
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000000fc <[^>]*> c\.le\.ps \$f8,\$f10 |
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00000100 <[^>]*> c\.le\.ps \$fcc2,\$f10,\$f12 |
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00000104 <[^>]*> c\.lt\.ps \$f8,\$f10 |
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00000108 <[^>]*> c\.lt\.ps \$fcc2,\$f10,\$f12 |
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0000010c <[^>]*> c\.nge\.ps \$f8,\$f10 |
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00000110 <[^>]*> c\.nge\.ps \$fcc2,\$f10,\$f12 |
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00000114 <[^>]*> c\.ngl\.ps \$f8,\$f10 |
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00000118 <[^>]*> c\.ngl\.ps \$fcc2,\$f10,\$f12 |
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0000011c <[^>]*> c\.ngle\.ps \$f8,\$f10 |
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00000120 <[^>]*> c\.ngle\.ps \$fcc2,\$f10,\$f12 |
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00000124 <[^>]*> c\.ngt\.ps \$f8,\$f10 |
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00000128 <[^>]*> c\.ngt\.ps \$fcc2,\$f10,\$f12 |
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0000012c <[^>]*> c\.ole\.ps \$f8,\$f10 |
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00000130 <[^>]*> c\.ole\.ps \$fcc2,\$f10,\$f12 |
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00000134 <[^>]*> c\.olt\.ps \$f8,\$f10 |
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00000138 <[^>]*> c\.olt\.ps \$fcc2,\$f10,\$f12 |
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0000013c <[^>]*> c\.seq\.ps \$f8,\$f10 |
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00000140 <[^>]*> c\.seq\.ps \$fcc2,\$f10,\$f12 |
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00000144 <[^>]*> c\.sf\.ps \$f8,\$f10 |
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00000148 <[^>]*> c\.sf\.ps \$fcc2,\$f10,\$f12 |
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0000014c <[^>]*> c\.ueq\.ps \$f8,\$f10 |
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00000150 <[^>]*> c\.ueq\.ps \$fcc2,\$f10,\$f12 |
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00000154 <[^>]*> c\.ule\.ps \$f8,\$f10 |
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00000158 <[^>]*> c\.ule\.ps \$fcc2,\$f10,\$f12 |
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0000015c <[^>]*> c\.ult\.ps \$f8,\$f10 |
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00000160 <[^>]*> c\.ult\.ps \$fcc2,\$f10,\$f12 |
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00000164 <[^>]*> c\.un\.ps \$f8,\$f10 |
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00000168 <[^>]*> c\.un\.ps \$fcc2,\$f10,\$f12 |
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0000016c <[^>]*> cvt\.ps\.s \$f12,\$f14,\$f16 |
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00000170 <[^>]*> cvt\.s\.pl \$f16,\$f18 |
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00000174 <[^>]*> cvt\.s\.pu \$f18,\$f20 |
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00000178 <[^>]*> luxc1 \$f20,a0\(a1\) |
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0000017c <[^>]*> madd\.ps \$f20,\$f22,\$f24,\$f26 |
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00000180 <[^>]*> mov\.ps \$f24,\$f26 |
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00000184 <[^>]*> movf\.ps \$f26,\$f28,\$fcc2 |
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00000188 <[^>]*> movn\.ps \$f26,\$f28,v1 |
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0000018c <[^>]*> movt\.ps \$f28,\$f30,\$fcc4 |
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00000190 <[^>]*> movz\.ps \$f28,\$f30,a1 |
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00000194 <[^>]*> msub\.ps \$f30,\$f0,\$f2,\$f4 |
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00000198 <[^>]*> mul\.ps \$f2,\$f4,\$f6 |
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0000019c <[^>]*> neg\.ps \$f6,\$f8 |
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000001a0 <[^>]*> nmadd\.ps \$f6,\$f8,\$f10,\$f12 |
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000001a4 <[^>]*> nmsub\.ps \$f6,\$f8,\$f10,\$f12 |
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000001a8 <[^>]*> pll\.ps \$f10,\$f12,\$f14 |
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000001ac <[^>]*> plu\.ps \$f14,\$f16,\$f18 |
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000001b0 <[^>]*> pul\.ps \$f16,\$f18,\$f20 |
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000001b4 <[^>]*> puu\.ps \$f20,\$f22,\$f24 |
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000001b8 <[^>]*> sub\.ps \$f22,\$f24,\$f26 |
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000001bc <[^>]*> suxc1 \$f26,a2\(a3\) |
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000001c0 <[^>]*> c\.eq\.ps \$fcc3,\$f10,\$f12 |
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000001c4 <[^>]*> movf\.ps \$f26,\$f28,\$fcc3 |
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000001c8 <[^>]*> clo at,v0 |
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000001cc <[^>]*> clz v1,a0 |
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000001d0 <[^>]*> madd a1,a2 |
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000001d4 <[^>]*> maddu a3,a4 |
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000001d8 <[^>]*> msub a5,a6 |
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000001dc <[^>]*> msubu a7,t0 |
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000001e0 <[^>]*> mul t1,t2,t3 |
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000001e4 <[^>]*> pref 0x4,0\(s0\) |
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000001e8 <[^>]*> pref 0x4,32767\(s1\) |
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000001ec <[^>]*> pref 0x4,-32768\(s2\) |
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000001f0 <[^>]*> ssnop |
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000001f4 <[^>]*> bc2f 00000050 <[^>]*> |
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000001f8 <[^>]*> nop |
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000001fc <[^>]*> bc2fl 00000050 <[^>]*> |
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00000200 <[^>]*> nop |
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00000204 <[^>]*> bc2t 00000050 <[^>]*> |
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00000208 <[^>]*> nop |
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0000020c <[^>]*> bc2tl 00000050 <[^>]*> |
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00000210 <[^>]*> nop |
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00000214 <[^>]*> cfc2 at,\$2 |
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00000218 <[^>]*> c2 0x1234567 |
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0000021c <[^>]*> ctc2 v0,\$3 |
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00000220 <[^>]*> mfc2 v1,\$4 |
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00000224 <[^>]*> mfc2 a0,\$5 |
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00000228 <[^>]*> mfc2 a1,\$6,7 |
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0000022c <[^>]*> mtc2 a2,\$7 |
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00000230 <[^>]*> mtc2 a3,\$8 |
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00000234 <[^>]*> mtc2 a4,\$9,7 |
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00000238 <[^>]*> cache 0x5,0\(at\) |
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0000023c <[^>]*> cache 0x5,32767\(v0\) |
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00000240 <[^>]*> cache 0x5,-32768\(v1\) |
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00000244 <[^>]*> eret |
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00000248 <[^>]*> tlbp |
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0000024c <[^>]*> tlbr |
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00000250 <[^>]*> tlbwi |
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00000254 <[^>]*> tlbwr |
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00000258 <[^>]*> wait |
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0000025c <[^>]*> wait |
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00000260 <[^>]*> wait 0x56789 |
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00000264 <[^>]*> break |
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00000268 <[^>]*> break |
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0000026c <[^>]*> break 0x12345 |
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00000270 <[^>]*> sdbbp |
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00000274 <[^>]*> sdbbp |
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00000278 <[^>]*> sdbbp 0x56789 |
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0000027c <[^>]*> sll zero,zero,0x3 |
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00000280 <[^>]*> 0x7ca43980 |
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00000284 <[^>]*> 0x7ca46984 |
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00000288 <[^>]*> 0x100fc09 |
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0000028c <[^>]*> 0x120a409 |
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00000290 <[^>]*> 0x1000408 |
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00000294 <[^>]*> 0x7c0a003b |
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00000298 <[^>]*> 0x7c0b083b |
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0000029c <[^>]*> 0x7c0c103b |
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000002a0 <[^>]*> 0x7c0d183b |
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000002a4 <[^>]*> 0x7c0e203b |
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000002a8 <[^>]*> 0x7c0f283b |
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000002ac <[^>]*> 0x2acf02 |
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000002b0 <[^>]*> 0x2ac902 |
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000002b4 <[^>]*> negu t9,a0 |
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000002b8 <[^>]*> 0x32ac846 |
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000002bc <[^>]*> 0x8ac846 |
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000002c0 <[^>]*> 0x8ac846 |
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000002c4 <[^>]*> 0x7c073c20 |
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000002c8 <[^>]*> 0x7c0a4420 |
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000002cc <[^>]*> 0x7c073e20 |
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000002d0 <[^>]*> 0x7c0a4620 |
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000002d4 <[^>]*> 0x55f5555 |
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000002d8 <[^>]*> 0x7c0738a0 |
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000002dc <[^>]*> 0x7c0a40a0 |
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000002e0 <[^>]*> 0x41606000 |
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000002e4 <[^>]*> 0x41606000 |
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000002e8 <[^>]*> 0x416a6000 |
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000002ec <[^>]*> 0x41606020 |
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000002f0 <[^>]*> 0x41606020 |
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000002f4 <[^>]*> 0x416a6020 |
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000002f8 <[^>]*> 0x41595000 |
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000002fc <[^>]*> 0x41d95000 |
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00000300 <[^>]*> 0x44710000 |
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00000304 <[^>]*> 0x44f10000 |
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00000308 <[^>]*> 0x48715555 |
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0000030c <[^>]*> 0x48f15555 |
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00000310 <[^>]*> dclo at,v0 |
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00000314 <[^>]*> dclz v1,a0 |
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00000318 <[^>]*> dmfc2 v1,\$4 |
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0000031c <[^>]*> dmfc2 a0,\$5 |
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00000320 <[^>]*> dmfc2 a1,\$6,7 |
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00000324 <[^>]*> dmtc2 a2,\$7 |
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00000328 <[^>]*> dmtc2 a3,\$8 |
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0000032c <[^>]*> dmtc2 a4,\$9,7 |
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00000330 <[^>]*> 0x850029 |
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00000334 <[^>]*> 0xa60028 |
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00000338 <[^>]*> mflo a0 |
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0000033c <[^>]*> 0xa62029 |
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00000340 <[^>]*> 0xa62229 |
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00000344 <[^>]*> 0xa62629 |
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00000348 <[^>]*> 0xa62269 |
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0000034c <[^>]*> 0xa62669 |
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00000350 <[^>]*> 0xa62429 |
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00000354 <[^>]*> 0xa62069 |
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00000358 <[^>]*> 0xa62469 |
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0000035c <[^>]*> mflo a0 |
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00000360 <[^>]*> 0xa62028 |
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00000364 <[^>]*> 0xa62228 |
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00000368 <[^>]*> 0xa62628 |
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0000036c <[^>]*> 0xa62268 |
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00000370 <[^>]*> 0xa62668 |
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00000374 <[^>]*> 0xa62428 |
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00000378 <[^>]*> 0xa62068 |
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0000037c <[^>]*> 0xa62468 |
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00000380 <[^>]*> 0xa62059 |
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00000384 <[^>]*> 0xa62258 |
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00000388 <[^>]*> 0xa62259 |
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0000038c <[^>]*> 0xa620d8 |
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00000390 <[^>]*> 0xa620d9 |
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00000394 <[^>]*> 0xa622d8 |
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00000398 <[^>]*> 0xa622d9 |
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0000039c <[^>]*> 0xa62158 |
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000003a0 <[^>]*> 0xa62159 |
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000003a4 <[^>]*> 0xa62358 |
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000003a8 <[^>]*> 0xa62359 |
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000003ac <[^>]*> 0xa621d8 |
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000003b0 <[^>]*> 0xa621d9 |
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000003b4 <[^>]*> 0xa623d8 |
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000003b8 <[^>]*> 0xa623d9 |
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000003bc <[^>]*> 0x252642 |
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000003c0 <[^>]*> 0xc52046 |
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000003c4 <[^>]*> 0x25267a |
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000003c8 <[^>]*> 0x25267e |
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000003cc <[^>]*> 0x25267e |
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000003d0 <[^>]*> 0xc52056 |
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000003d4 <[^>]*> sdbbp |
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000003d8 <[^>]*> 0x7000003e |
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000003dc <[^>]*> 0x7003183d |
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000003e0 <[^>]*> 0x7083183d |
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000003e4 <[^>]*> mfc0 a0,c0_perfcnt,3 |
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000003e8 <[^>]*> mfc0 a0,c0_perfcnt,2 |
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000003ec <[^>]*> mtc0 a0,c0_perfcnt,3 |
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000003f0 <[^>]*> mtc0 a0,c0_perfcnt,2 |
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000003f4 <[^>]*> c2 0xc4100b |
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000003f8 <[^>]*> 0x4886208b |
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000003fc <[^>]*> c2 0x1cf218b |
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00000400 <[^>]*> c2 0x1df310b |
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00000404 <[^>]*> c2 0xc4100c |
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00000408 <[^>]*> 0x4886208c |
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0000040c <[^>]*> c2 0x1cf218c |
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00000410 <[^>]*> c2 0x1df310c |
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00000414 <[^>]*> c2 0xc20001 |
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00000418 <[^>]*> mtc2 a2,\$4,1 |
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0000041c <[^>]*> c2 0x1cf3001 |
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00000420 <[^>]*> c2 0x1df2001 |
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00000424 <[^>]*> c2 0xc20005 |
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00000428 <[^>]*> mtc2 a2,\$4,5 |
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0000042c <[^>]*> c2 0x1cf3005 |
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00000430 <[^>]*> c2 0x1df2005 |
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00000434 <[^>]*> c2 0xc20004 |
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00000438 <[^>]*> mtc2 a2,\$4,4 |
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0000043c <[^>]*> c2 0x1cf3004 |
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00000440 <[^>]*> c2 0x1df2004 |
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00000444 <[^>]*> c2 0xc41007 |
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00000448 <[^>]*> 0x48862087 |
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0000044c <[^>]*> c2 0x1cf2187 |
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00000450 <[^>]*> c2 0x1df3107 |
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00000454 <[^>]*> c2 0xc41006 |
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00000458 <[^>]*> 0x48862086 |
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0000045c <[^>]*> c2 0x1cf2186 |
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00000460 <[^>]*> c2 0x1df3106 |
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00000464 <[^>]*> c2 0xc41030 |
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00000468 <[^>]*> 0x488620b0 |
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0000046c <[^>]*> c2 0x1cf21b0 |
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00000470 <[^>]*> c2 0x1df3130 |
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00000474 <[^>]*> c2 0xc20033 |
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00000478 <[^>]*> 0x48862033 |
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0000047c <[^>]*> c2 0x1cf3033 |
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00000480 <[^>]*> c2 0x1df2033 |
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00000484 <[^>]*> c2 0xc20433 |
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00000488 <[^>]*> 0x48862433 |
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0000048c <[^>]*> c2 0x1cf3433 |
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00000490 <[^>]*> c2 0x1df2433 |
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00000494 <[^>]*> c2 0xc20032 |
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00000498 <[^>]*> 0x48862032 |
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0000049c <[^>]*> c2 0x1cf3032 |
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000004a0 <[^>]*> c2 0x1df2032 |
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000004a4 <[^>]*> c2 0xc20432 |
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000004a8 <[^>]*> 0x48862432 |
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000004ac <[^>]*> c2 0x1cf3432 |
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000004b0 <[^>]*> c2 0x1df2432 |
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000004b4 <[^>]*> c2 0xc4100f |
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000004b8 <[^>]*> 0x4886208f |
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000004bc <[^>]*> c2 0x1cf218f |
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000004c0 <[^>]*> c2 0x1df310f |
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000004c4 <[^>]*> c2 0xc4100e |
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000004c8 <[^>]*> 0x4886208e |
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000004cc <[^>]*> c2 0x1cf218e |
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000004d0 <[^>]*> c2 0x1df310e |
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000004d4 <[^>]*> c2 0xc41002 |
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000004d8 <[^>]*> 0x48862082 |
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000004dc <[^>]*> c2 0x1cf2182 |
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000004e0 <[^>]*> c2 0x1df3102 |
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000004e4 <[^>]*> c2 0xc41003 |
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000004e8 <[^>]*> 0x48862083 |
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000004ec <[^>]*> c2 0x1cf2183 |
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000004f0 <[^>]*> c2 0x1df3103 |
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000004f4 <[^>]*> c2 0xc4100a |
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000004f8 <[^>]*> 0x4886208a |
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000004fc <[^>]*> c2 0x1cf218a |
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00000500 <[^>]*> c2 0x1df310a |
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00000504 <[^>]*> c2 0xc4100d |
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00000508 <[^>]*> 0x4886208d |
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0000050c <[^>]*> c2 0x1cf218d |
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00000510 <[^>]*> c2 0x1df310d |
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00000514 <[^>]*> 0x48a41018 |
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00000518 <[^>]*> 0x4984101f |
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0000051c <[^>]*> 0x49c4101f |
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00000520 <[^>]*> 0x4904101f |
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00000524 <[^>]*> 0x4944101f |
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00000528 <[^>]*> 0x48c62090 |
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0000052c <[^>]*> c2 0x1ce3110 |
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00000530 <[^>]*> 0x48c62092 |
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00000534 <[^>]*> c2 0x1ce3112 |
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00000538 <[^>]*> c2 0x1cd00a0 |
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0000053c <[^>]*> c2 0xbf |
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00000540 <[^>]*> 0x480000bf |
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00000544 <[^>]*> bc2f 00000844 <[^>]*> |
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00000548 <[^>]*> c2 0x103e |
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0000054c <[^>]*> 0x4804103e |
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00000550 <[^>]*> 0xc52046 |
|||
00000554 <[^>]*> 0x252442 |
|||
00000558 <[^>]*> 0xc52056 |
|||
0000055c <[^>]*> 0x25207e |
|||
00000560 <[^>]*> 0x2520ba |
|||
00000564 <[^>]*> prefx 0x4,a0\(a1\) |
|||
00000568 <[^>]*> wait |
|||
0000056c <[^>]*> wait |
|||
00000570 <[^>]*> wait 0x56789 |
|||
00000574 <[^>]*> ssnop |
|||
00000578 <[^>]*> clo v1,a0 |
|||
0000057c <[^>]*> dclo v1,a0 |
|||
00000580 <[^>]*> clz v1,a0 |
|||
00000584 <[^>]*> dclz v1,a0 |
|||
00000588 <[^>]*> luxc1 \$f0,a0\(v0\) |
|||
0000058c <[^>]*> suxc1 \$f2,a0\(v0\) |
|||
00000590 <[^>]*> tlbp |
|||
00000594 <[^>]*> tlbr |
|||
\.\.\. |
|||
@ -0,0 +1,487 @@ |
|||
.text |
|||
|
|||
.set noreorder |
|||
.set noat |
|||
|
|||
.set arch=4010 |
|||
|
|||
flushi |
|||
flushd |
|||
flushid |
|||
madd $4,$5 |
|||
maddu $5,$6 |
|||
ffc $6,$7 |
|||
ffs $7,$8 |
|||
msub $8,$9 |
|||
msubu $9,$10 |
|||
selsl $10,$11,$12 |
|||
selsr $11,$12,$13 |
|||
waiti |
|||
wb 16($14) |
|||
addciu $14,$15,16 |
|||
|
|||
.set arch=4100 |
|||
|
|||
hibernate |
|||
standby |
|||
suspend |
|||
|
|||
.set arch=4650 |
|||
|
|||
mad $4,$5 |
|||
madu $5,$6 |
|||
mul $6,$7,$8 |
|||
|
|||
# test mips4 instructions. |
|||
|
|||
.set arch=mips4 |
|||
|
|||
text_label: |
|||
bc1f text_label |
|||
bc1f $fcc1,text_label |
|||
bc1fl $fcc1,text_label |
|||
bc1t $fcc1,text_label |
|||
bc1tl $fcc2,text_label |
|||
c.f.d $f4,$f6 |
|||
c.f.d $fcc1,$f4,$f6 |
|||
ldxc1 $f2,$4($5) |
|||
lwxc1 $f2,$4($5) |
|||
madd.d $f0,$f2,$f4,$f6 |
|||
madd.s $f0,$f2,$f4,$f6 |
|||
movf $4,$5,$fcc4 |
|||
movf.d $f4,$f6,$fcc0 |
|||
movf.s $f4,$f6,$fcc0 |
|||
movn $4,$6,$6 |
|||
movn.d $f4,$f6,$6 |
|||
movn.s $f4,$f6,$6 |
|||
movt $4,$5,$fcc4 |
|||
movt.d $f4,$f6,$fcc0 |
|||
movt.s $f4,$f6,$fcc0 |
|||
movz $4,$6,$6 |
|||
movz.d $f4,$f6,$6 |
|||
movz.s $f4,$f6,$6 |
|||
msub.d $f0,$f2,$f4,$f6 |
|||
msub.s $f0,$f2,$f4,$f6 |
|||
nmadd.d $f0,$f2,$f4,$f6 |
|||
nmadd.s $f0,$f2,$f4,$f6 |
|||
nmsub.d $f0,$f2,$f4,$f6 |
|||
nmsub.s $f0,$f2,$f4,$f6 |
|||
|
|||
# We don't test pref because currently the disassembler will |
|||
# disassemble it as lwc3. lwc3 is correct for mips1 to mips3, |
|||
# while pref is correct for mips4. Unfortunately, the |
|||
# disassembler does not know which architecture it is |
|||
# disassembling for. |
|||
# pref 4,0($4) |
|||
|
|||
prefx 4,$4($5) |
|||
recip.d $f4,$f6 |
|||
recip.s $f4,$f6 |
|||
rsqrt.d $f4,$f6 |
|||
rsqrt.s $f4,$f6 |
|||
sdxc1 $f4,$4($5) |
|||
swxc1 $f4,$4($5) |
|||
|
|||
# test mips5 instructions. |
|||
|
|||
.set arch=mips5 |
|||
|
|||
abs.ps $f0, $f2 |
|||
add.ps $f2, $f4, $f6 |
|||
alnv.ps $f6, $f8, $f10, $3 |
|||
c.eq.ps $f8, $f10 |
|||
c.eq.ps $fcc2, $f10, $f12 |
|||
c.f.ps $f8, $f10 |
|||
c.f.ps $fcc2, $f10, $f12 |
|||
c.le.ps $f8, $f10 |
|||
c.le.ps $fcc2, $f10, $f12 |
|||
c.lt.ps $f8, $f10 |
|||
c.lt.ps $fcc2, $f10, $f12 |
|||
c.nge.ps $f8, $f10 |
|||
c.nge.ps $fcc2, $f10, $f12 |
|||
c.ngl.ps $f8, $f10 |
|||
c.ngl.ps $fcc2, $f10, $f12 |
|||
c.ngle.ps $f8, $f10 |
|||
c.ngle.ps $fcc2, $f10, $f12 |
|||
c.ngt.ps $f8, $f10 |
|||
c.ngt.ps $fcc2, $f10, $f12 |
|||
c.ole.ps $f8, $f10 |
|||
c.ole.ps $fcc2, $f10, $f12 |
|||
c.olt.ps $f8, $f10 |
|||
c.olt.ps $fcc2, $f10, $f12 |
|||
c.seq.ps $f8, $f10 |
|||
c.seq.ps $fcc2, $f10, $f12 |
|||
c.sf.ps $f8, $f10 |
|||
c.sf.ps $fcc2, $f10, $f12 |
|||
c.ueq.ps $f8, $f10 |
|||
c.ueq.ps $fcc2, $f10, $f12 |
|||
c.ule.ps $f8, $f10 |
|||
c.ule.ps $fcc2, $f10, $f12 |
|||
c.ult.ps $f8, $f10 |
|||
c.ult.ps $fcc2, $f10, $f12 |
|||
c.un.ps $f8, $f10 |
|||
c.un.ps $fcc2, $f10, $f12 |
|||
cvt.ps.s $f12, $f14, $f16 |
|||
cvt.s.pl $f16, $f18 |
|||
cvt.s.pu $f18, $f20 |
|||
luxc1 $f20, $4($5) |
|||
madd.ps $f20, $f22, $f24, $f26 |
|||
mov.ps $f24, $f26 |
|||
movf.ps $f26, $f28, $fcc2 |
|||
movn.ps $f26, $f28, $3 |
|||
movt.ps $f28, $f30, $fcc4 |
|||
movz.ps $f28, $f30, $5 |
|||
msub.ps $f30, $f0, $f2, $f4 |
|||
mul.ps $f2, $f4, $f6 |
|||
neg.ps $f6, $f8 |
|||
nmadd.ps $f6, $f8, $f10, $f12 |
|||
nmsub.ps $f6, $f8, $f10, $f12 |
|||
pll.ps $f10, $f12, $f14 |
|||
plu.ps $f14, $f16, $f18 |
|||
pul.ps $f16, $f18, $f20 |
|||
puu.ps $f20, $f22, $f24 |
|||
sub.ps $f22, $f24, $f26 |
|||
suxc1 $f26, $6($7) |
|||
|
|||
c.eq.ps $fcc3, $f10, $f12 # warns |
|||
movf.ps $f26, $f28, $fcc3 # warns |
|||
|
|||
# test assembly of mips32 instructions |
|||
|
|||
.set arch=mips32 |
|||
|
|||
# unprivileged CPU instructions |
|||
|
|||
clo $1, $2 |
|||
clz $3, $4 |
|||
madd $5, $6 |
|||
maddu $7, $8 |
|||
msub $9, $10 |
|||
msubu $11, $12 |
|||
mul $13, $14, $15 |
|||
pref 4, ($16) |
|||
pref 4, 32767($17) |
|||
pref 4, -32768($18) |
|||
ssnop |
|||
|
|||
# unprivileged coprocessor instructions. |
|||
# these tests use cp2 to avoid other (cp0, fpu, prefetch) opcodes. |
|||
|
|||
bc2f text_label |
|||
nop |
|||
bc2fl text_label |
|||
nop |
|||
bc2t text_label |
|||
nop |
|||
bc2tl text_label |
|||
nop |
|||
# XXX other BCzCond encodings not currently expressable |
|||
cfc2 $1, $2 |
|||
cop2 0x1234567 # disassembles as c2 ... |
|||
ctc2 $2, $3 |
|||
mfc2 $3, $4 |
|||
mfc2 $4, $5, 0 # disassembles without sel |
|||
mfc2 $5, $6, 7 |
|||
mtc2 $6, $7 |
|||
mtc2 $7, $8, 0 # disassembles without sel |
|||
mtc2 $8, $9, 7 |
|||
|
|||
# privileged instructions |
|||
|
|||
cache 5, ($1) |
|||
cache 5, 32767($2) |
|||
cache 5, -32768($3) |
|||
eret |
|||
tlbp |
|||
tlbr |
|||
tlbwi |
|||
tlbwr |
|||
wait |
|||
wait 0 # disassembles without code |
|||
wait 0x56789 |
|||
|
|||
# Instructions in previous ISAs or CPUs which are now slightly |
|||
# different. |
|||
break |
|||
break 0 # disassembles without code |
|||
break 0x12345 |
|||
sdbbp |
|||
sdbbp 0 # disassembles without code |
|||
sdbbp 0x56789 |
|||
|
|||
# test assembly of mips32r2 instructions |
|||
|
|||
.set arch=mips32r2 |
|||
|
|||
# unprivileged CPU instructions |
|||
|
|||
ehb |
|||
|
|||
ext $4, $5, 6, 8 |
|||
|
|||
ins $4, $5, 6, 8 |
|||
|
|||
jalr.hb $8 |
|||
jalr.hb $20, $9 |
|||
|
|||
jr.hb $8 |
|||
|
|||
# Note, further testing of rdhwr is done in hwr-names-mips32r2.d |
|||
rdhwr $10, $0 |
|||
rdhwr $11, $1 |
|||
rdhwr $12, $2 |
|||
rdhwr $13, $3 |
|||
rdhwr $14, $4 |
|||
rdhwr $15, $5 |
|||
|
|||
# This file checks that in fact HW rotate will |
|||
# be used for this arch, and checks assembly |
|||
# of the official MIPS mnemonics. (Note that disassembly |
|||
# uses the traditional "ror" and "rorv" mnemonics.) |
|||
# Additional rotate tests are done by rol-hw.d. |
|||
rotl $25, $10, 4 |
|||
rotr $25, $10, 4 |
|||
rotl $25, $10, $4 |
|||
rotr $25, $10, $4 |
|||
rotrv $25, $10, $4 |
|||
|
|||
seb $7 |
|||
seb $8, $10 |
|||
|
|||
seh $7 |
|||
seh $8, $10 |
|||
|
|||
synci 0x5555($10) |
|||
|
|||
wsbh $7 |
|||
wsbh $8, $10 |
|||
|
|||
# cp0 instructions |
|||
|
|||
di |
|||
di $0 |
|||
di $10 |
|||
|
|||
ei |
|||
ei $0 |
|||
ei $10 |
|||
|
|||
rdpgpr $10, $25 |
|||
|
|||
wrpgpr $10, $25 |
|||
|
|||
# FPU (cp1) instructions |
|||
# |
|||
# Even registers are supported w/ 32-bit FPU, odd |
|||
# registers supported only for 64-bit FPU. |
|||
# Only the 32-bit FPU instructions are tested here. |
|||
|
|||
mfhc1 $17, $f0 |
|||
mthc1 $17, $f0 |
|||
|
|||
# cp2 instructions |
|||
|
|||
mfhc2 $17, 0x5555 |
|||
mthc2 $17, 0x5555 |
|||
|
|||
.set arch=mips64 |
|||
|
|||
# test assembly of mips64 instructions |
|||
|
|||
# unprivileged CPU instructions |
|||
|
|||
dclo $1, $2 |
|||
dclz $3, $4 |
|||
|
|||
# unprivileged coprocessor instructions. |
|||
# these tests use cp2 to avoid other (cp0, fpu, prefetch) opcodes. |
|||
|
|||
dmfc2 $3, $4 |
|||
dmfc2 $4, $5, 0 # disassembles without sel |
|||
dmfc2 $5, $6, 7 |
|||
dmtc2 $6, $7 |
|||
dmtc2 $7, $8, 0 # disassembles without sel |
|||
dmtc2 $8, $9, 7 |
|||
|
|||
.set arch=vr4111 |
|||
|
|||
dmadd16 $4,$5 |
|||
madd16 $5,$6 |
|||
|
|||
.set arch=vr4120 |
|||
|
|||
# Include mflos to check for nop insertion. |
|||
mflo $4 |
|||
dmacc $4,$5,$6 |
|||
dmacchi $4,$5,$6 |
|||
dmacchis $4,$5,$6 |
|||
dmacchiu $4,$5,$6 |
|||
dmacchius $4,$5,$6 |
|||
dmaccs $4,$5,$6 |
|||
dmaccu $4,$5,$6 |
|||
dmaccus $4,$5,$6 |
|||
mflo $4 |
|||
macc $4,$5,$6 |
|||
macchi $4,$5,$6 |
|||
macchis $4,$5,$6 |
|||
macchiu $4,$5,$6 |
|||
macchius $4,$5,$6 |
|||
maccs $4,$5,$6 |
|||
maccu $4,$5,$6 |
|||
maccus $4,$5,$6 |
|||
|
|||
.set arch=vr5400 |
|||
|
|||
/* Integer instructions. */ |
|||
|
|||
mulu $4,$5,$6 |
|||
mulhi $4,$5,$6 |
|||
mulhiu $4,$5,$6 |
|||
muls $4,$5,$6 |
|||
mulsu $4,$5,$6 |
|||
mulshi $4,$5,$6 |
|||
mulshiu $4,$5,$6 |
|||
macc $4,$5,$6 |
|||
maccu $4,$5,$6 |
|||
macchi $4,$5,$6 |
|||
macchiu $4,$5,$6 |
|||
msac $4,$5,$6 |
|||
msacu $4,$5,$6 |
|||
msachi $4,$5,$6 |
|||
msachiu $4,$5,$6 |
|||
|
|||
ror $4,$5,25 |
|||
rorv $4,$5,$6 |
|||
dror $4,$5,25 |
|||
dror $4,$5,57 /* Should expand to dror32 $4,$5,25. */ |
|||
dror32 $4,$5,25 |
|||
drorv $4,$5,$6 |
|||
|
|||
/* Debug instructions. */ |
|||
|
|||
dbreak |
|||
dret |
|||
mfdr $3,$3 |
|||
mtdr $3,$3 |
|||
|
|||
/* Coprocessor 0 instructions, minus standard ISA 3 ones. |
|||
That leaves just the performance monitoring registers. */ |
|||
|
|||
mfpc $4,1 |
|||
mfps $4,1 |
|||
mtpc $4,1 |
|||
mtps $4,1 |
|||
|
|||
/* Multimedia instructions. */ |
|||
|
|||
.macro nsel2 op |
|||
/* Test each form of each vector opcode. */ |
|||
\op $f0,$f2 |
|||
\op $f4,$f6[2] |
|||
\op $f6,15 |
|||
.if 0 /* Which is right?? */ |
|||
/* Test negative numbers in immediate-value slot. */ |
|||
\op $f4,-3 |
|||
.else |
|||
/* Test that it's recognized as an unsigned field. */ |
|||
\op $f4,31 |
|||
.endif |
|||
.endm |
|||
|
|||
.macro nsel3 op |
|||
/* Test each form of each vector opcode. */ |
|||
\op $f0,$f2,$f4 |
|||
\op $f2,$f4,$f6[2] |
|||
\op $f6,$f4,15 |
|||
.if 0 /* Which is right?? */ |
|||
/* Test negative numbers in immediate-value slot. */ |
|||
\op $f4,$f6,-3 |
|||
.else |
|||
/* Test that it's recognized as an unsigned field. */ |
|||
\op $f4,$f6,31 |
|||
.endif |
|||
.endm |
|||
|
|||
nsel3 add.ob |
|||
nsel3 and.ob |
|||
nsel2 c.eq.ob |
|||
nsel2 c.le.ob |
|||
nsel2 c.lt.ob |
|||
nsel3 max.ob |
|||
nsel3 min.ob |
|||
nsel3 mul.ob |
|||
nsel2 mula.ob |
|||
nsel2 mull.ob |
|||
nsel2 muls.ob |
|||
nsel2 mulsl.ob |
|||
nsel3 nor.ob |
|||
nsel3 or.ob |
|||
nsel3 pickf.ob |
|||
nsel3 pickt.ob |
|||
nsel3 sub.ob |
|||
nsel3 xor.ob |
|||
|
|||
/* ALNI, SHFL: Vector only. */ |
|||
alni.ob $f0,$f2,$f4,5 |
|||
shfl.mixh.ob $f0,$f2,$f4 |
|||
shfl.mixl.ob $f0,$f2,$f4 |
|||
shfl.pach.ob $f0,$f2,$f4 |
|||
shfl.pacl.ob $f0,$f2,$f4 |
|||
|
|||
/* SLL,SRL: Scalar or immediate. */ |
|||
sll.ob $f2,$f4,$f6[3] |
|||
sll.ob $f4,$f6,14 |
|||
srl.ob $f2,$f4,$f6[3] |
|||
srl.ob $f4,$f6,14 |
|||
|
|||
/* RZU: Immediate, must be 0, 8, or 16. */ |
|||
rzu.ob $f2,13 |
|||
|
|||
/* No selector. */ |
|||
rach.ob $f2 |
|||
racl.ob $f2 |
|||
racm.ob $f2 |
|||
wach.ob $f2 |
|||
wacl.ob $f2,$f4 |
|||
|
|||
ror $4,$5,$6 |
|||
rol $4,$5,15 |
|||
dror $4,$5,$6 |
|||
drol $4,$5,31 |
|||
drol $4,$5,62 |
|||
|
|||
.set arch=vr5500 |
|||
|
|||
/* Prefetch instructions. */ |
|||
# We don't test pref because currently the disassembler will |
|||
# disassemble it as lwc3. lwc3 is correct for mips1 to mips3, |
|||
# while pref is correct for mips4. Unfortunately, the |
|||
# disassembler does not know which architecture it is |
|||
# disassembling for. |
|||
# pref 4,0($4) |
|||
|
|||
prefx 4,$4($5) |
|||
|
|||
/* Miscellaneous instructions. */ |
|||
|
|||
wait |
|||
wait 0 # disassembles without code |
|||
wait 0x56789 |
|||
|
|||
ssnop |
|||
|
|||
clo $3,$4 |
|||
dclo $3,$4 |
|||
clz $3,$4 |
|||
dclz $3,$4 |
|||
|
|||
luxc1 $f0,$4($2) |
|||
suxc1 $f2,$4($2) |
|||
|
|||
tlbp |
|||
tlbr |
|||
|
|||
.set arch=default |
|||
|
|||
# make objdump print ... |
|||
.space 8 |
|||
Loading…
Reference in new issue