PR 10186

* arm-dis.c (thumb32_opcodes): Fix binary value of SEV.W
        instruction.

        * gas/arm/thumb32.d: Fix expected binary value of SEV.W instruction.

        * config/tc-arm.c (T16_32_TAB): Fix binary value of SEV.W
        instruction.

gas/ChangeLog

@@ -1,3 +1,9 @@
+2009-06-15  Nick Clifton  <nickc@redhat.com>
+
+	PR 10186
+	* config/tc-arm.c (T16_32_TAB): Fix binary value of SEV.W
+	instruction.
+
 2009-06-13  H.J. Lu  <hongjiu.lu@intel.com>
 
 	PR ld/10269

gas/config/tc-arm.c

@@ -8429,7 +8429,7 @@ encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d)
   X(yield, bf10, f3af8001),			\
   X(wfe,   bf20, f3af8002),			\
   X(wfi,   bf30, f3af8003),			\
-  X(sev,   bf40, f3af9004), /* typo, 8004? */
+  X(sev,   bf40, f3af8004), 
 
 /* To catch errors in encoding functions, the codes are all offset by
    0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined

gas/testsuite/ChangeLog

@@ -1,3 +1,8 @@
+2009-06-15  Nick Clifton  <nickc@redhat.com>
+
+	PR gas/10186
+	* gas/arm/thumb32.d: Fix expected binary value of SEV.W instruction.
+
 2009-06-09  Jakub Jelinek  <jakub@redhat.com>
 
 	PR gas/10255

gas/testsuite/gas/arm/thumb32.d

@@ -359,7 +359,7 @@ Disassembly of section .text:
 0[0-9a-f]+ <[^>]+> f3af 8001 	yield\.w
 0[0-9a-f]+ <[^>]+> f3af 8002 	wfe\.w
 0[0-9a-f]+ <[^>]+> f3af 8003 	wfi\.w
-0[0-9a-f]+ <[^>]+> f3af 9004 	sev\.w
+0[0-9a-f]+ <[^>]+> f3af 8004 	sev\.w
 0[0-9a-f]+ <[^>]+> bf90      	nop	\{9\}
 0[0-9a-f]+ <[^>]+> f3af 8081 	nop\.w	\{129\}
 0[0-9a-f]+ <[^>]+> bf08      	it	eq

opcodes/ChangeLog

@@ -1,5 +1,9 @@
 2009-06-15  Nick Clifton  <nickc@redhat.com>
 
+	PR 10186
+	* arm-dis.c (thumb32_opcodes): Fix binary value of SEV.W
+	instruction.
+
 	PR 10173
 	* cr16-dis.c (print_arg): Avoid printing the 0x prefix twice.
 

opcodes/arm-dis.c

@@ -1245,7 +1245,7 @@ static const struct opcode32 thumb32_opcodes[] =
   {ARM_EXT_V6T2, 0xf3af8001, 0xffffffff, "yield%c.w"},
   {ARM_EXT_V6T2, 0xf3af8002, 0xffffffff, "wfe%c.w"},
   {ARM_EXT_V6T2, 0xf3af8003, 0xffffffff, "wfi%c.w"},
-  {ARM_EXT_V6T2, 0xf3af9004, 0xffffffff, "sev%c.w"},
+  {ARM_EXT_V6T2, 0xf3af8004, 0xffffffff, "sev%c.w"},
   {ARM_EXT_V6T2, 0xf3af8000, 0xffffff00, "nop%c.w\t{%0-7d}"},
 
   {ARM_EXT_V6T2, 0xf3bf8f2f, 0xffffffff, "clrex%c"},