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@ -934,13 +934,15 @@ rrrrr!0,111111,RRRRR + ddddddddddddddd,1:VII:::ld.hu |
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// LDSR |
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regID,111111,RRRRR + 0000000000100000:IX:::ldsr |
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"ldsr r<reg1>, s<regID>" |
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regID,111111,RRRRR + selID,00000100000:IX:::ldsr |
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"ldsr r<reg1>, s<regID>":(selID == 0) |
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"ldsr r<reg1>, s<regID>, <selID>" |
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{ |
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uint32 sreg = GR[reg1]; |
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TRACE_ALU_INPUT1 (GR[reg1]); |
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if ((idecode_issue == idecode_v850e2_issue |
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/* FIXME: For now we ignore the selID. */ |
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if ( (idecode_issue == idecode_v850e2_issue |
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|| idecode_issue == idecode_v850e3v5_issue |
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|| idecode_issue == idecode_v850e2v3_issue) |
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&& regID < 28) |
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