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@ -38,13 +38,12 @@ const char * md_shortopts = ""; /* None yet. */ |
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enum options |
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{ |
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OPTION_MACH_Z80 = OPTION_MD_BASE, |
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OPTION_MARCH = OPTION_MD_BASE, |
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OPTION_MACH_Z80, |
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OPTION_MACH_R800, |
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OPTION_MACH_Z180, |
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OPTION_MACH_EZ80_Z80, |
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OPTION_MACH_EZ80_ADL, |
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OPTION_MACH_GBZ80, |
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OPTION_MACH_Z80N, |
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OPTION_MACH_INST, |
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OPTION_MACH_NO_INST, |
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OPTION_MACH_IUD, |
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@ -83,13 +82,12 @@ enum options |
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struct option md_longopts[] = |
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{ |
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{ "march", required_argument, NULL, OPTION_MARCH}, |
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{ "z80", no_argument, NULL, OPTION_MACH_Z80}, |
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{ "r800", no_argument, NULL, OPTION_MACH_R800}, |
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{ "z180", no_argument, NULL, OPTION_MACH_Z180}, |
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{ "ez80", no_argument, NULL, OPTION_MACH_EZ80_Z80}, |
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{ "ez80-adl", no_argument, NULL, OPTION_MACH_EZ80_ADL}, |
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{ "gbz80", no_argument, NULL, OPTION_MACH_GBZ80}, |
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{ "z80n", no_argument, NULL, OPTION_MACH_Z80N}, |
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{ "fp-s", required_argument, NULL, OPTION_FP_SINGLE_FORMAT}, |
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{ "fp-d", required_argument, NULL, OPTION_FP_DOUBLE_FORMAT}, |
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{ "strict", no_argument, NULL, OPTION_MACH_FUD}, |
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@ -145,6 +143,83 @@ static str_to_float_t str_to_double; |
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#define INST_MODE_FORCED 4 /* CPU mode changed by instruction suffix*/ |
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static char inst_mode; |
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struct match_info |
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{ |
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const char *name; |
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int ins_ok; |
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int ins_err; |
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int cpu_mode; |
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const char *comment; |
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}; |
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static const struct match_info |
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match_cpu_table [] = |
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{ |
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{"z80", INS_Z80, 0, 0, "Zilog Z80 (+infc+xyhl)" }, |
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{"ez80", INS_EZ80, 0, 0, "Zilog eZ80" }, |
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{"gbz80", INS_GBZ80, INS_UNDOC|INS_UNPORT, 0, "GameBoy Z80" }, |
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{"r800", INS_R800, INS_UNPORT, 0, "Ascii R800" }, |
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{"z180", INS_Z180, INS_UNDOC|INS_UNPORT, 0, "Zilog Z180" }, |
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{"z80n", INS_Z80N, 0, 0, "Z80 Next" } |
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}; |
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static const struct match_info |
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match_ext_table [] = |
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{ |
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{"full", INS_UNDOC|INS_UNPORT, 0, 0, "assemble all known instructions" }, |
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{"adl", 0, 0, 1, "eZ80 ADL mode by default" }, |
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{"xyhl", INS_IDX_HALF, 0, 0, "instructions with halves of index registers" }, |
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{"infc", INS_IN_F_C, 0, 0, "instruction IN F,(C)" }, |
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{"outc0", INS_OUT_C_0, 0, 0, "instruction OUT (C),0" }, |
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{"sli", INS_SLI, 0, 0, "instruction known as SLI, SLL, or SL1" }, |
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{"xdcb", INS_ROT_II_LD, 0, 0, "instructions like RL (IX+d),R (DD/FD CB dd oo)" } |
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}; |
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static void |
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setup_march (const char *name, int *ok, int *err, int *mode) |
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{ |
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unsigned i; |
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size_t len = strcspn (name, "+-"); |
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for (i = 0; i < ARRAY_SIZE (match_cpu_table); ++i) |
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if (!strncasecmp (name, match_cpu_table[i].name, len) |
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&& strlen (match_cpu_table[i].name) == len) |
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{ |
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*ok = match_cpu_table[i].ins_ok; |
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*err = match_cpu_table[i].ins_err; |
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*mode = match_cpu_table[i].cpu_mode; |
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break; |
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} |
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if (i >= ARRAY_SIZE (match_cpu_table)) |
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as_fatal (_("Invalid CPU is specified: %s"), name); |
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while (name[len]) |
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{ |
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name = &name[len + 1]; |
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len = strcspn (name, "+-"); |
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for (i = 0; i < ARRAY_SIZE (match_ext_table); ++i) |
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if (!strncasecmp (name, match_ext_table[i].name, len) |
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&& strlen (match_ext_table[i].name) == len) |
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{ |
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if (name[-1] == '+') |
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{ |
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*ok |= match_ext_table[i].ins_ok; |
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*err &= ~match_ext_table[i].ins_ok; |
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*mode |= match_ext_table[i].cpu_mode; |
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} |
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else |
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{ |
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*ok &= ~match_ext_table[i].ins_ok; |
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*err |= match_ext_table[i].ins_ok; |
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*mode &= ~match_ext_table[i].cpu_mode; |
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} |
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break; |
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} |
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if (i >= ARRAY_SIZE (match_ext_table)) |
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as_fatal (_("Invalid EXTENTION is specified: %s"), name); |
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} |
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} |
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static int |
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setup_instruction (const char *inst, int *add, int *sub) |
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{ |
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@ -243,35 +318,23 @@ md_parse_option (int c, const char* arg) |
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{ |
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default: |
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return 0; |
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case OPTION_MARCH: |
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setup_march (arg, & ins_ok, & ins_err, & cpu_mode); |
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break; |
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case OPTION_MACH_Z80: |
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ins_ok = (ins_ok & INS_TUNE_MASK) | INS_Z80; |
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ins_err = (ins_err & INS_MARCH_MASK) | (~INS_Z80 & INS_MARCH_MASK); |
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setup_march ("z80", & ins_ok, & ins_err, & cpu_mode); |
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break; |
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case OPTION_MACH_R800: |
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ins_ok = INS_R800 | INS_IDX_HALF | INS_IN_F_C; |
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ins_err = INS_UNPORT; |
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setup_march ("r800", & ins_ok, & ins_err, & cpu_mode); |
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break; |
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case OPTION_MACH_Z180: |
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ins_ok = INS_Z180; |
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ins_err = INS_UNDOC | INS_UNPORT; |
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setup_march ("z180", & ins_ok, & ins_err, & cpu_mode); |
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break; |
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case OPTION_MACH_EZ80_Z80: |
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ins_ok = INS_EZ80 | INS_IDX_HALF; |
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ins_err = (INS_UNDOC | INS_UNPORT) & ~INS_IDX_HALF; |
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cpu_mode = 0; |
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setup_march ("ez80", & ins_ok, & ins_err, & cpu_mode); |
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break; |
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case OPTION_MACH_EZ80_ADL: |
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ins_ok = INS_EZ80 | INS_IDX_HALF; |
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ins_err = (INS_UNDOC | INS_UNPORT) & ~INS_IDX_HALF; |
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cpu_mode = 1; |
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break; |
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case OPTION_MACH_GBZ80: |
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ins_ok = INS_GBZ80; |
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ins_err = INS_UNDOC | INS_UNPORT; |
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break; |
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case OPTION_MACH_Z80N: |
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ins_ok = INS_Z80N | INS_UNPORT | INS_UNDOC; |
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ins_err = 0; |
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setup_march ("ez80+adl", & ins_ok, & ins_err, & cpu_mode); |
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break; |
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case OPTION_FP_SINGLE_FORMAT: |
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str_to_float = get_str_to_float (arg); |
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@ -319,7 +382,6 @@ md_parse_option (int c, const char* arg) |
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break; |
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case OPTION_COMPAT_SDCC: |
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sdcc_compat = 1; |
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local_label_prefix = "_"; |
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break; |
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case OPTION_COMPAT_COLONLESS: |
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colonless_labels = 1; |
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@ -332,16 +394,17 @@ md_parse_option (int c, const char* arg) |
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void |
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md_show_usage (FILE * f) |
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{ |
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fprintf (f, "\n\
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unsigned i; |
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fprintf (f, _("\n\
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CPU model options:\n\ |
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-z80\t\t\t assemble for Zilog Z80\n\ |
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-r800\t\t\t assemble for Ascii R800\n\ |
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-z180\t\t\t assemble for Zilog Z180\n\ |
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-ez80\t\t\t assemble for Zilog eZ80 in Z80 mode by default\n\ |
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-ez80-adl\t\t assemble for Zilog eZ80 in ADL mode by default\n\ |
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-gbz80\t\t assemble for GameBoy Z80\n\ |
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-z80n\t\t\t assemble for Z80N\n\ |
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\n\ |
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-march=CPU[+EXT...][-EXT...]\n\ |
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\t\t\t generate code for CPU, where CPU is one of:\n")); |
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for (i = 0; i < ARRAY_SIZE(match_cpu_table); ++i) |
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fprintf (f, " %-8s\t\t %s\n", match_cpu_table[i].name, match_cpu_table[i].comment); |
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fprintf (f, _("And EXT is combination (+EXT - add, -EXT - remove) of:\n")); |
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for (i = 0; i < ARRAY_SIZE(match_ext_table); ++i) |
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fprintf (f, " %-8s\t\t %s\n", match_ext_table[i].name, match_ext_table[i].comment); |
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fprintf (f, _("\n\
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Compatibility options:\n\ |
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-local-prefix=TEXT\t treat labels prefixed by TEXT as local\n\ |
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-colonless\t\t permit colonless labels\n\ |
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@ -349,42 +412,14 @@ Compatibility options:\n\ |
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-fp-s=FORMAT\t\t set single precission FP numbers format\n\ |
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-fp-d=FORMAT\t\t set double precission FP numbers format\n\ |
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Where FORMAT one of:\n\ |
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ieee754\t\t IEEE754 compatible\n\ |
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ieee754\t\t IEEE754 compatible (depends on directive)\n\ |
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half\t\t\t IEEE754 half precision (16 bit)\n\ |
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single\t\t IEEE754 single precision (32 bit)\n\ |
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double\t\t IEEE754 double precision (64 bit)\n\ |
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zeda32\t\t Zeda z80float library 32 bit format\n\ |
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math48\t\t 48 bit format from Math48 library\n\ |
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\n\ |
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Support for known undocumented instructions:\n\ |
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-strict\t\t assemble only documented instructions\n\ |
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-full\t\t\t assemble all undocumented instructions\n\ |
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-with-inst=INST[,...]\n\ |
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-Wnins INST[,...]\t assemble specified instruction(s)\n\ |
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-without-inst=INST[,...]\n\ |
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-Fins INST[,...]\t do not assemble specified instruction(s)\n\ |
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Where INST is one of:\n\ |
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idx-reg-halves\t instructions with halves of index registers\n\ |
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sli\t\t\t instruction SLI/SLL\n\ |
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op-ii-ld\t\t instructions like SLA (II+dd),R (opcodes DD/FD CB dd xx)\n\ |
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in-f-c\t\t instruction IN F,(C)\n\ |
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out-c-0\t\t instruction OUT (C),0\n\ |
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\n\ |
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Obsolete options:\n\ |
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-ignore-undocumented-instructions\n\ |
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-Wnud\t\t\t silently assemble undocumented Z80-instructions that work on R800\n\ |
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-ignore-unportable-instructions\n\ |
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-Wnup\t\t\t silently assemble all undocumented Z80-instructions\n\ |
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-warn-undocumented-instructions\n\ |
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-Wud\t\t\t issue warnings for undocumented Z80-instructions that work on R800\n\ |
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-warn-unportable-instructions\n\ |
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-Wup\t\t\t issue warnings for other undocumented Z80-instructions\n\ |
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-forbid-undocumented-instructions\n\ |
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-Fud\t\t\t treat all undocumented Z80-instructions as errors\n\ |
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-forbid-unportable-instructions\n\ |
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-Fup\t\t\t treat undocumented Z80-instructions that do not work on R800 as errors\n\ |
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\n\ |
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Default: -z80 -ignore-undocumented-instructions -warn-unportable-instructions.\n"); |
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Default: -march=z80+xyhl+infc\n")); |
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} |
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static symbolS * zero; |
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@ -499,12 +534,7 @@ z80_md_end (void) |
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switch (ins_ok & INS_MARCH_MASK) |
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{ |
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case INS_Z80: |
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if (ins_ok & INS_UNPORT) |
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mach_type = bfd_mach_z80full; |
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else if (ins_ok & INS_UNDOC) |
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mach_type = bfd_mach_z80; |
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else |
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mach_type = bfd_mach_z80strict; |
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mach_type = bfd_mach_z80; |
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break; |
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case INS_R800: |
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mach_type = bfd_mach_r800; |
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@ -524,40 +554,17 @@ z80_md_end (void) |
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default: |
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mach_type = 0; |
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} |
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bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach_type); |
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} |
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#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
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void |
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z80_elf_final_processing (void) |
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{ |
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{/* nothing to do, all is done by BFD itself */ |
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/*
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unsigned elf_flags; |
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switch (ins_ok & INS_MARCH_MASK) |
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{ |
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case INS_Z80: |
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elf_flags = EF_Z80_MACH_Z80; |
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break; |
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case INS_R800: |
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elf_flags = EF_Z80_MACH_R800; |
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break; |
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case INS_Z180: |
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elf_flags = EF_Z80_MACH_Z180; |
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break; |
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case INS_GBZ80: |
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elf_flags = EF_Z80_MACH_GBZ80; |
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break; |
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case INS_EZ80: |
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elf_flags = cpu_mode ? EF_Z80_MACH_EZ80_ADL : EF_Z80_MACH_EZ80_Z80; |
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break; |
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case INS_Z80N: |
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elf_flags = EF_Z80_MACH_Z80N; |
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break; |
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default: |
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elf_flags = 0; |
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} |
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elf_elfheader (stdoutput)->e_flags = elf_flags; |
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*/ |
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} |
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#endif |
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@ -631,8 +638,6 @@ z80_start_line_hook (void) |
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} |
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c = ':'; |
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} |
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if (c == ':' && sdcc_compat && rest[-2] != '$') |
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dollar_label_clear (); |
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if (*rest == ':') |
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{ |
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/* remove second colon if SDCC compatibility enabled */ |
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@ -1222,7 +1227,7 @@ emit_mx (char prefix, char opcode, int shift, expressionS * arg) |
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if ((prefix == 0) && (rnum & R_INDEX)) |
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{ |
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prefix = (rnum & R_IX) ? 0xDD : 0xFD; |
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if (!(ins_ok & INS_EZ80)) |
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if (!(ins_ok & (INS_EZ80|INS_R800|INS_Z80N))) |
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check_mach (INS_IDX_HALF); |
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rnum &= ~R_INDEX; |
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} |
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@ -1312,7 +1317,8 @@ emit_mr (char prefix, char opcode, const char *args) |
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ill_op (); |
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break; |
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} |
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check_mach (INS_ROT_II_LD); |
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if (!(ins_ok & INS_Z80N)) |
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check_mach (INS_ROT_II_LD); |
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} |
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/* Fall through. */ |
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case O_register: |
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@ -1926,7 +1932,7 @@ emit_in (char prefix ATTRIBUTE_UNUSED, char opcode ATTRIBUTE_UNUSED, |
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{ |
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if (port.X_add_number == REG_BC && !(ins_ok & INS_EZ80)) |
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ill_op (); |
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else if (reg.X_add_number == REG_F && !(ins_ok & INS_R800)) |
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else if (reg.X_add_number == REG_F && !(ins_ok & (INS_R800|INS_Z80N))) |
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check_mach (INS_IN_F_C); |
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q = frag_more (2); |
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*q++ = 0xED; |
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@ -1994,7 +2000,8 @@ emit_out (char prefix ATTRIBUTE_UNUSED, char opcode ATTRIBUTE_UNUSED, |
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/* Allow "out (c), 0" as unportable instruction. */ |
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if (reg.X_op == O_constant && reg.X_add_number == 0) |
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{ |
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check_mach (INS_OUT_C_0); |
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if (!(ins_ok & INS_Z80N)) |
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check_mach (INS_OUT_C_0); |
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reg.X_op = O_register; |
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reg.X_add_number = 6; |
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} |
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@ -2368,7 +2375,7 @@ emit_ld_r_n (expressionS *dst, expressionS *src) |
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{ |
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if (ins_ok & INS_GBZ80) |
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ill_op (); |
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else if (!(ins_ok & INS_EZ80)) |
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else if (!(ins_ok & (INS_EZ80|INS_R800|INS_Z80N))) |
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check_mach (INS_IDX_HALF); |
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*q++ = prefix; |
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} |
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@ -2529,7 +2536,7 @@ emit_ld_r_r (expressionS *dst, expressionS *src) |
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} |
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if ((ins_ok & INS_GBZ80) && prefix != 0) |
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ill_op (); |
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if (ii_halves && !(ins_ok & INS_EZ80)) |
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if (ii_halves && !(ins_ok & (INS_EZ80|INS_R800|INS_Z80N))) |
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check_mach (INS_IDX_HALF); |
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if (prefix == 0 && (ins_ok & INS_EZ80)) |
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{ |
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@ -3545,10 +3552,10 @@ static table_t instab[] = |
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{ "scf", 0x00, 0x37, emit_insn, INS_ALL }, |
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{ "set", 0xCB, 0xC0, emit_bit, INS_ALL }, |
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{ "setae",0xED, 0x95, emit_insn, INS_Z80N }, |
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{ "sl1", 0xCB, 0x30, emit_mr, INS_SLI }, |
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{ "sl1", 0xCB, 0x30, emit_mr, INS_SLI|INS_Z80N }, |
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{ "sla", 0xCB, 0x20, emit_mr, INS_ALL }, |
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{ "sli", 0xCB, 0x30, emit_mr, INS_SLI }, |
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{ "sll", 0xCB, 0x30, emit_mr, INS_SLI }, |
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{ "sli", 0xCB, 0x30, emit_mr, INS_SLI|INS_Z80N }, |
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{ "sll", 0xCB, 0x30, emit_mr, INS_SLI|INS_Z80N }, |
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{ "slp", 0xED, 0x76, emit_insn, INS_Z180|INS_EZ80 }, |
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{ "sra", 0xCB, 0x28, emit_mr, INS_ALL }, |
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{ "srl", 0xCB, 0x38, emit_mr, INS_ALL }, |
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Sergey Belyashov
7 years ago
Nick Clifton