Keep reserved bits in CPSR on write

In patch https://sourceware.org/ml/gdb-patches/2016-04/msg00529.html
I cleared reserved bits when reading CPSR.  It makes a problem that
these bits (zero) are written back to kernel through ptrace, and it
changes the state of the processor on some recent kernel, which is
unexpected.

In this patch, I keep these reserved bits when write CPSR back to
hardware.

gdb:

2016-09-21  Yao Qi  <yao.qi@linaro.org>

	* aarch32-linux-nat.c (aarch32_gp_regcache_collect): Keep
	bits 20 to 23.

gdb/gdbserver:

2016-09-21  Yao Qi  <yao.qi@linaro.org>

	* linux-aarch32-low.c (arm_fill_gregset): Keep bits 20 to
	23.

gdb/ChangeLog

@@ -1,3 +1,8 @@
+2016-09-21  Yao Qi  <yao.qi@linaro.org>
+
+	* aarch32-linux-nat.c (aarch32_gp_regcache_collect): Keep
+	bits 20 to 23.
+
 2016-09-20  Tom Tromey  <tom@tromey.com>
 
 	* python/py-value.c (convert_value_from_python): Make PyInt_Check

gdb/aarch32-linux-nat.c

@@ -67,8 +67,15 @@ aarch32_gp_regcache_collect (const struct regcache *regcache, uint32_t *regs,
 
   if (arm_apcs_32
       && REG_VALID == regcache_register_status (regcache, ARM_PS_REGNUM))
-    regcache_raw_collect (regcache, ARM_PS_REGNUM,
-			  &regs[ARM_CPSR_GREGNUM]);
+    {
+      uint32_t cpsr = regs[ARM_CPSR_GREGNUM];
+
+      regcache_raw_collect (regcache, ARM_PS_REGNUM,
+			    &regs[ARM_CPSR_GREGNUM]);
+      /* Keep reserved bits bit 20 to bit 23.  */
+      regs[ARM_CPSR_GREGNUM] = ((regs[ARM_CPSR_GREGNUM] & 0xff0fffff)
+				| (cpsr & 0x00f00000));
+    }
 }
 
 /* Supply VFP registers contents, stored in REGS, to REGCACHE.

gdb/gdbserver/ChangeLog

@@ -1,3 +1,8 @@
+2016-09-21  Yao Qi  <yao.qi@linaro.org>
+
+	* linux-aarch32-low.c (arm_fill_gregset): Keep bits 20 to
+	23.
+
 2016-09-19  Sergio Durigan Junior  <sergiodj@redhat.com>
 
 	* server.c (start_inferior): Call target_mourn_inferior instead of

gdb/gdbserver/linux-aarch32-low.c

@@ -62,11 +62,15 @@ arm_fill_gregset (struct regcache *regcache, void *buf)
 {
   int i;
   uint32_t *regs = (uint32_t *) buf;
+  uint32_t cpsr = regs[ARM_CPSR_GREGNUM];
 
   for (i = ARM_A1_REGNUM; i <= ARM_PC_REGNUM; i++)
     collect_register (regcache, i, &regs[i]);
 
   collect_register (regcache, ARM_PS_REGNUM, &regs[ARM_CPSR_GREGNUM]);
+  /* Keep reserved bits bit 20 to bit 23.  */
+  regs[ARM_CPSR_GREGNUM] = ((regs[ARM_CPSR_GREGNUM] & 0xff0fffff)
+			    | (cpsr & 0x00f00000));
 }
 
 /* Supply GP registers contents, stored in BUF, to REGCACHE.  */