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Add big-endian support for tilegx. 

bfd/
	* config.bfd (tilegx-*-*): rename little endian vector; add big
	endian vector.
	(tilegxbe-*-*): New case.
	* configure.in (bfd_elf32_tilegx_vec): Rename...
	(bfd_elf32_tilegx_le_vec): ... to this.
	(bfd_elf32_tilegx_be_vec): New vector.
	(bfd_elf64_tilegx_vec): Rename...
	(bfd_elf64_tilegx_le_vec): ... to this.
	(bfd_elf64_tilegx_be_vec): New vector.
	* configure: Regenerate.
	* elf32-tilegx.c (TARGET_LITTLE_SYM): Rename.
	(TARGET_LITTLE_NAME): Ditto.
	(TARGET_BIG_SYM): Define.
	(TARGET_BIG_NAME): Define.
	* elf64-tilegx.c (TARGET_LITTLE_SYM): Rename.
	(TARGET_LITTLE_NAME): Ditto.
	(TARGET_BIG_SYM): Define.
	(TARGET_BIG_NAME): Define.
	* targets.c (bfd_elf32_tilegx_vec): Rename...
	(bfd_elf32_tilegx_le_vec): ... to this.
	(bfd_elf32_tilegx_be_vec): Declare.
	(bfd_elf64_tilegx_vec): Rename...
	(bfd_elf64_tilegx_le_vec): ... to this.
	(bfd_elf64_tilegx_be_vec): Declare.
	(_bfd_target_vector): Add / rename above vectors.

binutils/testsuite/
	* binutils-all/objdump.exp (cpus_expected): Add tilegx.

gas/
	* tc-tilegx.c (tilegx_target_format): Handle big endian.
	(OPTION_EB): Define.
	(OPTION_EL): Define.
	(md_longopts): Add entries for "EB" and "EL".
	(md_parse_option): Handle OPTION_EB and OPTION_EL.
	(md_show_usage): Add -EB and -EL.
	(md_number_to_chars): New.
	* tc-tilegx.h (TARGET_BYTES_BIG_ENDIAN): Guard definition with
	ifndef.
	(md_number_to_chars): Delete.
	* configure.tgt (tilegx*be): Handle.
	* doc/as.texinfo [TILE-Gx]: Document -EB and -EL.
	* doc/c-tilegx.texi: Ditto.

ld/
	* Makefile.am (ALL_EMULATION_SOURCES): Add eelf32tilegx_be.c.
	(ALL_64_EMULATION_SOURCES): Add eelf64tilegx_be.c.
	(eelf32tilegx_be.c): Add rule to build this file.
	(eelf64tilegx_be.c): Ditto.
	* Makefile.in: Regenerate.
	* configure.tgt (tilegx-*-*): Support big endian.
	(tilegxbe-*-*): New.
	* emulparams/elf32tilegx.sh (OUTPUT_FORMAT): Rename.
	(BIG_OUTPUT_FORMAT): Define.
	(LITTLE_OUTPUT_FORMAT): Define.
	* emulparams/elf32tilegx_be.sh: New.
	* emulparams/elf64tilegx.sh (OUTPUT_FORMAT): Rename.
	(BIG_OUTPUT_FORMAT): Define.
	(LITTLE_OUTPUT_FORMAT): Define.
	* emulparams/elf64tilegx_be.sh: New.

ld/testsuite/
	* ld-tilegx/reloc-be.d: New.
	* ld-tilegx/reloc-le.d: New.
	* ld-tilegx/reloc.d: Delete.
	* ld-tilegx/tilegx.exp: Test big and little endian.
cygwin-64bit-branch
Walter Lee 14 years ago
parent
825902491e
commit
fb6ceddedd
27 changed files with 260 additions and 33 deletions
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  1. 27
      bfd/ChangeLog
  2. 8
      bfd/config.bfd
  3. 6
      bfd/configure
  4. 6
      bfd/configure.in
  5. 6
      bfd/elf32-tilegx.c
  6. 7
      bfd/elf64-tilegx.c
  7. 12
      bfd/targets.c
  8. 4
      binutils/testsuite/ChangeLog
  9. 4
      binutils/testsuite/binutils-all/objdump.exp
  10. 15
      gas/ChangeLog
  11. 28
      gas/config/tc-tilegx.c
  12. 4
      gas/config/tc-tilegx.h
  13. 4
      gas/configure.tgt
  14. 2
      gas/doc/as.texinfo
  15. 5
      gas/doc/c-tilegx.texi
  16. 18
      ld/ChangeLog
  17. 10
      ld/Makefile.am
  18. 12
      ld/Makefile.in
  19. 5
      ld/configure.tgt
  20. 4
      ld/emulparams/elf32tilegx.sh
  21. 2
      ld/emulparams/elf32tilegx_be.sh
  22. 4
      ld/emulparams/elf64tilegx.sh
  23. 2
      ld/emulparams/elf64tilegx_be.sh
  24. 7
      ld/testsuite/ChangeLog
  25. 70
      ld/testsuite/ld-tilegx/reloc-be.d
  26. 2
      ld/testsuite/ld-tilegx/reloc-le.d
  27. 19
      ld/testsuite/ld-tilegx/tilegx.exp

27
bfd/ChangeLog
View File

@ -1,9 +1,34 @@
2012-02-25 Walter Lee <walt@tilera.com>
* config.bfd (tilegx-*-*): rename little endian vector; add big
endian vector.
(tilegxbe-*-*): New case.
* configure.in (bfd_elf32_tilegx_vec): Rename...
(bfd_elf32_tilegx_le_vec): ... to this.
(bfd_elf32_tilegx_be_vec): New vector.
(bfd_elf64_tilegx_vec): Rename...
(bfd_elf64_tilegx_le_vec): ... to this.
(bfd_elf64_tilegx_be_vec): New vector.
* configure: Regenerate.
* elf32-tilegx.c (TARGET_LITTLE_SYM): Rename.
(TARGET_LITTLE_NAME): Ditto.
(TARGET_BIG_SYM): Define.
(TARGET_BIG_NAME): Define.
* elf64-tilegx.c (TARGET_LITTLE_SYM): Rename.
(TARGET_LITTLE_NAME): Ditto.
(TARGET_BIG_SYM): Define.
(TARGET_BIG_NAME): Define.
* targets.c (bfd_elf32_tilegx_vec): Rename...
(bfd_elf32_tilegx_le_vec): ... to this.
(bfd_elf32_tilegx_be_vec): Declare.
(bfd_elf64_tilegx_vec): Rename...
(bfd_elf64_tilegx_le_vec): ... to this.
(bfd_elf64_tilegx_be_vec): Declare.
(_bfd_target_vector): Add / rename above vectors.
* arctures.c (bfd_architecture): Define bfd_mach_tilegx32.
* bfd-in2.h: Regenerate.
* cpu-tilegx.c (bfd_tilegx32_arch): define.
(bfd_tilegx_arch): link to bfd_tilegx32_arch.
(bfd_tilegx_arch): link to bfd_tilegx32_arch.
2012-02-24 Nick Clifton <nickc@redhat.com>

8
bfd/config.bfd
View File

@ -1507,8 +1507,12 @@ case "${targ}" in
#ifdef BFD64
tilegx-*-*)
targ_defvec=bfd_elf64_tilegx_vec
targ_selvecs=bfd_elf32_tilegx_vec
targ_defvec=bfd_elf64_tilegx_le_vec
targ_selvecs="bfd_elf64_tilegx_be_vec bfd_elf32_tilegx_be_vec bfd_elf32_tilegx_le_vec"
;;
tilegxbe-*-*)
targ_defvec=bfd_elf64_tilegx_be_vec
targ_selvecs="bfd_elf64_tilegx_le_vec bfd_elf32_tilegx_be_vec bfd_elf32_tilegx_le_vec"
;;
#endif

6
bfd/configure
View File

@ -15302,7 +15302,8 @@ do
bfd_elf32_tic6x_linux_le_vec) tb="$tb elf32-tic6x.lo elf32.lo $elf" ;;
bfd_elf32_tic6x_elf_be_vec) tb="$tb elf32-tic6x.lo elf32.lo $elf" ;;
bfd_elf32_tic6x_elf_le_vec) tb="$tb elf32-tic6x.lo elf32.lo $elf" ;;
bfd_elf32_tilegx_vec) tb="$tb elf32-tilegx.lo elfxx-tilegx.lo elf32.lo $elf" ; target_size=32 ;;
bfd_elf32_tilegx_be_vec) tb="$tb elf32-tilegx.lo elfxx-tilegx.lo elf32.lo $elf" ; target_size=32 ;;
bfd_elf32_tilegx_le_vec) tb="$tb elf32-tilegx.lo elfxx-tilegx.lo elf32.lo $elf" ; target_size=32 ;;
bfd_elf32_tilepro_vec) tb="$tb elf32-tilepro.lo elf32.lo $elf" ;;
bfd_elf32_tradbigmips_vec | bfd_elf32_tradbigmips_freebsd_vec)
tb="$tb elf32-mips.lo elfxx-mips.lo elf-vxworks.lo elf32.lo $elf ecofflink.lo" ;;
@ -15341,7 +15342,8 @@ do
bfd_elf64_sparc_vec) tb="$tb elf64-sparc.lo elfxx-sparc.lo elf-vxworks.lo elf64.lo $elf"; target_size=64 ;;
bfd_elf64_sparc_freebsd_vec) tb="$tb elf64-sparc.lo elfxx-sparc.lo elf-vxworks.lo elf64.lo $elf"; target_size=64 ;;
bfd_elf64_sparc_sol2_vec) tb="$tb elf64-sparc.lo elfxx-sparc.lo elf-vxworks.lo elf64.lo $elf"; target_size=64 ;;
bfd_elf64_tilegx_vec) tb="$tb elf64-tilegx.lo elfxx-tilegx.lo elf64.lo $elf" ; target_size=64 ;;
bfd_elf64_tilegx_be_vec) tb="$tb elf64-tilegx.lo elfxx-tilegx.lo elf64.lo $elf" ; target_size=64 ;;
bfd_elf64_tilegx_le_vec) tb="$tb elf64-tilegx.lo elfxx-tilegx.lo elf64.lo $elf" ; target_size=64 ;;
bfd_elf64_tradbigmips_vec | bfd_elf64_tradbigmips_freebsd_vec)
tb="$tb elf64-mips.lo elf64.lo elfxx-mips.lo elf-vxworks.lo elf32.lo $elf ecofflink.lo"; target_size=64 ;;
bfd_elf64_tradlittlemips_vec | bfd_elf64_tradlittlemips_freebsd_vec)

6
bfd/configure.in
View File

@ -801,7 +801,8 @@ do
bfd_elf32_tic6x_linux_le_vec) tb="$tb elf32-tic6x.lo elf32.lo $elf" ;;
bfd_elf32_tic6x_elf_be_vec) tb="$tb elf32-tic6x.lo elf32.lo $elf" ;;
bfd_elf32_tic6x_elf_le_vec) tb="$tb elf32-tic6x.lo elf32.lo $elf" ;;
bfd_elf32_tilegx_vec) tb="$tb elf32-tilegx.lo elfxx-tilegx.lo elf32.lo $elf" ; target_size=32 ;;
bfd_elf32_tilegx_be_vec) tb="$tb elf32-tilegx.lo elfxx-tilegx.lo elf32.lo $elf" ; target_size=32 ;;
bfd_elf32_tilegx_le_vec) tb="$tb elf32-tilegx.lo elfxx-tilegx.lo elf32.lo $elf" ; target_size=32 ;;
bfd_elf32_tilepro_vec) tb="$tb elf32-tilepro.lo elf32.lo $elf" ;;
bfd_elf32_tradbigmips_vec | bfd_elf32_tradbigmips_freebsd_vec)
tb="$tb elf32-mips.lo elfxx-mips.lo elf-vxworks.lo elf32.lo $elf ecofflink.lo" ;;
@ -840,7 +841,8 @@ do
bfd_elf64_sparc_vec) tb="$tb elf64-sparc.lo elfxx-sparc.lo elf-vxworks.lo elf64.lo $elf"; target_size=64 ;;
bfd_elf64_sparc_freebsd_vec) tb="$tb elf64-sparc.lo elfxx-sparc.lo elf-vxworks.lo elf64.lo $elf"; target_size=64 ;;
bfd_elf64_sparc_sol2_vec) tb="$tb elf64-sparc.lo elfxx-sparc.lo elf-vxworks.lo elf64.lo $elf"; target_size=64 ;;
bfd_elf64_tilegx_vec) tb="$tb elf64-tilegx.lo elfxx-tilegx.lo elf64.lo $elf" ; target_size=64 ;;
bfd_elf64_tilegx_be_vec) tb="$tb elf64-tilegx.lo elfxx-tilegx.lo elf64.lo $elf" ; target_size=64 ;;
bfd_elf64_tilegx_le_vec) tb="$tb elf64-tilegx.lo elfxx-tilegx.lo elf64.lo $elf" ; target_size=64 ;;
bfd_elf64_tradbigmips_vec | bfd_elf64_tradbigmips_freebsd_vec)
tb="$tb elf64-mips.lo elf64.lo elfxx-mips.lo elf-vxworks.lo elf32.lo $elf ecofflink.lo"; target_size=64 ;;
bfd_elf64_tradlittlemips_vec | bfd_elf64_tradlittlemips_freebsd_vec)

6
bfd/elf32-tilegx.c
View File

@ -87,8 +87,10 @@ tilegx_elf_grok_psinfo (bfd *abfd, Elf_Internal_Note *note)
#define ELF_MAXPAGESIZE 0x10000
#define ELF_COMMONPAGESIZE 0x10000
#define TARGET_LITTLE_SYM bfd_elf32_tilegx_vec
#define TARGET_LITTLE_NAME "elf32-tilegx"
#define TARGET_BIG_SYM bfd_elf32_tilegx_be_vec
#define TARGET_BIG_NAME "elf32-tilegx-be"
#define TARGET_LITTLE_SYM bfd_elf32_tilegx_le_vec
#define TARGET_LITTLE_NAME "elf32-tilegx-le"
#define elf_backend_reloc_type_class tilegx_reloc_type_class

7
bfd/elf64-tilegx.c
View File

@ -87,8 +87,11 @@ tilegx_elf_grok_psinfo (bfd *abfd, Elf_Internal_Note *note)
#define ELF_MAXPAGESIZE 0x10000
#define ELF_COMMONPAGESIZE 0x10000
#define TARGET_LITTLE_SYM bfd_elf64_tilegx_vec
#define TARGET_LITTLE_NAME "elf64-tilegx"
#define TARGET_BIG_SYM bfd_elf64_tilegx_be_vec
#define TARGET_BIG_NAME "elf64-tilegx-be"
#define TARGET_LITTLE_SYM bfd_elf64_tilegx_le_vec
#define TARGET_LITTLE_NAME "elf64-tilegx-le"
#define elf_backend_reloc_type_class tilegx_reloc_type_class

12
bfd/targets.c
View File

@ -704,7 +704,8 @@ extern const bfd_target bfd_elf32_tic6x_elf_be_vec;
extern const bfd_target bfd_elf32_tic6x_elf_le_vec;
extern const bfd_target bfd_elf32_tic6x_linux_be_vec;
extern const bfd_target bfd_elf32_tic6x_linux_le_vec;
extern const bfd_target bfd_elf32_tilegx_vec;
extern const bfd_target bfd_elf32_tilegx_be_vec;
extern const bfd_target bfd_elf32_tilegx_le_vec;
extern const bfd_target bfd_elf32_tilepro_vec;
extern const bfd_target bfd_elf32_tradbigmips_vec;
extern const bfd_target bfd_elf32_tradlittlemips_vec;
@ -743,7 +744,8 @@ extern const bfd_target bfd_elf64_sh64nbsd_vec;
extern const bfd_target bfd_elf64_sparc_vec;
extern const bfd_target bfd_elf64_sparc_freebsd_vec;
extern const bfd_target bfd_elf64_sparc_sol2_vec;
extern const bfd_target bfd_elf64_tilegx_vec;
extern const bfd_target bfd_elf64_tilegx_be_vec;
extern const bfd_target bfd_elf64_tilegx_le_vec;
extern const bfd_target bfd_elf64_tradbigmips_vec;
extern const bfd_target bfd_elf64_tradlittlemips_vec;
extern const bfd_target bfd_elf64_tradbigmips_freebsd_vec;
@ -1073,7 +1075,8 @@ static const bfd_target * const _bfd_target_vector[] =
&bfd_elf32_spu_vec,
&bfd_elf32_tic6x_be_vec,
&bfd_elf32_tic6x_le_vec,
&bfd_elf32_tilegx_vec,
&bfd_elf32_tilegx_be_vec,
&bfd_elf32_tilegx_le_vec,
&bfd_elf32_tilepro_vec,
&bfd_elf32_tradbigmips_vec,
&bfd_elf32_tradlittlemips_vec,
@ -1113,7 +1116,8 @@ static const bfd_target * const _bfd_target_vector[] =
&bfd_elf64_sparc_vec,
&bfd_elf64_sparc_freebsd_vec,
&bfd_elf64_sparc_sol2_vec,
&bfd_elf64_tilegx_vec,
&bfd_elf64_tilegx_be_vec,
&bfd_elf64_tilegx_le_vec,
&bfd_elf64_tradbigmips_vec,
&bfd_elf64_tradlittlemips_vec,
&bfd_elf64_tradbigmips_freebsd_vec,

4
binutils/testsuite/ChangeLog
View File

@ -1,3 +1,7 @@
2012-02-25 Walter Lee <walt@tilera.com>
* binutils-all/objdump.exp (cpus_expected): Add tilegx.
2012-02-14 Alan Modra <amodra@gmail.com>
* binutils-all/dlltool.exp: Add setup_xfail.

4
binutils/testsuite/binutils-all/objdump.exp
View File

@ -41,8 +41,8 @@ lappend cpus_expected d10v d30v fr30 fr500 fr550 h8 hppa i386 i860 i960 ip2022
lappend cpus_expected m16c m32c m32r m68hc11 m68hc12 m68k m88k MCore MicroBlaze
lappend cpus_expected mips mn10200 mn10300 ms1 msp ns32k pj powerpc pyramid
lappend cpus_expected romp rs6000 s390 sh sparc
lappend cpus_expected tahoe tic54x tic80 tms320c30 tms320c4x tms320c54x v850
lappend cpus_expected vax we32k x86-64 xscale xtensa z8k z8001 z8002
lappend cpus_expected tahoe tic54x tic80 tilegx tms320c30 tms320c4x tms320c54x
lappend cpus_expected v850 vax we32k x86-64 xscale xtensa z8k z8001 z8002
# Make sure the target CPU shows up in the list.
lappend cpus_expected ${target_cpu}

15
gas/ChangeLog
View File

@ -1,6 +1,19 @@
2012-02-25 Walter Lee <walt@tilera.com>
* tc-tilegx.c (md_begin): set architecture and machine.
* tc-tilegx.c (md_begin): Set architecture and machine.
(tilegx_target_format): Handle big endian.
(OPTION_EB): Define.
(OPTION_EL): Define.
(md_longopts): Add entries for "EB" and "EL".
(md_parse_option): Handle OPTION_EB and OPTION_EL.
(md_show_usage): Add -EB and -EL.
(md_number_to_chars): New.
* tc-tilegx.h (TARGET_BYTES_BIG_ENDIAN): Guard definition with
ifndef.
(md_number_to_chars): Delete.
* configure.tgt (tilegx*be): Handle.
* doc/as.texinfo [TILE-Gx]: Document -EB and -EL.
* doc/c-tilegx.texi: Ditto.
2012-02-21 H.J. Lu <hongjiu.lu@intel.com>

28
gas/config/tc-tilegx.c
View File

@ -72,12 +72,18 @@ static int tilegx_arch_size = 64;
const char *
tilegx_target_format (void)
{
return tilegx_arch_size == 64 ? "elf64-tilegx" : "elf32-tilegx";
if (target_big_endian) {
return tilegx_arch_size == 64 ? "elf64-tilegx-be" : "elf32-tilegx-be";
} else {
return tilegx_arch_size == 64 ? "elf64-tilegx-le" : "elf32-tilegx-le";
}
}
#define OPTION_32 (OPTION_MD_BASE + 0)
#define OPTION_64 (OPTION_MD_BASE + 1)
#define OPTION_EB (OPTION_MD_BASE + 2)
#define OPTION_EL (OPTION_MD_BASE + 3)
const char *md_shortopts = "VQ:";
@ -85,6 +91,8 @@ struct option md_longopts[] =
{
{"32", no_argument, NULL, OPTION_32},
{"64", no_argument, NULL, OPTION_64},
{"EB", no_argument, NULL, OPTION_EB },
{"EL", no_argument, NULL, OPTION_EL },
{NULL, no_argument, NULL, 0}
};
@ -113,6 +121,14 @@ md_parse_option (int c, char *arg ATTRIBUTE_UNUSED)
tilegx_arch_size = 64;
break;
case OPTION_EB:
target_big_endian = 1;
break;
case OPTION_EL:
target_big_endian = 0;
break;
default:
return 0;
}
@ -126,6 +142,7 @@ md_show_usage (FILE *stream)
fprintf (stream, _("\
-Q ignored\n\
-V print assembler version number\n\
-EB/-EL generate big-endian/little-endian code\n\
--32/--64 generate 32bit/64bit code\n"));
}
@ -1269,6 +1286,15 @@ const pseudo_typeS md_pseudo_table[] =
/* Equal to MAX_PRECISION in atof-ieee.c */
#define MAX_LITTLENUMS 6
void
md_number_to_chars (char * buf, valueT val, int n)
{
if (target_big_endian)
number_to_chars_bigendian (buf, val, n);
else
number_to_chars_littleendian (buf, val, n);
}
/* Turn the string pointed to by litP into a floating point constant
of type TYPE, and emit the appropriate bytes. The number of
LITTLENUMS emitted is stored in *SIZEP. An error message is

4
gas/config/tc-tilegx.h
View File

@ -24,7 +24,9 @@
#define TC_TILEGX
#ifndef TARGET_BYTES_BIG_ENDIAN
#define TARGET_BYTES_BIG_ENDIAN 0
#endif
#define WORKING_DOT_WORD
@ -35,8 +37,6 @@ extern const char * tilegx_target_format (void);
#define DWARF2_LINE_MIN_INSN_LENGTH 8
#define md_number_to_chars number_to_chars_littleendian
#define DIFF_EXPR_OK /* foo-. gets turned into PC relative relocs */
#define HANDLE_ALIGN(fragp) tilegx_handle_align (fragp)

4
gas/configure.tgt
View File

@ -82,6 +82,8 @@ case ${cpu} in
sparclet*) cpu_type=sparc arch=sparclet ;;
sparclite*) cpu_type=sparc arch=sparclite ;;
sparc*) cpu_type=sparc arch=sparclite ;; # ??? See tc-sparc.c.
tilegx*be) cpu_type=tilegx endian=big ;;
tilegx*) cpu_type=tilegx endian=little ;;
v850*) cpu_type=v850 ;;
x86_64*) cpu_type=i386 arch=x86_64;;
xtensa*) cpu_type=xtensa arch=xtensa ;;
@ -404,7 +406,7 @@ case ${generic_target} in
tic54x-*-* | c54x*-*-*) fmt=coff bfd_gas=yes need_libm=yes;;
tic6x-*-*) fmt=elf ;;
tilepro-*-* | tilegx-*-*) fmt=elf ;;
tilepro-*-* | tilegx*-*-*) fmt=elf ;;
v850*-*-*) fmt=elf ;;

2
gas/doc/as.texinfo
View File

@ -497,7 +497,7 @@ gcc(1), ld(1), and the Info entries for @file{binutils} and @file{ld}.
@ifset TILEGX
@emph{Target TILE-Gx options:}
[@b{-m32}|@b{-m64}]
[@b{-m32}|@b{-m64}][@b{-EB}][@b{-EL}]
@end ifset
@ifset TILEPRO
@c TILEPro has no machine-dependent assembler options

5
gas/doc/c-tilegx.texi
View File

@ -33,6 +33,11 @@ The following table lists all available TILE-Gx specific options:
@item -m32 | -m64
Select the word size, either 32 bits or 64 bits.
@cindex @samp{-EB} option, TILE-Gx
@cindex @samp{-EL} option, TILE-Gx
@item -EB | -EL
Select the endianness, either big-endian (-EB) or little-endian (-EL).
@end table
@c man end

18
ld/ChangeLog
View File

@ -1,3 +1,21 @@
2012-02-25 Walter Lee <walt@tilera.com>
* Makefile.am (ALL_EMULATION_SOURCES): Add eelf32tilegx_be.c.
(ALL_64_EMULATION_SOURCES): Add eelf64tilegx_be.c.
(eelf32tilegx_be.c): Add rule to build this file.
(eelf64tilegx_be.c): Ditto.
* Makefile.in: Regenerate.
* configure.tgt (tilegx-*-*): Support big endian.
(tilegxbe-*-*): New.
* emulparams/elf32tilegx.sh (OUTPUT_FORMAT): Rename.
(BIG_OUTPUT_FORMAT): Define.
(LITTLE_OUTPUT_FORMAT): Define.
* emulparams/elf32tilegx_be.sh: New.
* emulparams/elf64tilegx.sh (OUTPUT_FORMAT): Rename.
(BIG_OUTPUT_FORMAT): Define.
(LITTLE_OUTPUT_FORMAT): Define.
* emulparams/elf64tilegx_be.sh: New.
2012-02-24 Kai Tietz <ktietz@redhat.com>
PR binutils/13710

10
ld/Makefile.am
View File

@ -250,6 +250,7 @@ ALL_EMULATION_SOURCES = \
eelf32rl78.c \
eelf32rx.c \
eelf32tilegx.c \
eelf32tilegx_be.c \
eelf32tilepro.c \
eelf32vax.c \
eelf32xc16x.c \
@ -482,6 +483,7 @@ ALL_64_EMULATION_SOURCES = \
eelf64ppc.c \
eelf64ppc_fbsd.c \
eelf64tilegx.c \
eelf64tilegx_be.c \
eelf_l1om.c \
eelf_l1om_fbsd.c \
eelf_k1om.c \
@ -1152,6 +1154,10 @@ eelf32tilegx.c: $(srcdir)/emulparams/elf32tilegx.sh \
$(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/needrelax.em \
$(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
${GENSCRIPTS} elf32tilegx "$(tdir_tilegx)"
eelf32tilegx_be.c: $(srcdir)/emulparams/elf32tilegx_be.sh \
$(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/needrelax.em \
$(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
${GENSCRIPTS} elf32tilegx_be "$(tdir_tilegx_be)"
eelf32tilepro.c: $(srcdir)/emulparams/elf32tilepro.sh \
$(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/needrelax.em \
$(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
@ -1989,6 +1995,10 @@ eelf64tilegx.c: $(srcdir)/emulparams/elf64tilegx.sh \
$(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/needrelax.em \
$(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
${GENSCRIPTS} elf64tilegx "$(tdir_tilegx)"
eelf64tilegx_be.c: $(srcdir)/emulparams/elf64tilegx_be.sh \
$(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/needrelax.em \
$(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
${GENSCRIPTS} elf64tilegx_be "$(tdir_tilegx_be)"
eelf_l1om.c: $(srcdir)/emulparams/elf_l1om.sh \
$(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
${GENSCRIPTS} elf_l1om "$(tdir_elf_l1om)"

12
ld/Makefile.in
View File

@ -556,6 +556,7 @@ ALL_EMULATION_SOURCES = \
eelf32rl78.c \
eelf32rx.c \
eelf32tilegx.c \
eelf32tilegx_be.c \
eelf32tilepro.c \
eelf32vax.c \
eelf32xc16x.c \
@ -787,6 +788,7 @@ ALL_64_EMULATION_SOURCES = \
eelf64ppc.c \
eelf64ppc_fbsd.c \
eelf64tilegx.c \
eelf64tilegx_be.c \
eelf_l1om.c \
eelf_l1om_fbsd.c \
eelf_k1om.c \
@ -1159,6 +1161,7 @@ distclean-compile:
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32rl78.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32rx.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32tilegx.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32tilegx_be.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32tilepro.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32vax.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32xc16x.Po@am__quote@
@ -1187,6 +1190,7 @@ distclean-compile:
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64ppc.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64ppc_fbsd.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64tilegx.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64tilegx_be.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf_i386.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf_i386_be.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf_i386_chaos.Po@am__quote@
@ -2608,6 +2612,10 @@ eelf32tilegx.c: $(srcdir)/emulparams/elf32tilegx.sh \
$(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/needrelax.em \
$(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
${GENSCRIPTS} elf32tilegx "$(tdir_tilegx)"
eelf32tilegx_be.c: $(srcdir)/emulparams/elf32tilegx_be.sh \
$(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/needrelax.em \
$(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
${GENSCRIPTS} elf32tilegx_be "$(tdir_tilegx_be)"
eelf32tilepro.c: $(srcdir)/emulparams/elf32tilepro.sh \
$(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/needrelax.em \
$(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
@ -3445,6 +3453,10 @@ eelf64tilegx.c: $(srcdir)/emulparams/elf64tilegx.sh \
$(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/needrelax.em \
$(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
${GENSCRIPTS} elf64tilegx "$(tdir_tilegx)"
eelf64tilegx_be.c: $(srcdir)/emulparams/elf64tilegx_be.sh \
$(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/needrelax.em \
$(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
${GENSCRIPTS} elf64tilegx_be "$(tdir_tilegx_be)"
eelf_l1om.c: $(srcdir)/emulparams/elf_l1om.sh \
$(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
${GENSCRIPTS} elf_l1om "$(tdir_elf_l1om)"

5
ld/configure.tgt
View File

@ -654,7 +654,10 @@ tic6x-*-uclinux) targ_emul=elf32_tic6x_linux_le
tic80-*-*) targ_emul=tic80coff
;;
tilegx-*-*) targ_emul=elf64tilegx
targ_extra_emuls="elf32tilegx"
targ_extra_emuls="elf64tilegx_be elf32tilegx elf32tilegx_be"
targ_extra_libpath=$targ_extra_emuls ;;
tilegxbe-*-*) targ_emul=elf64tilegx_be
targ_extra_emuls="elf64tilegx elf32tilegx elf32tilegx_be"
targ_extra_libpath=$targ_extra_emuls ;;
tilepro-*-*) targ_emul=elf32tilepro ;;
v850*-*-*) targ_emul=v850

4
ld/emulparams/elf32tilegx.sh
View File

@ -1,5 +1,7 @@
SCRIPT_NAME=elf
OUTPUT_FORMAT="elf32-tilegx"
OUTPUT_FORMAT="elf32-tilegx-le"
BIG_OUTPUT_FORMAT="elf32-tilegx-be"
LITTLE_OUTPUT_FORMAT="elf32-tilegx-le"
TEXT_START_ADDR=0x10000
NO_REL_RELOCS=yes
MAXPAGESIZE="CONSTANT (MAXPAGESIZE)"

2
ld/emulparams/elf32tilegx_be.sh
View File

@ -0,0 +1,2 @@
. ${srcdir}/emulparams/elf32tilegx.sh
OUTPUT_FORMAT="elf32-tilegx-be"

4
ld/emulparams/elf64tilegx.sh
View File

@ -1,5 +1,7 @@
SCRIPT_NAME=elf
OUTPUT_FORMAT="elf64-tilegx"
OUTPUT_FORMAT="elf64-tilegx-le"
BIG_OUTPUT_FORMAT="elf64-tilegx-be"
LITTLE_OUTPUT_FORMAT="elf64-tilegx-le"
TEXT_START_ADDR=0x10000
NO_REL_RELOCS=yes
MAXPAGESIZE="CONSTANT (MAXPAGESIZE)"

2
ld/emulparams/elf64tilegx_be.sh
View File

@ -0,0 +1,2 @@
. ${srcdir}/emulparams/elf64tilegx.sh
OUTPUT_FORMAT="elf64-tilegx-be"

7
ld/testsuite/ChangeLog
View File

@ -1,3 +1,10 @@
2012-02-25 Walter Lee <walt@tilera.com>
* ld-tilegx/reloc-be.d: New.
* ld-tilegx/reloc-le.d: New.
* ld-tilegx/reloc.d: Delete.
* ld-tilegx/tilegx.exp: Test big and little endian.
2012-02-22 Nick Clifton <nickc@redhat.com>
PR ld/13683

70
ld/testsuite/ld-tilegx/reloc-be.d
View File

@ -0,0 +1,70 @@
.*: file format .*tilegx.*
Contents of section .text:
100b0 .*
100c0 .*
100d0 .*
100e0 .*
100f0 .*
10100 .*
10110 .*
10120 .*
10130 .*
10140 .*
10150 .*
10160 .*
10170 .*
10180 .*
10190 .*
101a0 .*
101b0 .*
101c0 .*
Contents of section .data:
201e0 000101b8 000101c0 827a4b64 11770000 .*
201f0 0032002e 2c827a12 34567812 3456789a .*
20200 bc123456 789abcde f0000000 00000000 .*
20210 00000000 00000000 00000000 00000000 .*
Disassembly of section .text:
00000000000100b0 <_start>:
100b0: [0-9a-f]* { add r2, zero, zero }
100b8: [0-9a-f]* { j 101b8 <external1> }
100c0: [0-9a-f]* { add r3, r2, r2 }
100c8: [0-9a-f]* { beqzt zero, 101c0 <external2> }
100d0: [0-9a-f]* { movei r2, 17 ; movei r3, 119 }
100d8: [0-9a-f]* { movei r2, 17 ; movei r3, 119 ; ld zero, zero }
100e0: [0-9a-f]* { mtspr 17, zero }
100e8: [0-9a-f]* { mfspr zero, 17 }
100f0: [0-9a-f]* { moveli r2, -32134 ; moveli r3, 19300 }
100f8: [0-9a-f]* { moveli r2, 4660 ; moveli r3, -30293 }
10100: [0-9a-f]* { shl16insli r2, r2, 22136 ; shl16insli r3, r3, -12816 }
10108: [0-9a-f]* { moveli r2, 4660 ; moveli r3, 30292 }
10110: [0-9a-f]* { shl16insli r2, r2, 22136 ; shl16insli r3, r3, 12816 }
10118: [0-9a-f]* { shl16insli r2, r2, -25924 ; shl16insli r3, r3, -292 }
10120: [0-9a-f]* { moveli r2, 4660 ; moveli r3, -292 }
10128: [0-9a-f]* { shl16insli r2, r2, 22136 ; shl16insli r3, r3, -17768 }
10130: [0-9a-f]* { shl16insli r2, r2, -25924 ; shl16insli r3, r3, 30292 }
10138: [0-9a-f]* { shl16insli r2, r2, -8464 ; shl16insli r3, r3, 12816 }
10140: [0-9a-f]* { ld_add r0, r0, 17 }
10148: [0-9a-f]* { st_add r0, r0, 17 }
10150: [0-9a-f]* { mm r2, r3, 19, 31 }
10158: [0-9a-f]* { shli r2, r3, 19 ; shli r4, r5, 31 }
10160: [0-9a-f]* { shli r2, r3, 19 ; shli r4, r5, 31 ; ld zero, zero }
10168: [0-9a-f]* { moveli r0, 80 ; moveli r1, 80 }
10170: [0-9a-f]* { moveli r0, 1 ; moveli r1, 1 }
10178: [0-9a-f]* { moveli r0, 168 ; moveli r1, 168 }
10180: [0-9a-f]* { moveli r0, 4096 ; moveli r1, 4096 }
10188: [0-9a-f]* { moveli r0, 1 ; moveli r1, 1 }
10190: [0-9a-f]* { moveli r0, 144 ; moveli r1, 144 }
10198: [0-9a-f]* { moveli r0, 4096 ; moveli r1, 4096 }
101a0: [0-9a-f]* { moveli r0, 0 ; moveli r1, 0 }
101a8: [0-9a-f]* { moveli r0, 1 ; moveli r1, 1 }
101b0: [0-9a-f]* { moveli r0, 112 ; moveli r1, 112 }
00000000000101b8 <external1>:
101b8: [0-9a-f]* { j 101b8 <external1> }
00000000000101c0 <external2>:
101c0: [0-9a-f]* { j 101b8 <external1> }

2
ld/testsuite/ld-tilegx/reloc.d → ld/testsuite/ld-tilegx/reloc-le.d
View File

@ -1,5 +1,5 @@
.*: file format elf64-tilegx.*
.*: file format .*tilegx.*
Contents of section .text:
100b0 .*

19
ld/testsuite/ld-tilegx/tilegx.exp
View File

@ -24,14 +24,21 @@ if {!([istarget "tilegx-*-*"]) } {
# Set up a list as described in ld-lib.exp
set tilepro_tests {
{ "tilegx relocation resolution linker test"
""
""
set tilegx_tests {
{ "tilegx little-endian relocation resolution linker test"
"-EL"
"-EL"
{ "reloc.s" "external.s" }
{ {objdump -ds reloc.d} }
{ {objdump -ds reloc-le.d} }
"reloc"
}
{ "tilegx big-endian relocation resolution linker test"
"-EB"
"-EB"
{ "reloc.s" "external.s" }
{ {objdump -ds reloc-be.d} }
"reloc"
}
}
run_ld_link_tests $tilepro_tests
run_ld_link_tests $tilegx_tests

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