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@ -72,9 +72,10 @@ typedef unsigned64 uword64; |
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assume the HI32bits of the operand are zero, so we must perform a |
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mask to ensure we can use the simple subtraction to sign-extend. */ |
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#define SIGNEXTEND(e,b) \ |
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((unsigned_word) \ |
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(((e) & ((uword64) 1 << ((b) - 1))) \ |
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? (((e) & (((uword64) 1 << (b)) - 1)) - ((uword64)1 << (b))) \ |
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: ((e) & (((((uword64) 1 << ((b) - 1)) - 1) << 1) | 1))) |
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: ((e) & (((((uword64) 1 << ((b) - 1)) - 1) << 1) | 1)))) |
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/* Check if a value will fit within a halfword: */ |
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#define NOTHALFWORDVALUE(v) ((((((uword64)(v)>>16) == 0) && !((v) & ((unsigned)1 << 15))) || (((((uword64)(v)>>32) == 0xFFFFFFFF) && ((((uword64)(v)>>16) & 0xFFFF) == 0xFFFF)) && ((v) & ((unsigned)1 << 15)))) ? (1 == 0) : (1 == 1)) |
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@ -354,7 +355,7 @@ struct _sim_cpu { |
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vector of registers. The internal simulator engine then uses |
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manifests to access the correct slot. */ |
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signed_word registers[LAST_EMBED_REGNUM + 1]; |
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unsigned_word registers[LAST_EMBED_REGNUM + 1]; |
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int register_widths[NUM_REGS]; |
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#define REGISTERS ((STATE_CPU (sd,0))->registers) |
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