x86: emit {evex} prefix when disassembling ambiguous AVX512VL insns

When no AVX512-specific functionality is in use, the disassembly of
AVX512VL insns is indistinguishable from their AVX counterparts (if such
exist). Emit the {evex} pseudo-prefix in such cases.

Where applicable drop stray uses of PREFIX_OPCODE from table entries.

gas/testsuite/gas/i386/avx512f-opts-intel.d

@@ -65,8 +65,8 @@ Disassembly of section .text:
 [ 	]*[a-f0-9]+:	62 f1 7c 4f 10 f5    	vmovups zmm6\{k7\},zmm5
 [ 	]*[a-f0-9]+:	62 f1 7c cf 11 ee    	vmovups.s zmm6\{k7\}\{z\},zmm5
 [ 	]*[a-f0-9]+:	62 f1 7c cf 10 f5    	vmovups zmm6\{k7\}\{z\},zmm5
-[ 	]*[a-f0-9]+:	62 f1 fd 08 d6 ee    	vmovq\.s xmm6,xmm5
-[ 	]*[a-f0-9]+:	62 f1 fe 08 7e f5    	vmovq  xmm6,xmm5
+[ 	]*[a-f0-9]+:	62 f1 fd 08 d6 ee    	\{evex\} vmovq\.s xmm6,xmm5
+[ 	]*[a-f0-9]+:	62 f1 fe 08 7e f5    	\{evex\} vmovq xmm6,xmm5
 [ 	]*[a-f0-9]+:	62 f1 fd 48 29 ee    	vmovapd.s zmm6,zmm5
 [ 	]*[a-f0-9]+:	62 f1 fd 48 28 f5    	vmovapd zmm6,zmm5
 [ 	]*[a-f0-9]+:	62 f1 fd 4f 29 ee    	vmovapd.s zmm6\{k7\},zmm5

gas/testsuite/gas/i386/avx512f-opts.d

@@ -64,8 +64,8 @@ Disassembly of section .text:
 [ 	]*[a-f0-9]+:	62 f1 7c 4f 10 f5    	vmovups %zmm5,%zmm6\{%k7\}
 [ 	]*[a-f0-9]+:	62 f1 7c cf 11 ee    	vmovups.s %zmm5,%zmm6\{%k7\}\{z\}
 [ 	]*[a-f0-9]+:	62 f1 7c cf 10 f5    	vmovups %zmm5,%zmm6\{%k7\}\{z\}
-[ 	]*[a-f0-9]+:	62 f1 fd 08 d6 ee    	vmovq\.s %xmm5,%xmm6
-[ 	]*[a-f0-9]+:	62 f1 fe 08 7e f5    	vmovq  %xmm5,%xmm6
+[ 	]*[a-f0-9]+:	62 f1 fd 08 d6 ee    	\{evex\} vmovq\.s %xmm5,%xmm6
+[ 	]*[a-f0-9]+:	62 f1 fe 08 7e f5    	\{evex\} vmovq %xmm5,%xmm6
 [ 	]*[a-f0-9]+:	62 f1 fd 48 29 ee    	vmovapd.s %zmm5,%zmm6
 [ 	]*[a-f0-9]+:	62 f1 fd 48 28 f5    	vmovapd %zmm5,%zmm6
 [ 	]*[a-f0-9]+:	62 f1 fd 4f 29 ee    	vmovapd.s %zmm5,%zmm6\{%k7\}

gas/testsuite/gas/i386/avx512vl_vaes-intel.d

@@ -33,30 +33,30 @@ Disassembly of section \.text:
 [ 	]*[a-f0-9]+:[ 	]*c4 e2 55 dd f4[ 	]*vaesenclast ymm6,ymm5,ymm4
 [ 	]*[a-f0-9]+:[ 	]*c4 e2 55 dd b4 f4 c0 1d fe ff[ 	]*vaesenclast ymm6,ymm5,YMMWORD PTR \[esp\+esi\*8-0x1e240\]
 [ 	]*[a-f0-9]+:[ 	]*c4 e2 55 dd b2 e0 0f 00 00[ 	]*vaesenclast ymm6,ymm5,YMMWORD PTR \[edx\+0xfe0\]
-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 08 de f4[ 	]*vaesdec xmm6,xmm5,xmm4
-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 08 de b4 f4 c0 1d fe ff[ 	]*vaesdec xmm6,xmm5,XMMWORD PTR \[esp\+esi\*8-0x1e240\]
-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 08 de 72 7f[ 	]*vaesdec xmm6,xmm5,XMMWORD PTR \[edx\+0x7f0\]
-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 28 de f4[ 	]*vaesdec ymm6,ymm5,ymm4
-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 28 de b4 f4 c0 1d fe ff[ 	]*vaesdec ymm6,ymm5,YMMWORD PTR \[esp\+esi\*8-0x1e240\]
-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 28 de 72 7f[ 	]*vaesdec ymm6,ymm5,YMMWORD PTR \[edx\+0xfe0\]
-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 08 df f4[ 	]*vaesdeclast xmm6,xmm5,xmm4
-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 08 df b4 f4 c0 1d fe ff[ 	]*vaesdeclast xmm6,xmm5,XMMWORD PTR \[esp\+esi\*8-0x1e240\]
-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 08 df 72 7f[ 	]*vaesdeclast xmm6,xmm5,XMMWORD PTR \[edx\+0x7f0\]
-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 28 df f4[ 	]*vaesdeclast ymm6,ymm5,ymm4
-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 28 df b4 f4 c0 1d fe ff[ 	]*vaesdeclast ymm6,ymm5,YMMWORD PTR \[esp\+esi\*8-0x1e240\]
-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 28 df 72 7f[ 	]*vaesdeclast ymm6,ymm5,YMMWORD PTR \[edx\+0xfe0\]
-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 08 dc f4[ 	]*vaesenc xmm6,xmm5,xmm4
-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 08 dc b4 f4 c0 1d fe ff[ 	]*vaesenc xmm6,xmm5,XMMWORD PTR \[esp\+esi\*8-0x1e240\]
-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 08 dc 72 7f[ 	]*vaesenc xmm6,xmm5,XMMWORD PTR \[edx\+0x7f0\]
-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 28 dc f4[ 	]*vaesenc ymm6,ymm5,ymm4
-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 28 dc b4 f4 c0 1d fe ff[ 	]*vaesenc ymm6,ymm5,YMMWORD PTR \[esp\+esi\*8-0x1e240\]
-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 28 dc 72 7f[ 	]*vaesenc ymm6,ymm5,YMMWORD PTR \[edx\+0xfe0\]
-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 08 dd f4[ 	]*vaesenclast xmm6,xmm5,xmm4
-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 08 dd b4 f4 c0 1d fe ff[ 	]*vaesenclast xmm6,xmm5,XMMWORD PTR \[esp\+esi\*8-0x1e240\]
-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 08 dd 72 7f[ 	]*vaesenclast xmm6,xmm5,XMMWORD PTR \[edx\+0x7f0\]
-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 28 dd f4[ 	]*vaesenclast ymm6,ymm5,ymm4
-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 28 dd b4 f4 c0 1d fe ff[ 	]*vaesenclast ymm6,ymm5,YMMWORD PTR \[esp\+esi\*8-0x1e240\]
-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 28 dd 72 7f[ 	]*vaesenclast ymm6,ymm5,YMMWORD PTR \[edx\+0xfe0\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 55 08 de f4[ 	]*\{evex\} vaesdec xmm6,xmm5,xmm4
+[ 	]*[a-f0-9]+:[ 	]*62 f2 55 08 de b4 f4 c0 1d fe ff[ 	]*\{evex\} vaesdec xmm6,xmm5,XMMWORD PTR \[esp\+esi\*8-0x1e240\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 55 08 de 72 7f[ 	]*\{evex\} vaesdec xmm6,xmm5,XMMWORD PTR \[edx\+0x7f0\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 55 28 de f4[ 	]*\{evex\} vaesdec ymm6,ymm5,ymm4
+[ 	]*[a-f0-9]+:[ 	]*62 f2 55 28 de b4 f4 c0 1d fe ff[ 	]*\{evex\} vaesdec ymm6,ymm5,YMMWORD PTR \[esp\+esi\*8-0x1e240\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 55 28 de 72 7f[ 	]*\{evex\} vaesdec ymm6,ymm5,YMMWORD PTR \[edx\+0xfe0\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 55 08 df f4[ 	]*\{evex\} vaesdeclast xmm6,xmm5,xmm4
+[ 	]*[a-f0-9]+:[ 	]*62 f2 55 08 df b4 f4 c0 1d fe ff[ 	]*\{evex\} vaesdeclast xmm6,xmm5,XMMWORD PTR \[esp\+esi\*8-0x1e240\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 55 08 df 72 7f[ 	]*\{evex\} vaesdeclast xmm6,xmm5,XMMWORD PTR \[edx\+0x7f0\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 55 28 df f4[ 	]*\{evex\} vaesdeclast ymm6,ymm5,ymm4
+[ 	]*[a-f0-9]+:[ 	]*62 f2 55 28 df b4 f4 c0 1d fe ff[ 	]*\{evex\} vaesdeclast ymm6,ymm5,YMMWORD PTR \[esp\+esi\*8-0x1e240\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 55 28 df 72 7f[ 	]*\{evex\} vaesdeclast ymm6,ymm5,YMMWORD PTR \[edx\+0xfe0\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 55 08 dc f4[ 	]*\{evex\} vaesenc xmm6,xmm5,xmm4
+[ 	]*[a-f0-9]+:[ 	]*62 f2 55 08 dc b4 f4 c0 1d fe ff[ 	]*\{evex\} vaesenc xmm6,xmm5,XMMWORD PTR \[esp\+esi\*8-0x1e240\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 55 08 dc 72 7f[ 	]*\{evex\} vaesenc xmm6,xmm5,XMMWORD PTR \[edx\+0x7f0\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 55 28 dc f4[ 	]*\{evex\} vaesenc ymm6,ymm5,ymm4
+[ 	]*[a-f0-9]+:[ 	]*62 f2 55 28 dc b4 f4 c0 1d fe ff[ 	]*\{evex\} vaesenc ymm6,ymm5,YMMWORD PTR \[esp\+esi\*8-0x1e240\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 55 28 dc 72 7f[ 	]*\{evex\} vaesenc ymm6,ymm5,YMMWORD PTR \[edx\+0xfe0\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 55 08 dd f4[ 	]*\{evex\} vaesenclast xmm6,xmm5,xmm4
+[ 	]*[a-f0-9]+:[ 	]*62 f2 55 08 dd b4 f4 c0 1d fe ff[ 	]*\{evex\} vaesenclast xmm6,xmm5,XMMWORD PTR \[esp\+esi\*8-0x1e240\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 55 08 dd 72 7f[ 	]*\{evex\} vaesenclast xmm6,xmm5,XMMWORD PTR \[edx\+0x7f0\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 55 28 dd f4[ 	]*\{evex\} vaesenclast ymm6,ymm5,ymm4
+[ 	]*[a-f0-9]+:[ 	]*62 f2 55 28 dd b4 f4 c0 1d fe ff[ 	]*\{evex\} vaesenclast ymm6,ymm5,YMMWORD PTR \[esp\+esi\*8-0x1e240\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 55 28 dd 72 7f[ 	]*\{evex\} vaesenclast ymm6,ymm5,YMMWORD PTR \[edx\+0xfe0\]
 [ 	]*[a-f0-9]+:[ 	]*c4 e2 51 de f4[ 	]*vaesdec xmm6,xmm5,xmm4
 [ 	]*[a-f0-9]+:[ 	]*c4 e2 51 de b4 f4 c0 1d fe ff[ 	]*vaesdec xmm6,xmm5,XMMWORD PTR \[esp\+esi\*8-0x1e240\]
 [ 	]*[a-f0-9]+:[ 	]*c4 e2 51 de b2 f0 07 00 00[ 	]*vaesdec xmm6,xmm5,XMMWORD PTR \[edx\+0x7f0\]
@@ -81,28 +81,28 @@ Disassembly of section \.text:
 [ 	]*[a-f0-9]+:[ 	]*c4 e2 55 dd f4[ 	]*vaesenclast ymm6,ymm5,ymm4
 [ 	]*[a-f0-9]+:[ 	]*c4 e2 55 dd b4 f4 c0 1d fe ff[ 	]*vaesenclast ymm6,ymm5,YMMWORD PTR \[esp\+esi\*8-0x1e240\]
 [ 	]*[a-f0-9]+:[ 	]*c4 e2 55 dd b2 e0 0f 00 00[ 	]*vaesenclast ymm6,ymm5,YMMWORD PTR \[edx\+0xfe0\]
-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 08 de f4[ 	]*vaesdec xmm6,xmm5,xmm4
-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 08 de b4 f4 c0 1d fe ff[ 	]*vaesdec xmm6,xmm5,XMMWORD PTR \[esp\+esi\*8-0x1e240\]
-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 08 de 72 7f[ 	]*vaesdec xmm6,xmm5,XMMWORD PTR \[edx\+0x7f0\]
-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 28 de f4[ 	]*vaesdec ymm6,ymm5,ymm4
-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 28 de b4 f4 c0 1d fe ff[ 	]*vaesdec ymm6,ymm5,YMMWORD PTR \[esp\+esi\*8-0x1e240\]
-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 28 de 72 7f[ 	]*vaesdec ymm6,ymm5,YMMWORD PTR \[edx\+0xfe0\]
-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 08 df f4[ 	]*vaesdeclast xmm6,xmm5,xmm4
-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 08 df b4 f4 c0 1d fe ff[ 	]*vaesdeclast xmm6,xmm5,XMMWORD PTR \[esp\+esi\*8-0x1e240\]
-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 08 df 72 7f[ 	]*vaesdeclast xmm6,xmm5,XMMWORD PTR \[edx\+0x7f0\]
-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 28 df f4[ 	]*vaesdeclast ymm6,ymm5,ymm4
-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 28 df b4 f4 c0 1d fe ff[ 	]*vaesdeclast ymm6,ymm5,YMMWORD PTR \[esp\+esi\*8-0x1e240\]
-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 28 df 72 7f[ 	]*vaesdeclast ymm6,ymm5,YMMWORD PTR \[edx\+0xfe0\]
-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 08 dc f4[ 	]*vaesenc xmm6,xmm5,xmm4
-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 08 dc b4 f4 c0 1d fe ff[ 	]*vaesenc xmm6,xmm5,XMMWORD PTR \[esp\+esi\*8-0x1e240\]
-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 08 dc 72 7f[ 	]*vaesenc xmm6,xmm5,XMMWORD PTR \[edx\+0x7f0\]
-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 28 dc f4[ 	]*vaesenc ymm6,ymm5,ymm4
-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 28 dc b4 f4 c0 1d fe ff[ 	]*vaesenc ymm6,ymm5,YMMWORD PTR \[esp\+esi\*8-0x1e240\]
-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 28 dc 72 7f[ 	]*vaesenc ymm6,ymm5,YMMWORD PTR \[edx\+0xfe0\]
-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 08 dd f4[ 	]*vaesenclast xmm6,xmm5,xmm4
-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 08 dd b4 f4 c0 1d fe ff[ 	]*vaesenclast xmm6,xmm5,XMMWORD PTR \[esp\+esi\*8-0x1e240\]
-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 08 dd 72 7f[ 	]*vaesenclast xmm6,xmm5,XMMWORD PTR \[edx\+0x7f0\]
-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 28 dd f4[ 	]*vaesenclast ymm6,ymm5,ymm4
-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 28 dd b4 f4 c0 1d fe ff[ 	]*vaesenclast ymm6,ymm5,YMMWORD PTR \[esp\+esi\*8-0x1e240\]
-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 28 dd 72 7f[ 	]*vaesenclast ymm6,ymm5,YMMWORD PTR \[edx\+0xfe0\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 55 08 de f4[ 	]*\{evex\} vaesdec xmm6,xmm5,xmm4
+[ 	]*[a-f0-9]+:[ 	]*62 f2 55 08 de b4 f4 c0 1d fe ff[ 	]*\{evex\} vaesdec xmm6,xmm5,XMMWORD PTR \[esp\+esi\*8-0x1e240\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 55 08 de 72 7f[ 	]*\{evex\} vaesdec xmm6,xmm5,XMMWORD PTR \[edx\+0x7f0\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 55 28 de f4[ 	]*\{evex\} vaesdec ymm6,ymm5,ymm4
+[ 	]*[a-f0-9]+:[ 	]*62 f2 55 28 de b4 f4 c0 1d fe ff[ 	]*\{evex\} vaesdec ymm6,ymm5,YMMWORD PTR \[esp\+esi\*8-0x1e240\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 55 28 de 72 7f[ 	]*\{evex\} vaesdec ymm6,ymm5,YMMWORD PTR \[edx\+0xfe0\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 55 08 df f4[ 	]*\{evex\} vaesdeclast xmm6,xmm5,xmm4
+[ 	]*[a-f0-9]+:[ 	]*62 f2 55 08 df b4 f4 c0 1d fe ff[ 	]*\{evex\} vaesdeclast xmm6,xmm5,XMMWORD PTR \[esp\+esi\*8-0x1e240\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 55 08 df 72 7f[ 	]*\{evex\} vaesdeclast xmm6,xmm5,XMMWORD PTR \[edx\+0x7f0\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 55 28 df f4[ 	]*\{evex\} vaesdeclast ymm6,ymm5,ymm4
+[ 	]*[a-f0-9]+:[ 	]*62 f2 55 28 df b4 f4 c0 1d fe ff[ 	]*\{evex\} vaesdeclast ymm6,ymm5,YMMWORD PTR \[esp\+esi\*8-0x1e240\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 55 28 df 72 7f[ 	]*\{evex\} vaesdeclast ymm6,ymm5,YMMWORD PTR \[edx\+0xfe0\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 55 08 dc f4[ 	]*\{evex\} vaesenc xmm6,xmm5,xmm4
+[ 	]*[a-f0-9]+:[ 	]*62 f2 55 08 dc b4 f4 c0 1d fe ff[ 	]*\{evex\} vaesenc xmm6,xmm5,XMMWORD PTR \[esp\+esi\*8-0x1e240\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 55 08 dc 72 7f[ 	]*\{evex\} vaesenc xmm6,xmm5,XMMWORD PTR \[edx\+0x7f0\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 55 28 dc f4[ 	]*\{evex\} vaesenc ymm6,ymm5,ymm4
+[ 	]*[a-f0-9]+:[ 	]*62 f2 55 28 dc b4 f4 c0 1d fe ff[ 	]*\{evex\} vaesenc ymm6,ymm5,YMMWORD PTR \[esp\+esi\*8-0x1e240\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 55 28 dc 72 7f[ 	]*\{evex\} vaesenc ymm6,ymm5,YMMWORD PTR \[edx\+0xfe0\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 55 08 dd f4[ 	]*\{evex\} vaesenclast xmm6,xmm5,xmm4
+[ 	]*[a-f0-9]+:[ 	]*62 f2 55 08 dd b4 f4 c0 1d fe ff[ 	]*\{evex\} vaesenclast xmm6,xmm5,XMMWORD PTR \[esp\+esi\*8-0x1e240\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 55 08 dd 72 7f[ 	]*\{evex\} vaesenclast xmm6,xmm5,XMMWORD PTR \[edx\+0x7f0\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 55 28 dd f4[ 	]*\{evex\} vaesenclast ymm6,ymm5,ymm4
+[ 	]*[a-f0-9]+:[ 	]*62 f2 55 28 dd b4 f4 c0 1d fe ff[ 	]*\{evex\} vaesenclast ymm6,ymm5,YMMWORD PTR \[esp\+esi\*8-0x1e240\]
+[ 	]*[a-f0-9]+:[ 	]*62 f2 55 28 dd 72 7f[ 	]*\{evex\} vaesenclast ymm6,ymm5,YMMWORD PTR \[edx\+0xfe0\]
 #pass

gas/testsuite/gas/i386/avx512vl_vaes.d

@@ -33,30 +33,30 @@ Disassembly of section \.text:
 [ 	]*[a-f0-9]+:[ 	]*c4 e2 55 dd f4[ 	]*vaesenclast %ymm4,%ymm5,%ymm6
 [ 	]*[a-f0-9]+:[ 	]*c4 e2 55 dd b4 f4 c0 1d fe ff[ 	]*vaesenclast -0x1e240\(%esp,%esi,8\),%ymm5,%ymm6
 [ 	]*[a-f0-9]+:[ 	]*c4 e2 55 dd b2 e0 0f 00 00[ 	]*vaesenclast 0xfe0\(%edx\),%ymm5,%ymm6
-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 08 de f4[ 	]*vaesdec %xmm4,%xmm5,%xmm6
-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 08 de b4 f4 c0 1d fe ff[ 	]*vaesdec -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6
-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 08 de 72 7f[ 	]*vaesdec 0x7f0\(%edx\),%xmm5,%xmm6
-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 28 de f4[ 	]*vaesdec %ymm4,%ymm5,%ymm6
-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 28 de b4 f4 c0 1d fe ff[ 	]*vaesdec -0x1e240\(%esp,%esi,8\),%ymm5,%ymm6
-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 28 de 72 7f[ 	]*vaesdec 0xfe0\(%edx\),%ymm5,%ymm6
-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 08 df f4[ 	]*vaesdeclast %xmm4,%xmm5,%xmm6
-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 08 df b4 f4 c0 1d fe ff[ 	]*vaesdeclast -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6
-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 08 df 72 7f[ 	]*vaesdeclast 0x7f0\(%edx\),%xmm5,%xmm6
-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 28 df f4[ 	]*vaesdeclast %ymm4,%ymm5,%ymm6
-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 28 df b4 f4 c0 1d fe ff[ 	]*vaesdeclast -0x1e240\(%esp,%esi,8\),%ymm5,%ymm6
-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 28 df 72 7f[ 	]*vaesdeclast 0xfe0\(%edx\),%ymm5,%ymm6
-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 08 dc f4[ 	]*vaesenc %xmm4,%xmm5,%xmm6
-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 08 dc b4 f4 c0 1d fe ff[ 	]*vaesenc -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6
-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 08 dc 72 7f[ 	]*vaesenc 0x7f0\(%edx\),%xmm5,%xmm6
-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 28 dc f4[ 	]*vaesenc %ymm4,%ymm5,%ymm6
-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 28 dc b4 f4 c0 1d fe ff[ 	]*vaesenc -0x1e240\(%esp,%esi,8\),%ymm5,%ymm6
-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 28 dc 72 7f[ 	]*vaesenc 0xfe0\(%edx\),%ymm5,%ymm6
-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 08 dd f4[ 	]*vaesenclast %xmm4,%xmm5,%xmm6
-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 08 dd b4 f4 c0 1d fe ff[ 	]*vaesenclast -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6
-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 08 dd 72 7f[ 	]*vaesenclast 0x7f0\(%edx\),%xmm5,%xmm6
-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 28 dd f4[ 	]*vaesenclast %ymm4,%ymm5,%ymm6
-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 28 dd b4 f4 c0 1d fe ff[ 	]*vaesenclast -0x1e240\(%esp,%esi,8\),%ymm5,%ymm6
-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 28 dd 72 7f[ 	]*vaesenclast 0xfe0\(%edx\),%ymm5,%ymm6
+[ 	]*[a-f0-9]+:[ 	]*62 f2 55 08 de f4[ 	]*\{evex\} vaesdec %xmm4,%xmm5,%xmm6
+[ 	]*[a-f0-9]+:[ 	]*62 f2 55 08 de b4 f4 c0 1d fe ff[ 	]*\{evex\} vaesdec -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6
+[ 	]*[a-f0-9]+:[ 	]*62 f2 55 08 de 72 7f[ 	]*\{evex\} vaesdec 0x7f0\(%edx\),%xmm5,%xmm6
+[ 	]*[a-f0-9]+:[ 	]*62 f2 55 28 de f4[ 	]*\{evex\} vaesdec %ymm4,%ymm5,%ymm6
+[ 	]*[a-f0-9]+:[ 	]*62 f2 55 28 de b4 f4 c0 1d fe ff[ 	]*\{evex\} vaesdec -0x1e240\(%esp,%esi,8\),%ymm5,%ymm6
+[ 	]*[a-f0-9]+:[ 	]*62 f2 55 28 de 72 7f[ 	]*\{evex\} vaesdec 0xfe0\(%edx\),%ymm5,%ymm6
+[ 	]*[a-f0-9]+:[ 	]*62 f2 55 08 df f4[ 	]*\{evex\} vaesdeclast %xmm4,%xmm5,%xmm6
+[ 	]*[a-f0-9]+:[ 	]*62 f2 55 08 df b4 f4 c0 1d fe ff[ 	]*\{evex\} vaesdeclast -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6
+[ 	]*[a-f0-9]+:[ 	]*62 f2 55 08 df 72 7f[ 	]*\{evex\} vaesdeclast 0x7f0\(%edx\),%xmm5,%xmm6
+[ 	]*[a-f0-9]+:[ 	]*62 f2 55 28 df f4[ 	]*\{evex\} vaesdeclast %ymm4,%ymm5,%ymm6
+[ 	]*[a-f0-9]+:[ 	]*62 f2 55 28 df b4 f4 c0 1d fe ff[ 	]*\{evex\} vaesdeclast -0x1e240\(%esp,%esi,8\),%ymm5,%ymm6
+[ 	]*[a-f0-9]+:[ 	]*62 f2 55 28 df 72 7f[ 	]*\{evex\} vaesdeclast 0xfe0\(%edx\),%ymm5,%ymm6
+[ 	]*[a-f0-9]+:[ 	]*62 f2 55 08 dc f4[ 	]*\{evex\} vaesenc %xmm4,%xmm5,%xmm6
+[ 	]*[a-f0-9]+:[ 	]*62 f2 55 08 dc b4 f4 c0 1d fe ff[ 	]*\{evex\} vaesenc -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6
+[ 	]*[a-f0-9]+:[ 	]*62 f2 55 08 dc 72 7f[ 	]*\{evex\} vaesenc 0x7f0\(%edx\),%xmm5,%xmm6
+[ 	]*[a-f0-9]+:[ 	]*62 f2 55 28 dc f4[ 	]*\{evex\} vaesenc %ymm4,%ymm5,%ymm6
+[ 	]*[a-f0-9]+:[ 	]*62 f2 55 28 dc b4 f4 c0 1d fe ff[ 	]*\{evex\} vaesenc -0x1e240\(%esp,%esi,8\),%ymm5,%ymm6
+[ 	]*[a-f0-9]+:[ 	]*62 f2 55 28 dc 72 7f[ 	]*\{evex\} vaesenc 0xfe0\(%edx\),%ymm5,%ymm6
+[ 	]*[a-f0-9]+:[ 	]*62 f2 55 08 dd f4[ 	]*\{evex\} vaesenclast %xmm4,%xmm5,%xmm6
+[ 	]*[a-f0-9]+:[ 	]*62 f2 55 08 dd b4 f4 c0 1d fe ff[ 	]*\{evex\} vaesenclast -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6
+[ 	]*[a-f0-9]+:[ 	]*62 f2 55 08 dd 72 7f[ 	]*\{evex\} vaesenclast 0x7f0\(%edx\),%xmm5,%xmm6
+[ 	]*[a-f0-9]+:[ 	]*62 f2 55 28 dd f4[ 	]*\{evex\} vaesenclast %ymm4,%ymm5,%ymm6
+[ 	]*[a-f0-9]+:[ 	]*62 f2 55 28 dd b4 f4 c0 1d fe ff[ 	]*\{evex\} vaesenclast -0x1e240\(%esp,%esi,8\),%ymm5,%ymm6
+[ 	]*[a-f0-9]+:[ 	]*62 f2 55 28 dd 72 7f[ 	]*\{evex\} vaesenclast 0xfe0\(%edx\),%ymm5,%ymm6
 [ 	]*[a-f0-9]+:[ 	]*c4 e2 51 de f4[ 	]*vaesdec %xmm4,%xmm5,%xmm6
 [ 	]*[a-f0-9]+:[ 	]*c4 e2 51 de b4 f4 c0 1d fe ff[ 	]*vaesdec -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6
 [ 	]*[a-f0-9]+:[ 	]*c4 e2 51 de b2 f0 07 00 00[ 	]*vaesdec 0x7f0\(%edx\),%xmm5,%xmm6
@@ -81,28 +81,28 @@ Disassembly of section \.text:
 [ 	]*[a-f0-9]+:[ 	]*c4 e2 55 dd f4[ 	]*vaesenclast %ymm4,%ymm5,%ymm6
 [ 	]*[a-f0-9]+:[ 	]*c4 e2 55 dd b4 f4 c0 1d fe ff[ 	]*vaesenclast -0x1e240\(%esp,%esi,8\),%ymm5,%ymm6
 [ 	]*[a-f0-9]+:[ 	]*c4 e2 55 dd b2 e0 0f 00 00[ 	]*vaesenclast 0xfe0\(%edx\),%ymm5,%ymm6
-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 08 de f4[ 	]*vaesdec %xmm4,%xmm5,%xmm6
-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 08 de b4 f4 c0 1d fe ff[ 	]*vaesdec -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6
-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 08 de 72 7f[ 	]*vaesdec 0x7f0\(%edx\),%xmm5,%xmm6
-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 28 de f4[ 	]*vaesdec %ymm4,%ymm5,%ymm6
-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 28 de b4 f4 c0 1d fe ff[ 	]*vaesdec -0x1e240\(%esp,%esi,8\),%ymm5,%ymm6
-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 28 de 72 7f[ 	]*vaesdec 0xfe0\(%edx\),%ymm5,%ymm6
-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 08 df f4[ 	]*vaesdeclast %xmm4,%xmm5,%xmm6
-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 08 df b4 f4 c0 1d fe ff[ 	]*vaesdeclast -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6
-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 08 df 72 7f[ 	]*vaesdeclast 0x7f0\(%edx\),%xmm5,%xmm6
-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 28 df f4[ 	]*vaesdeclast %ymm4,%ymm5,%ymm6
-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 28 df b4 f4 c0 1d fe ff[ 	]*vaesdeclast -0x1e240\(%esp,%esi,8\),%ymm5,%ymm6
-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 28 df 72 7f[ 	]*vaesdeclast 0xfe0\(%edx\),%ymm5,%ymm6
-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 08 dc f4[ 	]*vaesenc %xmm4,%xmm5,%xmm6
-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 08 dc b4 f4 c0 1d fe ff[ 	]*vaesenc -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6
-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 08 dc 72 7f[ 	]*vaesenc 0x7f0\(%edx\),%xmm5,%xmm6
-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 28 dc f4[ 	]*vaesenc %ymm4,%ymm5,%ymm6
-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 28 dc b4 f4 c0 1d fe ff[ 	]*vaesenc -0x1e240\(%esp,%esi,8\),%ymm5,%ymm6
-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 28 dc 72 7f[ 	]*vaesenc 0xfe0\(%edx\),%ymm5,%ymm6
-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 08 dd f4[ 	]*vaesenclast %xmm4,%xmm5,%xmm6
-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 08 dd b4 f4 c0 1d fe ff[ 	]*vaesenclast -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6
-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 08 dd 72 7f[ 	]*vaesenclast 0x7f0\(%edx\),%xmm5,%xmm6
-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 28 dd f4[ 	]*vaesenclast %ymm4,%ymm5,%ymm6
-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 28 dd b4 f4 c0 1d fe ff[ 	]*vaesenclast -0x1e240\(%esp,%esi,8\),%ymm5,%ymm6
-[ 	]*[a-f0-9]+:[ 	]*62 f2 55 28 dd 72 7f[ 	]*vaesenclast 0xfe0\(%edx\),%ymm5,%ymm6
+[ 	]*[a-f0-9]+:[ 	]*62 f2 55 08 de f4[ 	]*\{evex\} vaesdec %xmm4,%xmm5,%xmm6
+[ 	]*[a-f0-9]+:[ 	]*62 f2 55 08 de b4 f4 c0 1d fe ff[ 	]*\{evex\} vaesdec -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6
+[ 	]*[a-f0-9]+:[ 	]*62 f2 55 08 de 72 7f[ 	]*\{evex\} vaesdec 0x7f0\(%edx\),%xmm5,%xmm6
+[ 	]*[a-f0-9]+:[ 	]*62 f2 55 28 de f4[ 	]*\{evex\} vaesdec %ymm4,%ymm5,%ymm6
+[ 	]*[a-f0-9]+:[ 	]*62 f2 55 28 de b4 f4 c0 1d fe ff[ 	]*\{evex\} vaesdec -0x1e240\(%esp,%esi,8\),%ymm5,%ymm6
+[ 	]*[a-f0-9]+:[ 	]*62 f2 55 28 de 72 7f[ 	]*\{evex\} vaesdec 0xfe0\(%edx\),%ymm5,%ymm6
+[ 	]*[a-f0-9]+:[ 	]*62 f2 55 08 df f4[ 	]*\{evex\} vaesdeclast %xmm4,%xmm5,%xmm6
+[ 	]*[a-f0-9]+:[ 	]*62 f2 55 08 df b4 f4 c0 1d fe ff[ 	]*\{evex\} vaesdeclast -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6
+[ 	]*[a-f0-9]+:[ 	]*62 f2 55 08 df 72 7f[ 	]*\{evex\} vaesdeclast 0x7f0\(%edx\),%xmm5,%xmm6
+[ 	]*[a-f0-9]+:[ 	]*62 f2 55 28 df f4[ 	]*\{evex\} vaesdeclast %ymm4,%ymm5,%ymm6
+[ 	]*[a-f0-9]+:[ 	]*62 f2 55 28 df b4 f4 c0 1d fe ff[ 	]*\{evex\} vaesdeclast -0x1e240\(%esp,%esi,8\),%ymm5,%ymm6
+[ 	]*[a-f0-9]+:[ 	]*62 f2 55 28 df 72 7f[ 	]*\{evex\} vaesdeclast 0xfe0\(%edx\),%ymm5,%ymm6
+[ 	]*[a-f0-9]+:[ 	]*62 f2 55 08 dc f4[ 	]*\{evex\} vaesenc %xmm4,%xmm5,%xmm6
+[ 	]*[a-f0-9]+:[ 	]*62 f2 55 08 dc b4 f4 c0 1d fe ff[ 	]*\{evex\} vaesenc -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6
+[ 	]*[a-f0-9]+:[ 	]*62 f2 55 08 dc 72 7f[ 	]*\{evex\} vaesenc 0x7f0\(%edx\),%xmm5,%xmm6
+[ 	]*[a-f0-9]+:[ 	]*62 f2 55 28 dc f4[ 	]*\{evex\} vaesenc %ymm4,%ymm5,%ymm6
+[ 	]*[a-f0-9]+:[ 	]*62 f2 55 28 dc b4 f4 c0 1d fe ff[ 	]*\{evex\} vaesenc -0x1e240\(%esp,%esi,8\),%ymm5,%ymm6
+[ 	]*[a-f0-9]+:[ 	]*62 f2 55 28 dc 72 7f[ 	]*\{evex\} vaesenc 0xfe0\(%edx\),%ymm5,%ymm6
+[ 	]*[a-f0-9]+:[ 	]*62 f2 55 08 dd f4[ 	]*\{evex\} vaesenclast %xmm4,%xmm5,%xmm6
+[ 	]*[a-f0-9]+:[ 	]*62 f2 55 08 dd b4 f4 c0 1d fe ff[ 	]*\{evex\} vaesenclast -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6
+[ 	]*[a-f0-9]+:[ 	]*62 f2 55 08 dd 72 7f[ 	]*\{evex\} vaesenclast 0x7f0\(%edx\),%xmm5,%xmm6
+[ 	]*[a-f0-9]+:[ 	]*62 f2 55 28 dd f4[ 	]*\{evex\} vaesenclast %ymm4,%ymm5,%ymm6
+[ 	]*[a-f0-9]+:[ 	]*62 f2 55 28 dd b4 f4 c0 1d fe ff[ 	]*\{evex\} vaesenclast -0x1e240\(%esp,%esi,8\),%ymm5,%ymm6
+[ 	]*[a-f0-9]+:[ 	]*62 f2 55 28 dd 72 7f[ 	]*\{evex\} vaesenclast 0xfe0\(%edx\),%ymm5,%ymm6
 #pass

gas/testsuite/gas/i386/avx512vl_vpclmulqdq-intel.d

@@ -15,30 +15,30 @@ Disassembly of section \.text:
 [ 	]*[a-f0-9]+:[ 	]*c4 e3 55 44 e1 ab[ 	]*vpclmulqdq ymm4,ymm5,ymm1,0xab
 [ 	]*[a-f0-9]+:[ 	]*c4 e3 55 44 a4 f4 c0 1d fe ff 7b[ 	]*vpclmulqdq ymm4,ymm5,YMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
 [ 	]*[a-f0-9]+:[ 	]*c4 e3 55 44 a2 e0 0f 00 00 7b[ 	]*vpclmulqdq ymm4,ymm5,YMMWORD PTR \[edx\+0xfe0\],0x7b
-[ 	]*[a-f0-9]+:[ 	]*62 f3 6d 08 44 da ab[ 	]*vpclmulqdq xmm3,xmm2,xmm2,0xab
-[ 	]*[a-f0-9]+:[ 	]*62 f3 6d 08 44 9c f4 c0 1d fe ff 7b[ 	]*vpclmulqdq xmm3,xmm2,XMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
-[ 	]*[a-f0-9]+:[ 	]*62 f3 6d 08 44 5a 7f 7b[ 	]*vpclmulqdq xmm3,xmm2,XMMWORD PTR \[edx\+0x7f0\],0x7b
-[ 	]*[a-f0-9]+:[ 	]*62 f3 55 28 44 e1 ab[ 	]*vpclmulqdq ymm4,ymm5,ymm1,0xab
-[ 	]*[a-f0-9]+:[ 	]*62 f3 55 28 44 a4 f4 c0 1d fe ff 7b[ 	]*vpclmulqdq ymm4,ymm5,YMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
-[ 	]*[a-f0-9]+:[ 	]*62 f3 55 28 44 62 7f 7b[ 	]*vpclmulqdq ymm4,ymm5,YMMWORD PTR \[edx\+0xfe0\],0x7b
-[ 	]*[a-f0-9]+:[ 	]*62 f3 65 08 44 e2 11[ 	]*vpclmulhqhqdq xmm4,xmm3,xmm2
-[ 	]*[a-f0-9]+:[ 	]*62 f3 5d 08 44 eb 01[ 	]*vpclmulhqlqdq xmm5,xmm4,xmm3
-[ 	]*[a-f0-9]+:[ 	]*62 f3 55 08 44 f4 10[ 	]*vpclmullqhqdq xmm6,xmm5,xmm4
-[ 	]*[a-f0-9]+:[ 	]*62 f3 4d 08 44 fd 00[ 	]*vpclmullqlqdq xmm7,xmm6,xmm5
-[ 	]*[a-f0-9]+:[ 	]*62 f3 6d 28 44 d9 11[ 	]*vpclmulhqhqdq ymm3,ymm2,ymm1
-[ 	]*[a-f0-9]+:[ 	]*62 f3 65 28 44 e2 01[ 	]*vpclmulhqlqdq ymm4,ymm3,ymm2
-[ 	]*[a-f0-9]+:[ 	]*62 f3 5d 28 44 eb 10[ 	]*vpclmullqhqdq ymm5,ymm4,ymm3
-[ 	]*[a-f0-9]+:[ 	]*62 f3 55 28 44 f4 00[ 	]*vpclmullqlqdq ymm6,ymm5,ymm4
+[ 	]*[a-f0-9]+:[ 	]*62 f3 6d 08 44 da ab[ 	]*\{evex\} vpclmulqdq xmm3,xmm2,xmm2,0xab
+[ 	]*[a-f0-9]+:[ 	]*62 f3 6d 08 44 9c f4 c0 1d fe ff 7b[ 	]*\{evex\} vpclmulqdq xmm3,xmm2,XMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 f3 6d 08 44 5a 7f 7b[ 	]*\{evex\} vpclmulqdq xmm3,xmm2,XMMWORD PTR \[edx\+0x7f0\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 f3 55 28 44 e1 ab[ 	]*\{evex\} vpclmulqdq ymm4,ymm5,ymm1,0xab
+[ 	]*[a-f0-9]+:[ 	]*62 f3 55 28 44 a4 f4 c0 1d fe ff 7b[ 	]*\{evex\} vpclmulqdq ymm4,ymm5,YMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 f3 55 28 44 62 7f 7b[ 	]*\{evex\} vpclmulqdq ymm4,ymm5,YMMWORD PTR \[edx\+0xfe0\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 f3 65 08 44 e2 11[ 	]*\{evex\} vpclmulhqhqdq xmm4,xmm3,xmm2
+[ 	]*[a-f0-9]+:[ 	]*62 f3 5d 08 44 eb 01[ 	]*\{evex\} vpclmulhqlqdq xmm5,xmm4,xmm3
+[ 	]*[a-f0-9]+:[ 	]*62 f3 55 08 44 f4 10[ 	]*\{evex\} vpclmullqhqdq xmm6,xmm5,xmm4
+[ 	]*[a-f0-9]+:[ 	]*62 f3 4d 08 44 fd 00[ 	]*\{evex\} vpclmullqlqdq xmm7,xmm6,xmm5
+[ 	]*[a-f0-9]+:[ 	]*62 f3 6d 28 44 d9 11[ 	]*\{evex\} vpclmulhqhqdq ymm3,ymm2,ymm1
+[ 	]*[a-f0-9]+:[ 	]*62 f3 65 28 44 e2 01[ 	]*\{evex\} vpclmulhqlqdq ymm4,ymm3,ymm2
+[ 	]*[a-f0-9]+:[ 	]*62 f3 5d 28 44 eb 10[ 	]*\{evex\} vpclmullqhqdq ymm5,ymm4,ymm3
+[ 	]*[a-f0-9]+:[ 	]*62 f3 55 28 44 f4 00[ 	]*\{evex\} vpclmullqlqdq ymm6,ymm5,ymm4
 [ 	]*[a-f0-9]+:[ 	]*c4 e3 51 44 db ab[ 	]*vpclmulqdq xmm3,xmm5,xmm3,0xab
 [ 	]*[a-f0-9]+:[ 	]*c4 e3 51 44 9c f4 c0 1d fe ff 7b[ 	]*vpclmulqdq xmm3,xmm5,XMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
 [ 	]*[a-f0-9]+:[ 	]*c4 e3 51 44 9a f0 07 00 00 7b[ 	]*vpclmulqdq xmm3,xmm5,XMMWORD PTR \[edx\+0x7f0\],0x7b
 [ 	]*[a-f0-9]+:[ 	]*c4 e3 6d 44 d2 ab[ 	]*vpclmulqdq ymm2,ymm2,ymm2,0xab
 [ 	]*[a-f0-9]+:[ 	]*c4 e3 6d 44 94 f4 c0 1d fe ff 7b[ 	]*vpclmulqdq ymm2,ymm2,YMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
 [ 	]*[a-f0-9]+:[ 	]*c4 e3 6d 44 92 e0 0f 00 00 7b[ 	]*vpclmulqdq ymm2,ymm2,YMMWORD PTR \[edx\+0xfe0\],0x7b
-[ 	]*[a-f0-9]+:[ 	]*62 f3 55 08 44 db ab[ 	]*vpclmulqdq xmm3,xmm5,xmm3,0xab
-[ 	]*[a-f0-9]+:[ 	]*62 f3 55 08 44 9c f4 c0 1d fe ff 7b[ 	]*vpclmulqdq xmm3,xmm5,XMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
-[ 	]*[a-f0-9]+:[ 	]*62 f3 55 08 44 5a 7f 7b[ 	]*vpclmulqdq xmm3,xmm5,XMMWORD PTR \[edx\+0x7f0\],0x7b
-[ 	]*[a-f0-9]+:[ 	]*62 f3 6d 28 44 d2 ab[ 	]*vpclmulqdq ymm2,ymm2,ymm2,0xab
-[ 	]*[a-f0-9]+:[ 	]*62 f3 6d 28 44 94 f4 c0 1d fe ff 7b[ 	]*vpclmulqdq ymm2,ymm2,YMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
-[ 	]*[a-f0-9]+:[ 	]*62 f3 6d 28 44 52 7f 7b[ 	]*vpclmulqdq ymm2,ymm2,YMMWORD PTR \[edx\+0xfe0\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 f3 55 08 44 db ab[ 	]*\{evex\} vpclmulqdq xmm3,xmm5,xmm3,0xab
+[ 	]*[a-f0-9]+:[ 	]*62 f3 55 08 44 9c f4 c0 1d fe ff 7b[ 	]*\{evex\} vpclmulqdq xmm3,xmm5,XMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 f3 55 08 44 5a 7f 7b[ 	]*\{evex\} vpclmulqdq xmm3,xmm5,XMMWORD PTR \[edx\+0x7f0\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 f3 6d 28 44 d2 ab[ 	]*\{evex\} vpclmulqdq ymm2,ymm2,ymm2,0xab
+[ 	]*[a-f0-9]+:[ 	]*62 f3 6d 28 44 94 f4 c0 1d fe ff 7b[ 	]*\{evex\} vpclmulqdq ymm2,ymm2,YMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 f3 6d 28 44 52 7f 7b[ 	]*\{evex\} vpclmulqdq ymm2,ymm2,YMMWORD PTR \[edx\+0xfe0\],0x7b
 #pass

gas/testsuite/gas/i386/avx512vl_vpclmulqdq-wig1-intel.d

@@ -15,22 +15,22 @@ Disassembly of section \.text:
 [ 	]*[a-f0-9]+:[ 	]*c4 e3 55 44 da ab[ 	]*vpclmulqdq ymm3,ymm5,ymm2,0xab
 [ 	]*[a-f0-9]+:[ 	]*c4 e3 55 44 9c f4 c0 1d fe ff 7b[ 	]*vpclmulqdq ymm3,ymm5,YMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
 [ 	]*[a-f0-9]+:[ 	]*c4 e3 55 44 9a e0 0f 00 00 7b[ 	]*vpclmulqdq ymm3,ymm5,YMMWORD PTR \[edx\+0xfe0\],0x7b
-[ 	]*[a-f0-9]+:[ 	]*62 f3 f5 08 44 cc ab[ 	]*vpclmulqdq xmm1,xmm1,xmm4,0xab
-[ 	]*[a-f0-9]+:[ 	]*62 f3 f5 08 44 8c f4 c0 1d fe ff 7b[ 	]*vpclmulqdq xmm1,xmm1,XMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
-[ 	]*[a-f0-9]+:[ 	]*62 f3 f5 08 44 4a 7f 7b[ 	]*vpclmulqdq xmm1,xmm1,XMMWORD PTR \[edx\+0x7f0\],0x7b
-[ 	]*[a-f0-9]+:[ 	]*62 f3 d5 28 44 da ab[ 	]*vpclmulqdq ymm3,ymm5,ymm2,0xab
-[ 	]*[a-f0-9]+:[ 	]*62 f3 d5 28 44 9c f4 c0 1d fe ff 7b[ 	]*vpclmulqdq ymm3,ymm5,YMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
-[ 	]*[a-f0-9]+:[ 	]*62 f3 d5 28 44 5a 7f 7b[ 	]*vpclmulqdq ymm3,ymm5,YMMWORD PTR \[edx\+0xfe0\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 f3 f5 08 44 cc ab[ 	]*\{evex\} vpclmulqdq xmm1,xmm1,xmm4,0xab
+[ 	]*[a-f0-9]+:[ 	]*62 f3 f5 08 44 8c f4 c0 1d fe ff 7b[ 	]*\{evex\} vpclmulqdq xmm1,xmm1,XMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 f3 f5 08 44 4a 7f 7b[ 	]*\{evex\} vpclmulqdq xmm1,xmm1,XMMWORD PTR \[edx\+0x7f0\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 f3 d5 28 44 da ab[ 	]*\{evex\} vpclmulqdq ymm3,ymm5,ymm2,0xab
+[ 	]*[a-f0-9]+:[ 	]*62 f3 d5 28 44 9c f4 c0 1d fe ff 7b[ 	]*\{evex\} vpclmulqdq ymm3,ymm5,YMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 f3 d5 28 44 5a 7f 7b[ 	]*\{evex\} vpclmulqdq ymm3,ymm5,YMMWORD PTR \[edx\+0xfe0\],0x7b
 [ 	]*[a-f0-9]+:[ 	]*c4 e3 59 44 f1 ab[ 	]*vpclmulqdq xmm6,xmm4,xmm1,0xab
 [ 	]*[a-f0-9]+:[ 	]*c4 e3 59 44 b4 f4 c0 1d fe ff 7b[ 	]*vpclmulqdq xmm6,xmm4,XMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
 [ 	]*[a-f0-9]+:[ 	]*c4 e3 59 44 b2 f0 07 00 00 7b[ 	]*vpclmulqdq xmm6,xmm4,XMMWORD PTR \[edx\+0x7f0\],0x7b
 [ 	]*[a-f0-9]+:[ 	]*c4 e3 5d 44 d4 ab[ 	]*vpclmulqdq ymm2,ymm4,ymm4,0xab
 [ 	]*[a-f0-9]+:[ 	]*c4 e3 5d 44 94 f4 c0 1d fe ff 7b[ 	]*vpclmulqdq ymm2,ymm4,YMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
 [ 	]*[a-f0-9]+:[ 	]*c4 e3 5d 44 92 e0 0f 00 00 7b[ 	]*vpclmulqdq ymm2,ymm4,YMMWORD PTR \[edx\+0xfe0\],0x7b
-[ 	]*[a-f0-9]+:[ 	]*62 f3 dd 08 44 f1 ab[ 	]*vpclmulqdq xmm6,xmm4,xmm1,0xab
-[ 	]*[a-f0-9]+:[ 	]*62 f3 dd 08 44 b4 f4 c0 1d fe ff 7b[ 	]*vpclmulqdq xmm6,xmm4,XMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
-[ 	]*[a-f0-9]+:[ 	]*62 f3 dd 08 44 72 7f 7b[ 	]*vpclmulqdq xmm6,xmm4,XMMWORD PTR \[edx\+0x7f0\],0x7b
-[ 	]*[a-f0-9]+:[ 	]*62 f3 dd 28 44 d4 ab[ 	]*vpclmulqdq ymm2,ymm4,ymm4,0xab
-[ 	]*[a-f0-9]+:[ 	]*62 f3 dd 28 44 94 f4 c0 1d fe ff 7b[ 	]*vpclmulqdq ymm2,ymm4,YMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
-[ 	]*[a-f0-9]+:[ 	]*62 f3 dd 28 44 52 7f 7b[ 	]*vpclmulqdq ymm2,ymm4,YMMWORD PTR \[edx\+0xfe0\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 f3 dd 08 44 f1 ab[ 	]*\{evex\} vpclmulqdq xmm6,xmm4,xmm1,0xab
+[ 	]*[a-f0-9]+:[ 	]*62 f3 dd 08 44 b4 f4 c0 1d fe ff 7b[ 	]*\{evex\} vpclmulqdq xmm6,xmm4,XMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 f3 dd 08 44 72 7f 7b[ 	]*\{evex\} vpclmulqdq xmm6,xmm4,XMMWORD PTR \[edx\+0x7f0\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 f3 dd 28 44 d4 ab[ 	]*\{evex\} vpclmulqdq ymm2,ymm4,ymm4,0xab
+[ 	]*[a-f0-9]+:[ 	]*62 f3 dd 28 44 94 f4 c0 1d fe ff 7b[ 	]*\{evex\} vpclmulqdq ymm2,ymm4,YMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
+[ 	]*[a-f0-9]+:[ 	]*62 f3 dd 28 44 52 7f 7b[ 	]*\{evex\} vpclmulqdq ymm2,ymm4,YMMWORD PTR \[edx\+0xfe0\],0x7b
 #pass

gas/testsuite/gas/i386/avx512vl_vpclmulqdq-wig1.d

@@ -15,22 +15,22 @@ Disassembly of section \.text:
 [ 	]*[a-f0-9]+:[ 	]*c4 e3 55 44 da ab[ 	]*vpclmulqdq \$0xab,%ymm2,%ymm5,%ymm3
 [ 	]*[a-f0-9]+:[ 	]*c4 e3 55 44 9c f4 c0 1d fe ff 7b[ 	]*vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%ymm5,%ymm3
 [ 	]*[a-f0-9]+:[ 	]*c4 e3 55 44 9a e0 0f 00 00 7b[ 	]*vpclmulqdq \$0x7b,0xfe0\(%edx\),%ymm5,%ymm3
-[ 	]*[a-f0-9]+:[ 	]*62 f3 f5 08 44 cc ab[ 	]*vpclmulqdq \$0xab,%xmm4,%xmm1,%xmm1
-[ 	]*[a-f0-9]+:[ 	]*62 f3 f5 08 44 8c f4 c0 1d fe ff 7b[ 	]*vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%xmm1,%xmm1
-[ 	]*[a-f0-9]+:[ 	]*62 f3 f5 08 44 4a 7f 7b[ 	]*vpclmulqdq \$0x7b,0x7f0\(%edx\),%xmm1,%xmm1
-[ 	]*[a-f0-9]+:[ 	]*62 f3 d5 28 44 da ab[ 	]*vpclmulqdq \$0xab,%ymm2,%ymm5,%ymm3
-[ 	]*[a-f0-9]+:[ 	]*62 f3 d5 28 44 9c f4 c0 1d fe ff 7b[ 	]*vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%ymm5,%ymm3
-[ 	]*[a-f0-9]+:[ 	]*62 f3 d5 28 44 5a 7f 7b[ 	]*vpclmulqdq \$0x7b,0xfe0\(%edx\),%ymm5,%ymm3
+[ 	]*[a-f0-9]+:[ 	]*62 f3 f5 08 44 cc ab[ 	]*\{evex\} vpclmulqdq \$0xab,%xmm4,%xmm1,%xmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f3 f5 08 44 8c f4 c0 1d fe ff 7b[ 	]*\{evex\} vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%xmm1,%xmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f3 f5 08 44 4a 7f 7b[ 	]*\{evex\} vpclmulqdq \$0x7b,0x7f0\(%edx\),%xmm1,%xmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f3 d5 28 44 da ab[ 	]*\{evex\} vpclmulqdq \$0xab,%ymm2,%ymm5,%ymm3
+[ 	]*[a-f0-9]+:[ 	]*62 f3 d5 28 44 9c f4 c0 1d fe ff 7b[ 	]*\{evex\} vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%ymm5,%ymm3
+[ 	]*[a-f0-9]+:[ 	]*62 f3 d5 28 44 5a 7f 7b[ 	]*\{evex\} vpclmulqdq \$0x7b,0xfe0\(%edx\),%ymm5,%ymm3
 [ 	]*[a-f0-9]+:[ 	]*c4 e3 59 44 f1 ab[ 	]*vpclmulqdq \$0xab,%xmm1,%xmm4,%xmm6
 [ 	]*[a-f0-9]+:[ 	]*c4 e3 59 44 b4 f4 c0 1d fe ff 7b[ 	]*vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%xmm4,%xmm6
 [ 	]*[a-f0-9]+:[ 	]*c4 e3 59 44 b2 f0 07 00 00 7b[ 	]*vpclmulqdq \$0x7b,0x7f0\(%edx\),%xmm4,%xmm6
 [ 	]*[a-f0-9]+:[ 	]*c4 e3 5d 44 d4 ab[ 	]*vpclmulqdq \$0xab,%ymm4,%ymm4,%ymm2
 [ 	]*[a-f0-9]+:[ 	]*c4 e3 5d 44 94 f4 c0 1d fe ff 7b[ 	]*vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%ymm4,%ymm2
 [ 	]*[a-f0-9]+:[ 	]*c4 e3 5d 44 92 e0 0f 00 00 7b[ 	]*vpclmulqdq \$0x7b,0xfe0\(%edx\),%ymm4,%ymm2
-[ 	]*[a-f0-9]+:[ 	]*62 f3 dd 08 44 f1 ab[ 	]*vpclmulqdq \$0xab,%xmm1,%xmm4,%xmm6
-[ 	]*[a-f0-9]+:[ 	]*62 f3 dd 08 44 b4 f4 c0 1d fe ff 7b[ 	]*vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%xmm4,%xmm6
-[ 	]*[a-f0-9]+:[ 	]*62 f3 dd 08 44 72 7f 7b[ 	]*vpclmulqdq \$0x7b,0x7f0\(%edx\),%xmm4,%xmm6
-[ 	]*[a-f0-9]+:[ 	]*62 f3 dd 28 44 d4 ab[ 	]*vpclmulqdq \$0xab,%ymm4,%ymm4,%ymm2
-[ 	]*[a-f0-9]+:[ 	]*62 f3 dd 28 44 94 f4 c0 1d fe ff 7b[ 	]*vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%ymm4,%ymm2
-[ 	]*[a-f0-9]+:[ 	]*62 f3 dd 28 44 52 7f 7b[ 	]*vpclmulqdq \$0x7b,0xfe0\(%edx\),%ymm4,%ymm2
+[ 	]*[a-f0-9]+:[ 	]*62 f3 dd 08 44 f1 ab[ 	]*\{evex\} vpclmulqdq \$0xab,%xmm1,%xmm4,%xmm6
+[ 	]*[a-f0-9]+:[ 	]*62 f3 dd 08 44 b4 f4 c0 1d fe ff 7b[ 	]*\{evex\} vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%xmm4,%xmm6
+[ 	]*[a-f0-9]+:[ 	]*62 f3 dd 08 44 72 7f 7b[ 	]*\{evex\} vpclmulqdq \$0x7b,0x7f0\(%edx\),%xmm4,%xmm6
+[ 	]*[a-f0-9]+:[ 	]*62 f3 dd 28 44 d4 ab[ 	]*\{evex\} vpclmulqdq \$0xab,%ymm4,%ymm4,%ymm2
+[ 	]*[a-f0-9]+:[ 	]*62 f3 dd 28 44 94 f4 c0 1d fe ff 7b[ 	]*\{evex\} vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%ymm4,%ymm2
+[ 	]*[a-f0-9]+:[ 	]*62 f3 dd 28 44 52 7f 7b[ 	]*\{evex\} vpclmulqdq \$0x7b,0xfe0\(%edx\),%ymm4,%ymm2
 #pass

gas/testsuite/gas/i386/avx512vl_vpclmulqdq.d

@@ -15,30 +15,30 @@ Disassembly of section \.text:
 [ 	]*[a-f0-9]+:[ 	]*c4 e3 55 44 e1 ab[ 	]*vpclmulqdq \$0xab,%ymm1,%ymm5,%ymm4
 [ 	]*[a-f0-9]+:[ 	]*c4 e3 55 44 a4 f4 c0 1d fe ff 7b[ 	]*vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%ymm5,%ymm4
 [ 	]*[a-f0-9]+:[ 	]*c4 e3 55 44 a2 e0 0f 00 00 7b[ 	]*vpclmulqdq \$0x7b,0xfe0\(%edx\),%ymm5,%ymm4
-[ 	]*[a-f0-9]+:[ 	]*62 f3 6d 08 44 da ab[ 	]*vpclmulqdq \$0xab,%xmm2,%xmm2,%xmm3
-[ 	]*[a-f0-9]+:[ 	]*62 f3 6d 08 44 9c f4 c0 1d fe ff 7b[ 	]*vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%xmm2,%xmm3
-[ 	]*[a-f0-9]+:[ 	]*62 f3 6d 08 44 5a 7f 7b[ 	]*vpclmulqdq \$0x7b,0x7f0\(%edx\),%xmm2,%xmm3
-[ 	]*[a-f0-9]+:[ 	]*62 f3 55 28 44 e1 ab[ 	]*vpclmulqdq \$0xab,%ymm1,%ymm5,%ymm4
-[ 	]*[a-f0-9]+:[ 	]*62 f3 55 28 44 a4 f4 c0 1d fe ff 7b[ 	]*vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%ymm5,%ymm4
-[ 	]*[a-f0-9]+:[ 	]*62 f3 55 28 44 62 7f 7b[ 	]*vpclmulqdq \$0x7b,0xfe0\(%edx\),%ymm5,%ymm4
-[ 	]*[a-f0-9]+:[ 	]*62 f3 65 08 44 e2 11[ 	]*vpclmulhqhqdq %xmm2,%xmm3,%xmm4
-[ 	]*[a-f0-9]+:[ 	]*62 f3 5d 08 44 eb 01[ 	]*vpclmulhqlqdq %xmm3,%xmm4,%xmm5
-[ 	]*[a-f0-9]+:[ 	]*62 f3 55 08 44 f4 10[ 	]*vpclmullqhqdq %xmm4,%xmm5,%xmm6
-[ 	]*[a-f0-9]+:[ 	]*62 f3 4d 08 44 fd 00[ 	]*vpclmullqlqdq %xmm5,%xmm6,%xmm7
-[ 	]*[a-f0-9]+:[ 	]*62 f3 6d 28 44 d9 11[ 	]*vpclmulhqhqdq %ymm1,%ymm2,%ymm3
-[ 	]*[a-f0-9]+:[ 	]*62 f3 65 28 44 e2 01[ 	]*vpclmulhqlqdq %ymm2,%ymm3,%ymm4
-[ 	]*[a-f0-9]+:[ 	]*62 f3 5d 28 44 eb 10[ 	]*vpclmullqhqdq %ymm3,%ymm4,%ymm5
-[ 	]*[a-f0-9]+:[ 	]*62 f3 55 28 44 f4 00[ 	]*vpclmullqlqdq %ymm4,%ymm5,%ymm6
+[ 	]*[a-f0-9]+:[ 	]*62 f3 6d 08 44 da ab[ 	]*\{evex\} vpclmulqdq \$0xab,%xmm2,%xmm2,%xmm3
+[ 	]*[a-f0-9]+:[ 	]*62 f3 6d 08 44 9c f4 c0 1d fe ff 7b[ 	]*\{evex\} vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%xmm2,%xmm3
+[ 	]*[a-f0-9]+:[ 	]*62 f3 6d 08 44 5a 7f 7b[ 	]*\{evex\} vpclmulqdq \$0x7b,0x7f0\(%edx\),%xmm2,%xmm3
+[ 	]*[a-f0-9]+:[ 	]*62 f3 55 28 44 e1 ab[ 	]*\{evex\} vpclmulqdq \$0xab,%ymm1,%ymm5,%ymm4
+[ 	]*[a-f0-9]+:[ 	]*62 f3 55 28 44 a4 f4 c0 1d fe ff 7b[ 	]*\{evex\} vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%ymm5,%ymm4
+[ 	]*[a-f0-9]+:[ 	]*62 f3 55 28 44 62 7f 7b[ 	]*\{evex\} vpclmulqdq \$0x7b,0xfe0\(%edx\),%ymm5,%ymm4
+[ 	]*[a-f0-9]+:[ 	]*62 f3 65 08 44 e2 11[ 	]*\{evex\} vpclmulhqhqdq %xmm2,%xmm3,%xmm4
+[ 	]*[a-f0-9]+:[ 	]*62 f3 5d 08 44 eb 01[ 	]*\{evex\} vpclmulhqlqdq %xmm3,%xmm4,%xmm5
+[ 	]*[a-f0-9]+:[ 	]*62 f3 55 08 44 f4 10[ 	]*\{evex\} vpclmullqhqdq %xmm4,%xmm5,%xmm6
+[ 	]*[a-f0-9]+:[ 	]*62 f3 4d 08 44 fd 00[ 	]*\{evex\} vpclmullqlqdq %xmm5,%xmm6,%xmm7
+[ 	]*[a-f0-9]+:[ 	]*62 f3 6d 28 44 d9 11[ 	]*\{evex\} vpclmulhqhqdq %ymm1,%ymm2,%ymm3
+[ 	]*[a-f0-9]+:[ 	]*62 f3 65 28 44 e2 01[ 	]*\{evex\} vpclmulhqlqdq %ymm2,%ymm3,%ymm4
+[ 	]*[a-f0-9]+:[ 	]*62 f3 5d 28 44 eb 10[ 	]*\{evex\} vpclmullqhqdq %ymm3,%ymm4,%ymm5
+[ 	]*[a-f0-9]+:[ 	]*62 f3 55 28 44 f4 00[ 	]*\{evex\} vpclmullqlqdq %ymm4,%ymm5,%ymm6
 [ 	]*[a-f0-9]+:[ 	]*c4 e3 51 44 db ab[ 	]*vpclmulqdq \$0xab,%xmm3,%xmm5,%xmm3
 [ 	]*[a-f0-9]+:[ 	]*c4 e3 51 44 9c f4 c0 1d fe ff 7b[ 	]*vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%xmm5,%xmm3
 [ 	]*[a-f0-9]+:[ 	]*c4 e3 51 44 9a f0 07 00 00 7b[ 	]*vpclmulqdq \$0x7b,0x7f0\(%edx\),%xmm5,%xmm3
 [ 	]*[a-f0-9]+:[ 	]*c4 e3 6d 44 d2 ab[ 	]*vpclmulqdq \$0xab,%ymm2,%ymm2,%ymm2
 [ 	]*[a-f0-9]+:[ 	]*c4 e3 6d 44 94 f4 c0 1d fe ff 7b[ 	]*vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%ymm2,%ymm2
 [ 	]*[a-f0-9]+:[ 	]*c4 e3 6d 44 92 e0 0f 00 00 7b[ 	]*vpclmulqdq \$0x7b,0xfe0\(%edx\),%ymm2,%ymm2
-[ 	]*[a-f0-9]+:[ 	]*62 f3 55 08 44 db ab[ 	]*vpclmulqdq \$0xab,%xmm3,%xmm5,%xmm3
-[ 	]*[a-f0-9]+:[ 	]*62 f3 55 08 44 9c f4 c0 1d fe ff 7b[ 	]*vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%xmm5,%xmm3
-[ 	]*[a-f0-9]+:[ 	]*62 f3 55 08 44 5a 7f 7b[ 	]*vpclmulqdq \$0x7b,0x7f0\(%edx\),%xmm5,%xmm3
-[ 	]*[a-f0-9]+:[ 	]*62 f3 6d 28 44 d2 ab[ 	]*vpclmulqdq \$0xab,%ymm2,%ymm2,%ymm2
-[ 	]*[a-f0-9]+:[ 	]*62 f3 6d 28 44 94 f4 c0 1d fe ff 7b[ 	]*vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%ymm2,%ymm2
-[ 	]*[a-f0-9]+:[ 	]*62 f3 6d 28 44 52 7f 7b[ 	]*vpclmulqdq \$0x7b,0xfe0\(%edx\),%ymm2,%ymm2
+[ 	]*[a-f0-9]+:[ 	]*62 f3 55 08 44 db ab[ 	]*\{evex\} vpclmulqdq \$0xab,%xmm3,%xmm5,%xmm3
+[ 	]*[a-f0-9]+:[ 	]*62 f3 55 08 44 9c f4 c0 1d fe ff 7b[ 	]*\{evex\} vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%xmm5,%xmm3
+[ 	]*[a-f0-9]+:[ 	]*62 f3 55 08 44 5a 7f 7b[ 	]*\{evex\} vpclmulqdq \$0x7b,0x7f0\(%edx\),%xmm5,%xmm3
+[ 	]*[a-f0-9]+:[ 	]*62 f3 6d 28 44 d2 ab[ 	]*\{evex\} vpclmulqdq \$0xab,%ymm2,%ymm2,%ymm2
+[ 	]*[a-f0-9]+:[ 	]*62 f3 6d 28 44 94 f4 c0 1d fe ff 7b[ 	]*\{evex\} vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%ymm2,%ymm2
+[ 	]*[a-f0-9]+:[ 	]*62 f3 6d 28 44 52 7f 7b[ 	]*\{evex\} vpclmulqdq \$0x7b,0xfe0\(%edx\),%ymm2,%ymm2
 #pass

gas/testsuite/gas/i386/evex-lig-2.d

@@ -8,28 +8,28 @@
 Disassembly of section .text:
 
 0+ <_start>:
- +[a-f0-9]+:	62 f1 7d 08 7e 21    	vmovd  %xmm4,\(%ecx\)
- +[a-f0-9]+:	62 f1 7d 08 7e e1    	vmovd  %xmm4,%ecx
- +[a-f0-9]+:	62 f1 7d 08 6e 21    	vmovd  \(%ecx\),%xmm4
- +[a-f0-9]+:	62 f1 7d 08 6e e1    	vmovd  %ecx,%xmm4
- +[a-f0-9]+:	62 f1 fd 08 d6 21    	vmovq  %xmm4,\(%ecx\)
- +[a-f0-9]+:	62 f1 fe 08 7e 21    	vmovq  \(%ecx\),%xmm4
- +[a-f0-9]+:	62 f1 fe 08 7e f4    	vmovq  %xmm4,%xmm6
- +[a-f0-9]+:	62 f3 7d 08 17 c0 00 	vextractps \$0x0,%xmm0,%eax
- +[a-f0-9]+:	62 f3 7d 08 17 00 00 	vextractps \$0x0,%xmm0,\(%eax\)
- +[a-f0-9]+:	62 f3 7d 08 14 c0 00 	vpextrb \$0x0,%xmm0,%eax
- +[a-f0-9]+:	62 f3 7d 08 14 00 00 	vpextrb \$0x0,%xmm0,\(%eax\)
- +[a-f0-9]+:	62 f1 7d 08 c5 c0 00 	vpextrw \$0x0,%xmm0,%eax
- +[a-f0-9]+:	62 f3 7d 08 15 c0 00 	vpextrw \$0x0,%xmm0,%eax
- +[a-f0-9]+:	62 f3 7d 08 15 00 00 	vpextrw \$0x0,%xmm0,\(%eax\)
- +[a-f0-9]+:	62 f3 7d 08 16 c0 00 	vpextrd \$0x0,%xmm0,%eax
- +[a-f0-9]+:	62 f3 7d 08 16 00 00 	vpextrd \$0x0,%xmm0,\(%eax\)
- +[a-f0-9]+:	62 f3 7d 08 21 c0 00 	vinsertps \$0x0,%xmm0,%xmm0,%xmm0
- +[a-f0-9]+:	62 f3 7d 08 21 00 00 	vinsertps \$0x0,\(%eax\),%xmm0,%xmm0
- +[a-f0-9]+:	62 f3 7d 08 20 c0 00 	vpinsrb \$0x0,%eax,%xmm0,%xmm0
- +[a-f0-9]+:	62 f3 7d 08 20 00 00 	vpinsrb \$0x0,\(%eax\),%xmm0,%xmm0
- +[a-f0-9]+:	62 f1 7d 08 c4 c0 00 	vpinsrw \$0x0,%eax,%xmm0,%xmm0
- +[a-f0-9]+:	62 f1 7d 08 c4 00 00 	vpinsrw \$0x0,\(%eax\),%xmm0,%xmm0
- +[a-f0-9]+:	62 f3 7d 08 22 c0 00 	vpinsrd \$0x0,%eax,%xmm0,%xmm0
- +[a-f0-9]+:	62 f3 7d 08 22 00 00 	vpinsrd \$0x0,\(%eax\),%xmm0,%xmm0
+ +[a-f0-9]+:	62 f1 7d 08 7e 21    	\{evex\} vmovd %xmm4,\(%ecx\)
+ +[a-f0-9]+:	62 f1 7d 08 7e e1    	\{evex\} vmovd %xmm4,%ecx
+ +[a-f0-9]+:	62 f1 7d 08 6e 21    	\{evex\} vmovd \(%ecx\),%xmm4
+ +[a-f0-9]+:	62 f1 7d 08 6e e1    	\{evex\} vmovd %ecx,%xmm4
+ +[a-f0-9]+:	62 f1 fd 08 d6 21    	\{evex\} vmovq %xmm4,\(%ecx\)
+ +[a-f0-9]+:	62 f1 fe 08 7e 21    	\{evex\} vmovq \(%ecx\),%xmm4
+ +[a-f0-9]+:	62 f1 fe 08 7e f4    	\{evex\} vmovq %xmm4,%xmm6
+ +[a-f0-9]+:	62 f3 7d 08 17 c0 00 	\{evex\} vextractps \$0x0,%xmm0,%eax
+ +[a-f0-9]+:	62 f3 7d 08 17 00 00 	\{evex\} vextractps \$0x0,%xmm0,\(%eax\)
+ +[a-f0-9]+:	62 f3 7d 08 14 c0 00 	\{evex\} vpextrb \$0x0,%xmm0,%eax
+ +[a-f0-9]+:	62 f3 7d 08 14 00 00 	\{evex\} vpextrb \$0x0,%xmm0,\(%eax\)
+ +[a-f0-9]+:	62 f1 7d 08 c5 c0 00 	\{evex\} vpextrw \$0x0,%xmm0,%eax
+ +[a-f0-9]+:	62 f3 7d 08 15 c0 00 	\{evex\} vpextrw \$0x0,%xmm0,%eax
+ +[a-f0-9]+:	62 f3 7d 08 15 00 00 	\{evex\} vpextrw \$0x0,%xmm0,\(%eax\)
+ +[a-f0-9]+:	62 f3 7d 08 16 c0 00 	\{evex\} vpextrd \$0x0,%xmm0,%eax
+ +[a-f0-9]+:	62 f3 7d 08 16 00 00 	\{evex\} vpextrd \$0x0,%xmm0,\(%eax\)
+ +[a-f0-9]+:	62 f3 7d 08 21 c0 00 	\{evex\} vinsertps \$0x0,%xmm0,%xmm0,%xmm0
+ +[a-f0-9]+:	62 f3 7d 08 21 00 00 	\{evex\} vinsertps \$0x0,\(%eax\),%xmm0,%xmm0
+ +[a-f0-9]+:	62 f3 7d 08 20 c0 00 	\{evex\} vpinsrb \$0x0,%eax,%xmm0,%xmm0
+ +[a-f0-9]+:	62 f3 7d 08 20 00 00 	\{evex\} vpinsrb \$0x0,\(%eax\),%xmm0,%xmm0
+ +[a-f0-9]+:	62 f1 7d 08 c4 c0 00 	\{evex\} vpinsrw \$0x0,%eax,%xmm0,%xmm0
+ +[a-f0-9]+:	62 f1 7d 08 c4 00 00 	\{evex\} vpinsrw \$0x0,\(%eax\),%xmm0,%xmm0
+ +[a-f0-9]+:	62 f3 7d 08 22 c0 00 	\{evex\} vpinsrd \$0x0,%eax,%xmm0,%xmm0
+ +[a-f0-9]+:	62 f3 7d 08 22 00 00 	\{evex\} vpinsrd \$0x0,\(%eax\),%xmm0,%xmm0
 #pass

gas/testsuite/gas/i386/evex-wig1-intel.d

@@ -9,14 +9,14 @@
 Disassembly of section .text:
 
 0+ <_start>:
-[ 	]*[a-f0-9]+:	62 f1 fe 08 2a c0    	vcvtsi2ss xmm0,xmm0,eax
-[ 	]*[a-f0-9]+:	62 f1 fe 08 2a 40 01 	vcvtsi2ss xmm0,xmm0,DWORD PTR \[eax\+0x4\]
-[ 	]*[a-f0-9]+:	62 f1 ff 08 2a c0    	vcvtsi2sd xmm0,xmm0,eax
-[ 	]*[a-f0-9]+:	62 f1 ff 08 2a 40 01 	vcvtsi2sd xmm0,xmm0,DWORD PTR \[eax\+0x4\]
-[ 	]*[a-f0-9]+:	62 f1 fe 08 2d c0    	vcvtss2si eax,xmm0
-[ 	]*[a-f0-9]+:	62 f1 ff 08 2d c0    	vcvtsd2si eax,xmm0
-[ 	]*[a-f0-9]+:	62 f1 fe 08 2c c0    	vcvttss2si eax,xmm0
-[ 	]*[a-f0-9]+:	62 f1 ff 08 2c c0    	vcvttsd2si eax,xmm0
+[ 	]*[a-f0-9]+:	62 f1 fe 08 2a c0    	\{evex\} vcvtsi2ss xmm0,xmm0,eax
+[ 	]*[a-f0-9]+:	62 f1 fe 08 2a 40 01 	\{evex\} vcvtsi2ss xmm0,xmm0,DWORD PTR \[eax\+0x4\]
+[ 	]*[a-f0-9]+:	62 f1 ff 08 2a c0    	\{evex\} vcvtsi2sd xmm0,xmm0,eax
+[ 	]*[a-f0-9]+:	62 f1 ff 08 2a 40 01 	\{evex\} vcvtsi2sd xmm0,xmm0,DWORD PTR \[eax\+0x4\]
+[ 	]*[a-f0-9]+:	62 f1 fe 08 2d c0    	\{evex\} vcvtss2si eax,xmm0
+[ 	]*[a-f0-9]+:	62 f1 ff 08 2d c0    	\{evex\} vcvtsd2si eax,xmm0
+[ 	]*[a-f0-9]+:	62 f1 fe 08 2c c0    	\{evex\} vcvttss2si eax,xmm0
+[ 	]*[a-f0-9]+:	62 f1 ff 08 2c c0    	\{evex\} vcvttsd2si eax,xmm0
 [ 	]*[a-f0-9]+:	62 f1 fe 08 7b c0    	vcvtusi2ss xmm0,xmm0,eax
 [ 	]*[a-f0-9]+:	62 f1 fe 08 7b 40 01 	vcvtusi2ss xmm0,xmm0,DWORD PTR \[eax\+0x4\]
 [ 	]*[a-f0-9]+:	62 f1 ff 08 7b c0    	vcvtusi2sd xmm0,xmm0,eax
@@ -25,26 +25,26 @@ Disassembly of section .text:
 [ 	]*[a-f0-9]+:	62 f1 ff 08 79 c0    	vcvtsd2usi eax,xmm0
 [ 	]*[a-f0-9]+:	62 f1 fe 08 78 c0    	vcvttss2usi eax,xmm0
 [ 	]*[a-f0-9]+:	62 f1 ff 08 78 c0    	vcvttsd2usi eax,xmm0
-[ 	]*[a-f0-9]+:	62 f3 fd 08 17 c0 00 	vextractps eax,xmm0,0x0
-[ 	]*[a-f0-9]+:	62 f3 fd 08 17 40 01 00 	vextractps DWORD PTR \[eax\+0x4\],xmm0,0x0
-[ 	]*[a-f0-9]+:	62 f1 fd 08 6e c0    	vmovd  xmm0,eax
-[ 	]*[a-f0-9]+:	62 f1 fd 08 6e 40 01 	vmovd  xmm0,DWORD PTR \[eax\+0x4\]
-[ 	]*[a-f0-9]+:	62 f1 fd 08 7e c0    	vmovd  eax,xmm0
-[ 	]*[a-f0-9]+:	62 f1 fd 08 7e 40 01 	vmovd  DWORD PTR \[eax\+0x4\],xmm0
+[ 	]*[a-f0-9]+:	62 f3 fd 08 17 c0 00 	\{evex\} vextractps eax,xmm0,0x0
+[ 	]*[a-f0-9]+:	62 f3 fd 08 17 40 01 00 	\{evex\} vextractps DWORD PTR \[eax\+0x4\],xmm0,0x0
+[ 	]*[a-f0-9]+:	62 f1 fd 08 6e c0    	\{evex\} vmovd xmm0,eax
+[ 	]*[a-f0-9]+:	62 f1 fd 08 6e 40 01 	\{evex\} vmovd xmm0,DWORD PTR \[eax\+0x4\]
+[ 	]*[a-f0-9]+:	62 f1 fd 08 7e c0    	\{evex\} vmovd eax,xmm0
+[ 	]*[a-f0-9]+:	62 f1 fd 08 7e 40 01 	\{evex\} vmovd DWORD PTR \[eax\+0x4\],xmm0
 [ 	]*[a-f0-9]+:	62 f2 fd 08 7c c0    	vpbroadcastd xmm0,eax
-[ 	]*[a-f0-9]+:	62 f3 fd 08 14 c0 00 	vpextrb eax,xmm0,0x0
-[ 	]*[a-f0-9]+:	62 f3 fd 08 14 40 01 00 	vpextrb BYTE PTR \[eax\+0x1\],xmm0,0x0
-[ 	]*[a-f0-9]+:	62 f3 fd 08 16 c0 00 	vpextrd eax,xmm0,0x0
-[ 	]*[a-f0-9]+:	62 f3 fd 08 16 40 01 00 	vpextrd DWORD PTR \[eax\+0x4\],xmm0,0x0
-[ 	]*[a-f0-9]+:	62 f1 fd 08 c5 c0 00 	vpextrw eax,xmm0,0x0
-[ 	]*[a-f0-9]+:	62 f3 fd 08 15 c0 00 	vpextrw eax,xmm0,0x0
-[ 	]*[a-f0-9]+:	62 f3 fd 08 15 40 01 00 	vpextrw WORD PTR \[eax\+0x2\],xmm0,0x0
-[ 	]*[a-f0-9]+:	62 f3 fd 08 20 c0 00 	vpinsrb xmm0,xmm0,eax,0x0
-[ 	]*[a-f0-9]+:	62 f3 fd 08 20 40 01 00 	vpinsrb xmm0,xmm0,BYTE PTR \[eax\+0x1\],0x0
-[ 	]*[a-f0-9]+:	62 f3 fd 08 22 c0 00 	vpinsrd xmm0,xmm0,eax,0x0
-[ 	]*[a-f0-9]+:	62 f3 fd 08 22 40 01 00 	vpinsrd xmm0,xmm0,DWORD PTR \[eax\+0x4\],0x0
-[ 	]*[a-f0-9]+:	62 f1 fd 08 c4 c0 00 	vpinsrw xmm0,xmm0,eax,0x0
-[ 	]*[a-f0-9]+:	62 f1 fd 08 c4 40 01 00 	vpinsrw xmm0,xmm0,WORD PTR \[eax\+0x2\],0x0
+[ 	]*[a-f0-9]+:	62 f3 fd 08 14 c0 00 	\{evex\} vpextrb eax,xmm0,0x0
+[ 	]*[a-f0-9]+:	62 f3 fd 08 14 40 01 00 	\{evex\} vpextrb BYTE PTR \[eax\+0x1\],xmm0,0x0
+[ 	]*[a-f0-9]+:	62 f3 fd 08 16 c0 00 	\{evex\} vpextrd eax,xmm0,0x0
+[ 	]*[a-f0-9]+:	62 f3 fd 08 16 40 01 00 	\{evex\} vpextrd DWORD PTR \[eax\+0x4\],xmm0,0x0
+[ 	]*[a-f0-9]+:	62 f1 fd 08 c5 c0 00 	\{evex\} vpextrw eax,xmm0,0x0
+[ 	]*[a-f0-9]+:	62 f3 fd 08 15 c0 00 	\{evex\} vpextrw eax,xmm0,0x0
+[ 	]*[a-f0-9]+:	62 f3 fd 08 15 40 01 00 	\{evex\} vpextrw WORD PTR \[eax\+0x2\],xmm0,0x0
+[ 	]*[a-f0-9]+:	62 f3 fd 08 20 c0 00 	\{evex\} vpinsrb xmm0,xmm0,eax,0x0
+[ 	]*[a-f0-9]+:	62 f3 fd 08 20 40 01 00 	\{evex\} vpinsrb xmm0,xmm0,BYTE PTR \[eax\+0x1\],0x0
+[ 	]*[a-f0-9]+:	62 f3 fd 08 22 c0 00 	\{evex\} vpinsrd xmm0,xmm0,eax,0x0
+[ 	]*[a-f0-9]+:	62 f3 fd 08 22 40 01 00 	\{evex\} vpinsrd xmm0,xmm0,DWORD PTR \[eax\+0x4\],0x0
+[ 	]*[a-f0-9]+:	62 f1 fd 08 c4 c0 00 	\{evex\} vpinsrw xmm0,xmm0,eax,0x0
+[ 	]*[a-f0-9]+:	62 f1 fd 08 c4 40 01 00 	\{evex\} vpinsrw xmm0,xmm0,WORD PTR \[eax\+0x2\],0x0
 [ 	]*[a-f0-9]+:	62 f1 7e 0f 10 c0    	vmovss xmm0\{k7\},xmm0,xmm0
 [ 	]*[a-f0-9]+:	62 f1 7e 0f 10 00    	vmovss xmm0\{k7\},DWORD PTR \[eax\]
 [ 	]*[a-f0-9]+:	62 f1 7e 0f 11 00    	vmovss DWORD PTR \[eax\]\{k7\},xmm0

gas/testsuite/gas/i386/evex-wig1.d

@@ -9,14 +9,14 @@
 Disassembly of section .text:
 
 0+ <_start>:
-[ 	]*[a-f0-9]+:	62 f1 fe 08 2a c0    	vcvtsi2ss %eax,%xmm0,%xmm0
-[ 	]*[a-f0-9]+:	62 f1 fe 08 2a 40 01 	vcvtsi2ss 0x4\(%eax\),%xmm0,%xmm0
-[ 	]*[a-f0-9]+:	62 f1 ff 08 2a c0    	vcvtsi2sd %eax,%xmm0,%xmm0
-[ 	]*[a-f0-9]+:	62 f1 ff 08 2a 40 01 	vcvtsi2sd 0x4\(%eax\),%xmm0,%xmm0
-[ 	]*[a-f0-9]+:	62 f1 fe 08 2d c0    	vcvtss2si %xmm0,%eax
-[ 	]*[a-f0-9]+:	62 f1 ff 08 2d c0    	vcvtsd2si %xmm0,%eax
-[ 	]*[a-f0-9]+:	62 f1 fe 08 2c c0    	vcvttss2si %xmm0,%eax
-[ 	]*[a-f0-9]+:	62 f1 ff 08 2c c0    	vcvttsd2si %xmm0,%eax
+[ 	]*[a-f0-9]+:	62 f1 fe 08 2a c0    	\{evex\} vcvtsi2ss %eax,%xmm0,%xmm0
+[ 	]*[a-f0-9]+:	62 f1 fe 08 2a 40 01 	\{evex\} vcvtsi2ss 0x4\(%eax\),%xmm0,%xmm0
+[ 	]*[a-f0-9]+:	62 f1 ff 08 2a c0    	\{evex\} vcvtsi2sd %eax,%xmm0,%xmm0
+[ 	]*[a-f0-9]+:	62 f1 ff 08 2a 40 01 	\{evex\} vcvtsi2sd 0x4\(%eax\),%xmm0,%xmm0
+[ 	]*[a-f0-9]+:	62 f1 fe 08 2d c0    	\{evex\} vcvtss2si %xmm0,%eax
+[ 	]*[a-f0-9]+:	62 f1 ff 08 2d c0    	\{evex\} vcvtsd2si %xmm0,%eax
+[ 	]*[a-f0-9]+:	62 f1 fe 08 2c c0    	\{evex\} vcvttss2si %xmm0,%eax
+[ 	]*[a-f0-9]+:	62 f1 ff 08 2c c0    	\{evex\} vcvttsd2si %xmm0,%eax
 [ 	]*[a-f0-9]+:	62 f1 fe 08 7b c0    	vcvtusi2ss %eax,%xmm0,%xmm0
 [ 	]*[a-f0-9]+:	62 f1 fe 08 7b 40 01 	vcvtusi2ss 0x4\(%eax\),%xmm0,%xmm0
 [ 	]*[a-f0-9]+:	62 f1 ff 08 7b c0    	vcvtusi2sd %eax,%xmm0,%xmm0
@@ -25,26 +25,26 @@ Disassembly of section .text:
 [ 	]*[a-f0-9]+:	62 f1 ff 08 79 c0    	vcvtsd2usi %xmm0,%eax
 [ 	]*[a-f0-9]+:	62 f1 fe 08 78 c0    	vcvttss2usi %xmm0,%eax
 [ 	]*[a-f0-9]+:	62 f1 ff 08 78 c0    	vcvttsd2usi %xmm0,%eax
-[ 	]*[a-f0-9]+:	62 f3 fd 08 17 c0 00 	vextractps \$0x0,%xmm0,%eax
-[ 	]*[a-f0-9]+:	62 f3 fd 08 17 40 01 00 	vextractps \$0x0,%xmm0,0x4\(%eax\)
-[ 	]*[a-f0-9]+:	62 f1 fd 08 6e c0    	vmovd  %eax,%xmm0
-[ 	]*[a-f0-9]+:	62 f1 fd 08 6e 40 01 	vmovd  0x4\(%eax\),%xmm0
-[ 	]*[a-f0-9]+:	62 f1 fd 08 7e c0    	vmovd  %xmm0,%eax
-[ 	]*[a-f0-9]+:	62 f1 fd 08 7e 40 01 	vmovd  %xmm0,0x4\(%eax\)
+[ 	]*[a-f0-9]+:	62 f3 fd 08 17 c0 00 	\{evex\} vextractps \$0x0,%xmm0,%eax
+[ 	]*[a-f0-9]+:	62 f3 fd 08 17 40 01 00 	\{evex\} vextractps \$0x0,%xmm0,0x4\(%eax\)
+[ 	]*[a-f0-9]+:	62 f1 fd 08 6e c0    	\{evex\} vmovd %eax,%xmm0
+[ 	]*[a-f0-9]+:	62 f1 fd 08 6e 40 01 	\{evex\} vmovd 0x4\(%eax\),%xmm0
+[ 	]*[a-f0-9]+:	62 f1 fd 08 7e c0    	\{evex\} vmovd %xmm0,%eax
+[ 	]*[a-f0-9]+:	62 f1 fd 08 7e 40 01 	\{evex\} vmovd %xmm0,0x4\(%eax\)
 [ 	]*[a-f0-9]+:	62 f2 fd 08 7c c0    	vpbroadcastd %eax,%xmm0
-[ 	]*[a-f0-9]+:	62 f3 fd 08 14 c0 00 	vpextrb \$0x0,%xmm0,%eax
-[ 	]*[a-f0-9]+:	62 f3 fd 08 14 40 01 00 	vpextrb \$0x0,%xmm0,0x1\(%eax\)
-[ 	]*[a-f0-9]+:	62 f3 fd 08 16 c0 00 	vpextrd \$0x0,%xmm0,%eax
-[ 	]*[a-f0-9]+:	62 f3 fd 08 16 40 01 00 	vpextrd \$0x0,%xmm0,0x4\(%eax\)
-[ 	]*[a-f0-9]+:	62 f1 fd 08 c5 c0 00 	vpextrw \$0x0,%xmm0,%eax
-[ 	]*[a-f0-9]+:	62 f3 fd 08 15 c0 00 	vpextrw \$0x0,%xmm0,%eax
-[ 	]*[a-f0-9]+:	62 f3 fd 08 15 40 01 00 	vpextrw \$0x0,%xmm0,0x2\(%eax\)
-[ 	]*[a-f0-9]+:	62 f3 fd 08 20 c0 00 	vpinsrb \$0x0,%eax,%xmm0,%xmm0
-[ 	]*[a-f0-9]+:	62 f3 fd 08 20 40 01 00 	vpinsrb \$0x0,0x1\(%eax\),%xmm0,%xmm0
-[ 	]*[a-f0-9]+:	62 f3 fd 08 22 c0 00 	vpinsrd \$0x0,%eax,%xmm0,%xmm0
-[ 	]*[a-f0-9]+:	62 f3 fd 08 22 40 01 00 	vpinsrd \$0x0,0x4\(%eax\),%xmm0,%xmm0
-[ 	]*[a-f0-9]+:	62 f1 fd 08 c4 c0 00 	vpinsrw \$0x0,%eax,%xmm0,%xmm0
-[ 	]*[a-f0-9]+:	62 f1 fd 08 c4 40 01 00 	vpinsrw \$0x0,0x2\(%eax\),%xmm0,%xmm0
+[ 	]*[a-f0-9]+:	62 f3 fd 08 14 c0 00 	\{evex\} vpextrb \$0x0,%xmm0,%eax
+[ 	]*[a-f0-9]+:	62 f3 fd 08 14 40 01 00 	\{evex\} vpextrb \$0x0,%xmm0,0x1\(%eax\)
+[ 	]*[a-f0-9]+:	62 f3 fd 08 16 c0 00 	\{evex\} vpextrd \$0x0,%xmm0,%eax
+[ 	]*[a-f0-9]+:	62 f3 fd 08 16 40 01 00 	\{evex\} vpextrd \$0x0,%xmm0,0x4\(%eax\)
+[ 	]*[a-f0-9]+:	62 f1 fd 08 c5 c0 00 	\{evex\} vpextrw \$0x0,%xmm0,%eax
+[ 	]*[a-f0-9]+:	62 f3 fd 08 15 c0 00 	\{evex\} vpextrw \$0x0,%xmm0,%eax
+[ 	]*[a-f0-9]+:	62 f3 fd 08 15 40 01 00 	\{evex\} vpextrw \$0x0,%xmm0,0x2\(%eax\)
+[ 	]*[a-f0-9]+:	62 f3 fd 08 20 c0 00 	\{evex\} vpinsrb \$0x0,%eax,%xmm0,%xmm0
+[ 	]*[a-f0-9]+:	62 f3 fd 08 20 40 01 00 	\{evex\} vpinsrb \$0x0,0x1\(%eax\),%xmm0,%xmm0
+[ 	]*[a-f0-9]+:	62 f3 fd 08 22 c0 00 	\{evex\} vpinsrd \$0x0,%eax,%xmm0,%xmm0
+[ 	]*[a-f0-9]+:	62 f3 fd 08 22 40 01 00 	\{evex\} vpinsrd \$0x0,0x4\(%eax\),%xmm0,%xmm0
+[ 	]*[a-f0-9]+:	62 f1 fd 08 c4 c0 00 	\{evex\} vpinsrw \$0x0,%eax,%xmm0,%xmm0
+[ 	]*[a-f0-9]+:	62 f1 fd 08 c4 40 01 00 	\{evex\} vpinsrw \$0x0,0x2\(%eax\),%xmm0,%xmm0
 [ 	]*[a-f0-9]+:	62 f1 7e 0f 10 c0    	vmovss %xmm0,%xmm0,%xmm0\{%k7\}
 [ 	]*[a-f0-9]+:	62 f1 7e 0f 10 00    	vmovss \(%eax\),%xmm0\{%k7\}
 [ 	]*[a-f0-9]+:	62 f1 7e 0f 11 00    	vmovss %xmm0,\(%eax\)\{%k7\}

gas/testsuite/gas/i386/evex.d

@@ -16,6 +16,6 @@ Disassembly of section .text:
  +[a-f0-9]+:	62 f1 d6 38 7b f0    	vcvtusi2ssl %eax,\{rd-sae\},%xmm5,%xmm6
  +[a-f0-9]+:	62 f1 57 38 7b f0    	vcvtusi2sdl %eax,\{rd-bad\},%xmm5,%xmm6
  +[a-f0-9]+:	62 f1 d7 38 7b f0    	vcvtusi2sdl %eax,\{rd-bad\},%xmm5,%xmm6
- +[a-f0-9]+:	62 e1 7e 08 2d c0    	vcvtss2si %xmm0,%eax
+ +[a-f0-9]+:	62 e1 7e 08 2d c0    	\{evex\} vcvtss2si %xmm0,%eax
  +[a-f0-9]+:	62 e1 7c 08 c2 c0 00 	vcmpeqps %xmm0,%xmm0,%k0
 #pass

gas/testsuite/gas/i386/noreg16-data32.d

@@ -141,9 +141,9 @@ Disassembly of section .text:
  *[a-f0-9]+:	66 f7 07 89 00 00 00 	testl  \$0x89,\(%bx\)
  *[a-f0-9]+:	66 f7 07 34 12 00 00 	testl  \$0x1234,\(%bx\)
  *[a-f0-9]+:	c5 fb 2a 07          	vcvtsi2sd \(%bx\),%xmm0,%xmm0
- *[a-f0-9]+:	62 f1 7f 08 2a 07    	vcvtsi2sd \(%bx\),%xmm0,%xmm0
+ *[a-f0-9]+:	62 f1 7f 08 2a 07    	\{evex\} vcvtsi2sd \(%bx\),%xmm0,%xmm0
  *[a-f0-9]+:	c5 fa 2a 07          	vcvtsi2ss \(%bx\),%xmm0,%xmm0
- *[a-f0-9]+:	62 f1 7e 08 2a 07    	vcvtsi2ss \(%bx\),%xmm0,%xmm0
+ *[a-f0-9]+:	62 f1 7e 08 2a 07    	\{evex\} vcvtsi2ss \(%bx\),%xmm0,%xmm0
  *[a-f0-9]+:	62 f1 7f 08 7b 07    	vcvtusi2sd \(%bx\),%xmm0,%xmm0
  *[a-f0-9]+:	62 f1 7e 08 7b 07    	vcvtusi2ss \(%bx\),%xmm0,%xmm0
  *[a-f0-9]+:	66 83 37 01          	xorl   \$0x1,\(%bx\)

gas/testsuite/gas/i386/noreg16.d

@@ -140,9 +140,9 @@ Disassembly of section .text:
  *[a-f0-9]+:	f7 07 89 00          	testw  \$0x89,\(%bx\)
  *[a-f0-9]+:	f7 07 34 12          	testw  \$0x1234,\(%bx\)
  *[a-f0-9]+:	c5 fb 2a 07          	vcvtsi2sd \(%bx\),%xmm0,%xmm0
- *[a-f0-9]+:	62 f1 7f 08 2a 07    	vcvtsi2sd \(%bx\),%xmm0,%xmm0
+ *[a-f0-9]+:	62 f1 7f 08 2a 07    	\{evex\} vcvtsi2sd \(%bx\),%xmm0,%xmm0
  *[a-f0-9]+:	c5 fa 2a 07          	vcvtsi2ss \(%bx\),%xmm0,%xmm0
- *[a-f0-9]+:	62 f1 7e 08 2a 07    	vcvtsi2ss \(%bx\),%xmm0,%xmm0
+ *[a-f0-9]+:	62 f1 7e 08 2a 07    	\{evex\} vcvtsi2ss \(%bx\),%xmm0,%xmm0
  *[a-f0-9]+:	62 f1 7f 08 7b 07    	vcvtusi2sd \(%bx\),%xmm0,%xmm0
  *[a-f0-9]+:	62 f1 7e 08 7b 07    	vcvtusi2ss \(%bx\),%xmm0,%xmm0
  *[a-f0-9]+:	83 37 01             	xorw   \$0x1,\(%bx\)

gas/testsuite/gas/i386/noreg32-data16.d

@@ -151,9 +151,9 @@ Disassembly of section .text:
  *[a-f0-9]+:	66 f7 00 34 12       	testw  \$0x1234,\(%eax\)
  *[a-f0-9]+:	66 f7 00 78 56       	testw  \$0x5678,\(%eax\)
  *[a-f0-9]+:	c5 fb 2a 00          	vcvtsi2sd \(%eax\),%xmm0,%xmm0
- *[a-f0-9]+:	62 f1 7f 08 2a 00    	vcvtsi2sd \(%eax\),%xmm0,%xmm0
+ *[a-f0-9]+:	62 f1 7f 08 2a 00    	\{evex\} vcvtsi2sd \(%eax\),%xmm0,%xmm0
  *[a-f0-9]+:	c5 fa 2a 00          	vcvtsi2ss \(%eax\),%xmm0,%xmm0
- *[a-f0-9]+:	62 f1 7e 08 2a 00    	vcvtsi2ss \(%eax\),%xmm0,%xmm0
+ *[a-f0-9]+:	62 f1 7e 08 2a 00    	\{evex\} vcvtsi2ss \(%eax\),%xmm0,%xmm0
  *[a-f0-9]+:	62 f1 7f 08 7b 00    	vcvtusi2sd \(%eax\),%xmm0,%xmm0
  *[a-f0-9]+:	62 f1 7e 08 7b 00    	vcvtusi2ss \(%eax\),%xmm0,%xmm0
  *[a-f0-9]+:	66 83 30 01          	xorw   \$0x1,\(%eax\)

gas/testsuite/gas/i386/noreg32.d

@@ -149,9 +149,9 @@ Disassembly of section .text:
  *[a-f0-9]+:	f7 00 34 12 00 00    	testl  \$0x1234,\(%eax\)
  *[a-f0-9]+:	f7 00 78 56 34 12    	testl  \$0x12345678,\(%eax\)
  *[a-f0-9]+:	c5 fb 2a 00          	vcvtsi2sd \(%eax\),%xmm0,%xmm0
- *[a-f0-9]+:	62 f1 7f 08 2a 00    	vcvtsi2sd \(%eax\),%xmm0,%xmm0
+ *[a-f0-9]+:	62 f1 7f 08 2a 00    	\{evex\} vcvtsi2sd \(%eax\),%xmm0,%xmm0
  *[a-f0-9]+:	c5 fa 2a 00          	vcvtsi2ss \(%eax\),%xmm0,%xmm0
- *[a-f0-9]+:	62 f1 7e 08 2a 00    	vcvtsi2ss \(%eax\),%xmm0,%xmm0
+ *[a-f0-9]+:	62 f1 7e 08 2a 00    	\{evex\} vcvtsi2ss \(%eax\),%xmm0,%xmm0
  *[a-f0-9]+:	62 f1 7f 08 7b 00    	vcvtusi2sd \(%eax\),%xmm0,%xmm0
  *[a-f0-9]+:	62 f1 7e 08 7b 00    	vcvtusi2ss \(%eax\),%xmm0,%xmm0
  *[a-f0-9]+:	83 30 01             	xorl   \$0x1,\(%eax\)

gas/testsuite/gas/i386/opcode-intel.d

@@ -601,7 +601,7 @@ Disassembly of section .text:
  +[a-f0-9]+:	82 eb 01             	sub    bl,0x1
  +[a-f0-9]+:	82 f3 01             	xor    bl,0x1
  +[a-f0-9]+:	82 fb 01             	cmp    bl,0x1
- +[a-f0-9]+:	62 f3 7d 08 15 e8 ab 	vpextrw eax,xmm5,0xab
+ +[a-f0-9]+:	62 f3 7d 08 15 e8 ab 	\{evex\} vpextrw eax,xmm5,0xab
  +[a-f0-9]+:	f6 c9 01             	test   cl,(0x)?0*1
  +[a-f0-9]+:	66 f7 c9 02 00       	test   cx,(0x)?0*2
  +[a-f0-9]+:	f7 c9 04 00 00 00    	test   ecx,(0x)?0*4

gas/testsuite/gas/i386/opcode-suffix.d

@@ -601,5 +601,5 @@ Disassembly of section .text:
  +[a-f0-9]+:	82 eb 01             	subb   \$0x1,%bl
  +[a-f0-9]+:	82 f3 01             	xorb   \$0x1,%bl
  +[a-f0-9]+:	82 fb 01             	cmpb   \$0x1,%bl
- +[a-f0-9]+:	62 f3 7d 08 15 e8 ab 	vpextrw \$0xab,%xmm5,%eax
+ +[a-f0-9]+:	62 f3 7d 08 15 e8 ab 	\{evex\} vpextrw \$0xab,%xmm5,%eax
 #pass

gas/testsuite/gas/i386/opcode.d

@@ -600,7 +600,7 @@ Disassembly of section .text:
  +[a-f0-9]+:	82 eb 01             	sub    \$0x1,%bl
  +[a-f0-9]+:	82 f3 01             	xor    \$0x1,%bl
  +[a-f0-9]+:	82 fb 01             	cmp    \$0x1,%bl
- +[a-f0-9]+:	62 f3 7d 08 15 e8 ab 	vpextrw \$0xab,%xmm5,%eax
+ +[a-f0-9]+:	62 f3 7d 08 15 e8 ab 	\{evex\} vpextrw \$0xab,%xmm5,%eax
  +[a-f0-9]+:	f6 c9 01             	test   \$(0x)?0*1,%cl
  +[a-f0-9]+:	66 f7 c9 02 00       	test   \$(0x)?0*2,%cx
  +[a-f0-9]+:	f7 c9 04 00 00 00    	test   \$(0x)?0*4,%ecx

gas/testsuite/gas/i386/optimize-4.d

@@ -147,6 +147,6 @@ Disassembly of section .text:
  +[a-f0-9]+:	62 .*	vporq  0x80\(%eax\),%ymm2,%ymm3
  +[a-f0-9]+:	62 .*	vpxord 0x80\(%eax\),%ymm2,%ymm3
  +[a-f0-9]+:	62 .*	vpxorq 0x80\(%eax\),%ymm2,%ymm3
- +[a-f0-9]+:	62 f1 f5 08 55 e9    	vandnpd %xmm1,%xmm1,%xmm5
- +[a-f0-9]+:	62 f1 f5 08 55 e9    	vandnpd %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	62 f1 f5 08 55 e9    	\{evex\} vandnpd %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	62 f1 f5 08 55 e9    	\{evex\} vandnpd %xmm1,%xmm1,%xmm5
 #pass

gas/testsuite/gas/i386/optimize-5.d

@@ -147,8 +147,8 @@ Disassembly of section .text:
  +[a-f0-9]+:	62 .*	vporq  0x80\(%eax\),%ymm2,%ymm3
  +[a-f0-9]+:	62 .*	vpxord 0x80\(%eax\),%ymm2,%ymm3
  +[a-f0-9]+:	62 .*	vpxorq 0x80\(%eax\),%ymm2,%ymm3
- +[a-f0-9]+:	62 f1 f5 08 55 e9    	vandnpd %xmm1,%xmm1,%xmm5
- +[a-f0-9]+:	62 f1 f5 08 55 e9    	vandnpd %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	62 f1 f5 08 55 e9    	\{evex\} vandnpd %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	62 f1 f5 08 55 e9    	\{evex\} vandnpd %xmm1,%xmm1,%xmm5
  +[a-f0-9]+:	62 f1 7d 28 6f d1    	vmovdqa32 %ymm1,%ymm2
  +[a-f0-9]+:	62 f1 fd 28 6f d1    	vmovdqa64 %ymm1,%ymm2
  +[a-f0-9]+:	62 f1 7f 08 6f d1    	vmovdqu8 %xmm1,%xmm2

gas/testsuite/gas/i386/prefix.d

@@ -89,7 +89,7 @@ Disassembly of section .text:
 [ 	]*[a-f0-9]+:	66 c5 f8 28 c0       	data16 vmovaps %xmm0,%xmm0
 [ 	]*[a-f0-9]+:	f3 c4 e1 78 28 c0    	repz vmovaps %xmm0,%xmm0
 [ 	]*[a-f0-9]+:	f2 c5 f8 28 c0       	repnz vmovaps %xmm0,%xmm0
-[ 	]*[a-f0-9]+:	f0 62 f1 7c 08 28 c0 	lock vmovaps %xmm0,%xmm0
+[ 	]*[a-f0-9]+:	f0 62 f1 7c 08 28 c0 	lock \{evex\} vmovaps %xmm0,%xmm0
 [ 	]*[a-f0-9]+:	c5 fb e6 40 20       	vcvtpd2dqx 0x20\(%eax\),%xmm0
 [ 	]*[a-f0-9]+:	62 f1 ff 18 e6 40 04 	vcvtpd2dq 0x20\(%eax\)\{1to2\},%xmm0
 [ 	]*[a-f0-9]+:	c5 fb e6 40 20       	vcvtpd2dqx 0x20\(%eax\),%xmm0

gas/testsuite/gas/i386/pseudos.d

@@ -18,15 +18,15 @@ Disassembly of section .text:
  +[a-f0-9]+:	c4 e1 78 28 10       	vmovaps \(%eax\),%xmm2
  +[a-f0-9]+:	c5 f8 28 10          	vmovaps \(%eax\),%xmm2
  +[a-f0-9]+:	c5 f8 28 10          	vmovaps \(%eax\),%xmm2
- +[a-f0-9]+:	62 f1 7c 08 28 10    	vmovaps \(%eax\),%xmm2
+ +[a-f0-9]+:	62 f1 7c 08 28 10    	\{evex\} vmovaps \(%eax\),%xmm2
  +[a-f0-9]+:	c5 f8 28 90 00 00 00 00 	vmovaps 0x0\(%eax\),%xmm2
- +[a-f0-9]+:	62 f1 7c 08 28 50 00 	vmovaps 0x0\(%eax\),%xmm2
- +[a-f0-9]+:	62 f1 7c 08 28 90 00 00 00 00 	vmovaps 0x0\(%eax\),%xmm2
+ +[a-f0-9]+:	62 f1 7c 08 28 50 00 	\{evex\} vmovaps 0x0\(%eax\),%xmm2
+ +[a-f0-9]+:	62 f1 7c 08 28 90 00 00 00 00 	\{evex\} vmovaps 0x0\(%eax\),%xmm2
  +[a-f0-9]+:	c5 f8 28 90 80 00 00 00 	vmovaps 0x80\(%eax\),%xmm2
  +[a-f0-9]+:	c5 f8 28 90 80 00 00 00 	vmovaps 0x80\(%eax\),%xmm2
- +[a-f0-9]+:	62 f1 7c 08 28 50 08 	vmovaps 0x80\(%eax\),%xmm2
- +[a-f0-9]+:	67 62 f1 7c 08 28 97 80 00 	vmovaps 0x80\(%bx\),%xmm2
- +[a-f0-9]+:	62 f1 7c 08 28 90 80 00 00 00 	vmovaps 0x80\(%eax\),%xmm2
+ +[a-f0-9]+:	62 f1 7c 08 28 50 08 	\{evex\} vmovaps 0x80\(%eax\),%xmm2
+ +[a-f0-9]+:	67 62 f1 7c 08 28 97 80 00 	\{evex\} vmovaps 0x80\(%bx\),%xmm2
+ +[a-f0-9]+:	62 f1 7c 08 28 90 80 00 00 00 	\{evex\} vmovaps 0x80\(%eax\),%xmm2
  +[a-f0-9]+:	89 c8                	mov    %ecx,%eax
  +[a-f0-9]+:	8b c1                	mov    %ecx,%eax
  +[a-f0-9]+:	89 c8                	mov    %ecx,%eax
@@ -267,18 +267,18 @@ Disassembly of section .text:
  +[a-f0-9]+:	c5 fa 7e f8          	vmovq  %xmm0,%xmm7
  +[a-f0-9]+:	c5 fa 7e f8          	vmovq  %xmm0,%xmm7
  +[a-f0-9]+:	c5 f9 d6 c7          	vmovq  %xmm0,%xmm7
- +[a-f0-9]+:	62 f1 fe 08 7e f8    	vmovq  %xmm0,%xmm7
- +[a-f0-9]+:	62 f1 fe 08 7e f8    	vmovq  %xmm0,%xmm7
- +[a-f0-9]+:	62 f1 fd 08 d6 c7    	vmovq  %xmm0,%xmm7
+ +[a-f0-9]+:	62 f1 fe 08 7e f8    	\{evex\} vmovq %xmm0,%xmm7
+ +[a-f0-9]+:	62 f1 fe 08 7e f8    	\{evex\} vmovq %xmm0,%xmm7
+ +[a-f0-9]+:	62 f1 fd 08 d6 c7    	\{evex\} vmovq %xmm0,%xmm7
  +[a-f0-9]+:	66 0f c5 f8 00       	pextrw \$0x0,%xmm0,%edi
  +[a-f0-9]+:	66 0f c5 f8 00       	pextrw \$0x0,%xmm0,%edi
  +[a-f0-9]+:	66 0f 3a 15 c7 00    	pextrw \$0x0,%xmm0,%edi
  +[a-f0-9]+:	c5 f9 c5 f8 00       	vpextrw \$0x0,%xmm0,%edi
  +[a-f0-9]+:	c5 f9 c5 f8 00       	vpextrw \$0x0,%xmm0,%edi
  +[a-f0-9]+:	c4 e3 79 15 c7 00    	vpextrw \$0x0,%xmm0,%edi
- +[a-f0-9]+:	62 f1 7d 08 c5 f8 00 	vpextrw \$0x0,%xmm0,%edi
- +[a-f0-9]+:	62 f1 7d 08 c5 f8 00 	vpextrw \$0x0,%xmm0,%edi
- +[a-f0-9]+:	62 f3 7d 08 15 c7 00 	vpextrw \$0x0,%xmm0,%edi
+ +[a-f0-9]+:	62 f1 7d 08 c5 f8 00 	\{evex\} vpextrw \$0x0,%xmm0,%edi
+ +[a-f0-9]+:	62 f1 7d 08 c5 f8 00 	\{evex\} vpextrw \$0x0,%xmm0,%edi
+ +[a-f0-9]+:	62 f3 7d 08 15 c7 00 	\{evex\} vpextrw \$0x0,%xmm0,%edi
  +[a-f0-9]+:	66 0f 1a c3          	bndmov %bnd3,%bnd0
  +[a-f0-9]+:	66 0f 1a c3          	bndmov %bnd3,%bnd0
  +[a-f0-9]+:	66 0f 1b d8          	bndmov %bnd3,%bnd0
@@ -318,15 +318,15 @@ Disassembly of section .text:
  +[a-f0-9]+:	c4 e1 78 28 10       	vmovaps \(%eax\),%xmm2
  +[a-f0-9]+:	c5 f8 28 10          	vmovaps \(%eax\),%xmm2
  +[a-f0-9]+:	c5 f8 28 10          	vmovaps \(%eax\),%xmm2
- +[a-f0-9]+:	62 f1 7c 08 28 10    	vmovaps \(%eax\),%xmm2
+ +[a-f0-9]+:	62 f1 7c 08 28 10    	\{evex\} vmovaps \(%eax\),%xmm2
  +[a-f0-9]+:	c5 f8 28 90 00 00 00 00 	vmovaps 0x0\(%eax\),%xmm2
- +[a-f0-9]+:	62 f1 7c 08 28 50 00 	vmovaps 0x0\(%eax\),%xmm2
- +[a-f0-9]+:	62 f1 7c 08 28 90 00 00 00 00 	vmovaps 0x0\(%eax\),%xmm2
+ +[a-f0-9]+:	62 f1 7c 08 28 50 00 	\{evex\} vmovaps 0x0\(%eax\),%xmm2
+ +[a-f0-9]+:	62 f1 7c 08 28 90 00 00 00 00 	\{evex\} vmovaps 0x0\(%eax\),%xmm2
  +[a-f0-9]+:	c5 f8 28 90 80 00 00 00 	vmovaps 0x80\(%eax\),%xmm2
  +[a-f0-9]+:	c5 f8 28 90 80 00 00 00 	vmovaps 0x80\(%eax\),%xmm2
- +[a-f0-9]+:	62 f1 7c 08 28 50 08 	vmovaps 0x80\(%eax\),%xmm2
- +[a-f0-9]+:	67 62 f1 7c 08 28 97 80 00 	vmovaps 0x80\(%bx\),%xmm2
- +[a-f0-9]+:	62 f1 7c 08 28 90 80 00 00 00 	vmovaps 0x80\(%eax\),%xmm2
+ +[a-f0-9]+:	62 f1 7c 08 28 50 08 	\{evex\} vmovaps 0x80\(%eax\),%xmm2
+ +[a-f0-9]+:	67 62 f1 7c 08 28 97 80 00 	\{evex\} vmovaps 0x80\(%bx\),%xmm2
+ +[a-f0-9]+:	62 f1 7c 08 28 90 80 00 00 00 	\{evex\} vmovaps 0x80\(%eax\),%xmm2
  +[a-f0-9]+:	89 c8                	mov    %ecx,%eax
  +[a-f0-9]+:	8b c1                	mov    %ecx,%eax
  +[a-f0-9]+:	89 c8                	mov    %ecx,%eax

gas/testsuite/gas/i386/x86-64-evex-lig-2.d

@@ -8,34 +8,34 @@
 Disassembly of section .text:
 
 0+ <_start>:
- +[a-f0-9]+:	62 f1 7d 08 7e 21    	vmovd  %xmm4,\(%rcx\)
- +[a-f0-9]+:	62 f1 7d 08 7e e1    	vmovd  %xmm4,%ecx
- +[a-f0-9]+:	62 f1 7d 08 6e 21    	vmovd  \(%rcx\),%xmm4
- +[a-f0-9]+:	62 f1 7d 08 6e e1    	vmovd  %ecx,%xmm4
- +[a-f0-9]+:	62 f1 fd 08 7e 21    	vmovq  %xmm4,\(%rcx\)
- +[a-f0-9]+:	62 f1 fd 08 7e e1    	vmovq  %xmm4,%rcx
- +[a-f0-9]+:	62 f1 fd 08 6e 21    	vmovq  \(%rcx\),%xmm4
- +[a-f0-9]+:	62 f1 fd 08 6e e1    	vmovq  %rcx,%xmm4
- +[a-f0-9]+:	62 f1 fe 08 7e f4    	vmovq  %xmm4,%xmm6
- +[a-f0-9]+:	62 f3 7d 08 17 c0 00 	vextractps \$0x0,%xmm0,%eax
- +[a-f0-9]+:	62 f3 7d 08 17 00 00 	vextractps \$0x0,%xmm0,\(%rax\)
- +[a-f0-9]+:	62 f3 7d 08 14 c0 00 	vpextrb \$0x0,%xmm0,%eax
- +[a-f0-9]+:	62 f3 7d 08 14 00 00 	vpextrb \$0x0,%xmm0,\(%rax\)
- +[a-f0-9]+:	62 f1 7d 08 c5 c0 00 	vpextrw \$0x0,%xmm0,%eax
- +[a-f0-9]+:	62 f3 7d 08 15 c0 00 	vpextrw \$0x0,%xmm0,%eax
- +[a-f0-9]+:	62 f3 7d 08 15 00 00 	vpextrw \$0x0,%xmm0,\(%rax\)
- +[a-f0-9]+:	62 f3 7d 08 16 c0 00 	vpextrd \$0x0,%xmm0,%eax
- +[a-f0-9]+:	62 f3 7d 08 16 00 00 	vpextrd \$0x0,%xmm0,\(%rax\)
- +[a-f0-9]+:	62 f3 fd 08 16 c0 00 	vpextrq \$0x0,%xmm0,%rax
- +[a-f0-9]+:	62 f3 fd 08 16 00 00 	vpextrq \$0x0,%xmm0,\(%rax\)
- +[a-f0-9]+:	62 f3 7d 08 21 c0 00 	vinsertps \$0x0,%xmm0,%xmm0,%xmm0
- +[a-f0-9]+:	62 f3 7d 08 21 00 00 	vinsertps \$0x0,\(%rax\),%xmm0,%xmm0
- +[a-f0-9]+:	62 f3 7d 08 20 c0 00 	vpinsrb \$0x0,%eax,%xmm0,%xmm0
- +[a-f0-9]+:	62 f3 7d 08 20 00 00 	vpinsrb \$0x0,\(%rax\),%xmm0,%xmm0
- +[a-f0-9]+:	62 f1 7d 08 c4 c0 00 	vpinsrw \$0x0,%eax,%xmm0,%xmm0
- +[a-f0-9]+:	62 f1 7d 08 c4 00 00 	vpinsrw \$0x0,\(%rax\),%xmm0,%xmm0
- +[a-f0-9]+:	62 f3 7d 08 22 c0 00 	vpinsrd \$0x0,%eax,%xmm0,%xmm0
- +[a-f0-9]+:	62 f3 7d 08 22 00 00 	vpinsrd \$0x0,\(%rax\),%xmm0,%xmm0
- +[a-f0-9]+:	62 f3 fd 08 22 c0 00 	vpinsrq \$0x0,%rax,%xmm0,%xmm0
- +[a-f0-9]+:	62 f3 fd 08 22 00 00 	vpinsrq \$0x0,\(%rax\),%xmm0,%xmm0
+ +[a-f0-9]+:	62 f1 7d 08 7e 21    	\{evex\} vmovd %xmm4,\(%rcx\)
+ +[a-f0-9]+:	62 f1 7d 08 7e e1    	\{evex\} vmovd %xmm4,%ecx
+ +[a-f0-9]+:	62 f1 7d 08 6e 21    	\{evex\} vmovd \(%rcx\),%xmm4
+ +[a-f0-9]+:	62 f1 7d 08 6e e1    	\{evex\} vmovd %ecx,%xmm4
+ +[a-f0-9]+:	62 f1 fd 08 7e 21    	\{evex\} vmovq %xmm4,\(%rcx\)
+ +[a-f0-9]+:	62 f1 fd 08 7e e1    	\{evex\} vmovq %xmm4,%rcx
+ +[a-f0-9]+:	62 f1 fd 08 6e 21    	\{evex\} vmovq \(%rcx\),%xmm4
+ +[a-f0-9]+:	62 f1 fd 08 6e e1    	\{evex\} vmovq %rcx,%xmm4
+ +[a-f0-9]+:	62 f1 fe 08 7e f4    	\{evex\} vmovq %xmm4,%xmm6
+ +[a-f0-9]+:	62 f3 7d 08 17 c0 00 	\{evex\} vextractps \$0x0,%xmm0,%eax
+ +[a-f0-9]+:	62 f3 7d 08 17 00 00 	\{evex\} vextractps \$0x0,%xmm0,\(%rax\)
+ +[a-f0-9]+:	62 f3 7d 08 14 c0 00 	\{evex\} vpextrb \$0x0,%xmm0,%eax
+ +[a-f0-9]+:	62 f3 7d 08 14 00 00 	\{evex\} vpextrb \$0x0,%xmm0,\(%rax\)
+ +[a-f0-9]+:	62 f1 7d 08 c5 c0 00 	\{evex\} vpextrw \$0x0,%xmm0,%eax
+ +[a-f0-9]+:	62 f3 7d 08 15 c0 00 	\{evex\} vpextrw \$0x0,%xmm0,%eax
+ +[a-f0-9]+:	62 f3 7d 08 15 00 00 	\{evex\} vpextrw \$0x0,%xmm0,\(%rax\)
+ +[a-f0-9]+:	62 f3 7d 08 16 c0 00 	\{evex\} vpextrd \$0x0,%xmm0,%eax
+ +[a-f0-9]+:	62 f3 7d 08 16 00 00 	\{evex\} vpextrd \$0x0,%xmm0,\(%rax\)
+ +[a-f0-9]+:	62 f3 fd 08 16 c0 00 	\{evex\} vpextrq \$0x0,%xmm0,%rax
+ +[a-f0-9]+:	62 f3 fd 08 16 00 00 	\{evex\} vpextrq \$0x0,%xmm0,\(%rax\)
+ +[a-f0-9]+:	62 f3 7d 08 21 c0 00 	\{evex\} vinsertps \$0x0,%xmm0,%xmm0,%xmm0
+ +[a-f0-9]+:	62 f3 7d 08 21 00 00 	\{evex\} vinsertps \$0x0,\(%rax\),%xmm0,%xmm0
+ +[a-f0-9]+:	62 f3 7d 08 20 c0 00 	\{evex\} vpinsrb \$0x0,%eax,%xmm0,%xmm0
+ +[a-f0-9]+:	62 f3 7d 08 20 00 00 	\{evex\} vpinsrb \$0x0,\(%rax\),%xmm0,%xmm0
+ +[a-f0-9]+:	62 f1 7d 08 c4 c0 00 	\{evex\} vpinsrw \$0x0,%eax,%xmm0,%xmm0
+ +[a-f0-9]+:	62 f1 7d 08 c4 00 00 	\{evex\} vpinsrw \$0x0,\(%rax\),%xmm0,%xmm0
+ +[a-f0-9]+:	62 f3 7d 08 22 c0 00 	\{evex\} vpinsrd \$0x0,%eax,%xmm0,%xmm0
+ +[a-f0-9]+:	62 f3 7d 08 22 00 00 	\{evex\} vpinsrd \$0x0,\(%rax\),%xmm0,%xmm0
+ +[a-f0-9]+:	62 f3 fd 08 22 c0 00 	\{evex\} vpinsrq \$0x0,%rax,%xmm0,%xmm0
+ +[a-f0-9]+:	62 f3 fd 08 22 00 00 	\{evex\} vpinsrq \$0x0,\(%rax\),%xmm0,%xmm0
 #pass

gas/testsuite/gas/i386/x86-64-evex-wig1-intel.d

@@ -18,15 +18,15 @@ Disassembly of section .text:
 [ 	]*[a-f0-9]+:	62 63 fd 08 17 aa 00 02 00 00 7b 	vextractps DWORD PTR \[rdx\+0x200\],xmm29,0x7b
 [ 	]*[a-f0-9]+:	62 63 fd 08 17 6a 80 7b 	vextractps DWORD PTR \[rdx-0x200\],xmm29,0x7b
 [ 	]*[a-f0-9]+:	62 63 fd 08 17 aa fc fd ff ff 7b 	vextractps DWORD PTR \[rdx-0x204\],xmm29,0x7b
-[ 	]*[a-f0-9]+:	62 f3 fd 08 14 c0 00 	vpextrb eax,xmm0,0x0
-[ 	]*[a-f0-9]+:	62 f3 fd 08 14 00 00 	vpextrb BYTE PTR \[rax\],xmm0,0x0
-[ 	]*[a-f0-9]+:	62 f1 fd 08 c5 c0 00 	vpextrw eax,xmm0,0x0
-[ 	]*[a-f0-9]+:	62 f3 fd 08 15 c0 00 	vpextrw eax,xmm0,0x0
-[ 	]*[a-f0-9]+:	62 f3 fd 08 15 00 00 	vpextrw WORD PTR \[rax\],xmm0,0x0
-[ 	]*[a-f0-9]+:	62 f3 fd 08 20 c0 00 	vpinsrb xmm0,xmm0,eax,0x0
-[ 	]*[a-f0-9]+:	62 f3 fd 08 20 00 00 	vpinsrb xmm0,xmm0,BYTE PTR \[rax\],0x0
-[ 	]*[a-f0-9]+:	62 f1 fd 08 c4 c0 00 	vpinsrw xmm0,xmm0,eax,0x0
-[ 	]*[a-f0-9]+:	62 f1 fd 08 c4 00 00 	vpinsrw xmm0,xmm0,WORD PTR \[rax\],0x0
+[ 	]*[a-f0-9]+:	62 f3 fd 08 14 c0 00 	\{evex\} vpextrb eax,xmm0,0x0
+[ 	]*[a-f0-9]+:	62 f3 fd 08 14 00 00 	\{evex\} vpextrb BYTE PTR \[rax\],xmm0,0x0
+[ 	]*[a-f0-9]+:	62 f1 fd 08 c5 c0 00 	\{evex\} vpextrw eax,xmm0,0x0
+[ 	]*[a-f0-9]+:	62 f3 fd 08 15 c0 00 	\{evex\} vpextrw eax,xmm0,0x0
+[ 	]*[a-f0-9]+:	62 f3 fd 08 15 00 00 	\{evex\} vpextrw WORD PTR \[rax\],xmm0,0x0
+[ 	]*[a-f0-9]+:	62 f3 fd 08 20 c0 00 	\{evex\} vpinsrb xmm0,xmm0,eax,0x0
+[ 	]*[a-f0-9]+:	62 f3 fd 08 20 00 00 	\{evex\} vpinsrb xmm0,xmm0,BYTE PTR \[rax\],0x0
+[ 	]*[a-f0-9]+:	62 f1 fd 08 c4 c0 00 	\{evex\} vpinsrw xmm0,xmm0,eax,0x0
+[ 	]*[a-f0-9]+:	62 f1 fd 08 c4 00 00 	\{evex\} vpinsrw xmm0,xmm0,WORD PTR \[rax\],0x0
 [ 	]*[a-f0-9]+:	62 02 fd 4f 21 f5    	vpmovsxbd zmm30\{k7\},xmm29
 [ 	]*[a-f0-9]+:	62 02 fd cf 21 f5    	vpmovsxbd zmm30\{k7\}\{z\},xmm29
 [ 	]*[a-f0-9]+:	62 62 fd 4f 21 31    	vpmovsxbd zmm30\{k7\},XMMWORD PTR \[rcx\]

gas/testsuite/gas/i386/x86-64-evex-wig1.d

@@ -18,15 +18,15 @@ Disassembly of section .text:
 [ 	]*[a-f0-9]+:	62 63 fd 08 17 aa 00 02 00 00 7b 	vextractps \$0x7b,%xmm29,0x200\(%rdx\)
 [ 	]*[a-f0-9]+:	62 63 fd 08 17 6a 80 7b 	vextractps \$0x7b,%xmm29,-0x200\(%rdx\)
 [ 	]*[a-f0-9]+:	62 63 fd 08 17 aa fc fd ff ff 7b 	vextractps \$0x7b,%xmm29,-0x204\(%rdx\)
-[ 	]*[a-f0-9]+:	62 f3 fd 08 14 c0 00 	vpextrb \$0x0,%xmm0,%eax
-[ 	]*[a-f0-9]+:	62 f3 fd 08 14 00 00 	vpextrb \$0x0,%xmm0,\(%rax\)
-[ 	]*[a-f0-9]+:	62 f1 fd 08 c5 c0 00 	vpextrw \$0x0,%xmm0,%eax
-[ 	]*[a-f0-9]+:	62 f3 fd 08 15 c0 00 	vpextrw \$0x0,%xmm0,%eax
-[ 	]*[a-f0-9]+:	62 f3 fd 08 15 00 00 	vpextrw \$0x0,%xmm0,\(%rax\)
-[ 	]*[a-f0-9]+:	62 f3 fd 08 20 c0 00 	vpinsrb \$0x0,%eax,%xmm0,%xmm0
-[ 	]*[a-f0-9]+:	62 f3 fd 08 20 00 00 	vpinsrb \$0x0,\(%rax\),%xmm0,%xmm0
-[ 	]*[a-f0-9]+:	62 f1 fd 08 c4 c0 00 	vpinsrw \$0x0,%eax,%xmm0,%xmm0
-[ 	]*[a-f0-9]+:	62 f1 fd 08 c4 00 00 	vpinsrw \$0x0,\(%rax\),%xmm0,%xmm0
+[ 	]*[a-f0-9]+:	62 f3 fd 08 14 c0 00 	\{evex\} vpextrb \$0x0,%xmm0,%eax
+[ 	]*[a-f0-9]+:	62 f3 fd 08 14 00 00 	\{evex\} vpextrb \$0x0,%xmm0,\(%rax\)
+[ 	]*[a-f0-9]+:	62 f1 fd 08 c5 c0 00 	\{evex\} vpextrw \$0x0,%xmm0,%eax
+[ 	]*[a-f0-9]+:	62 f3 fd 08 15 c0 00 	\{evex\} vpextrw \$0x0,%xmm0,%eax
+[ 	]*[a-f0-9]+:	62 f3 fd 08 15 00 00 	\{evex\} vpextrw \$0x0,%xmm0,\(%rax\)
+[ 	]*[a-f0-9]+:	62 f3 fd 08 20 c0 00 	\{evex\} vpinsrb \$0x0,%eax,%xmm0,%xmm0
+[ 	]*[a-f0-9]+:	62 f3 fd 08 20 00 00 	\{evex\} vpinsrb \$0x0,\(%rax\),%xmm0,%xmm0
+[ 	]*[a-f0-9]+:	62 f1 fd 08 c4 c0 00 	\{evex\} vpinsrw \$0x0,%eax,%xmm0,%xmm0
+[ 	]*[a-f0-9]+:	62 f1 fd 08 c4 00 00 	\{evex\} vpinsrw \$0x0,\(%rax\),%xmm0,%xmm0
 [ 	]*[a-f0-9]+:	62 02 fd 4f 21 f5    	vpmovsxbd %xmm29,%zmm30\{%k7\}
 [ 	]*[a-f0-9]+:	62 02 fd cf 21 f5    	vpmovsxbd %xmm29,%zmm30\{%k7\}\{z\}
 [ 	]*[a-f0-9]+:	62 62 fd 4f 21 31    	vpmovsxbd \(%rcx\),%zmm30\{%k7\}

gas/testsuite/gas/i386/x86-64-movd-intel.d

@@ -16,8 +16,8 @@ Disassembly of section .text:
  +[a-f0-9]+:	c4 e1 f9 6e c8       	vmovq  xmm1,rax
  +[a-f0-9]+:	c5 f9 7e 88 80 00 00 00 	vmovd  DWORD PTR \[rax\+0x80\],xmm1
  +[a-f0-9]+:	c4 e1 f9 7e c8       	vmovq  rax,xmm1
- +[a-f0-9]+:	62 f1 7d 08 6e 48 20 	vmovd  xmm1,DWORD PTR \[rax\+0x80\]
- +[a-f0-9]+:	62 f1 7d 08 7e 48 20 	vmovd  DWORD PTR \[rax\+0x80\],xmm1
+ +[a-f0-9]+:	62 f1 7d 08 6e 48 20 	\{evex\} vmovd xmm1,DWORD PTR \[rax\+0x80\]
+ +[a-f0-9]+:	62 f1 7d 08 7e 48 20 	\{evex\} vmovd DWORD PTR \[rax\+0x80\],xmm1
  +[a-f0-9]+:	66 0f 6e 88 80 00 00 00 	movd   xmm1,DWORD PTR \[rax\+0x80\]
  +[a-f0-9]+:	66 0f 6e 88 80 00 00 00 	movd   xmm1,DWORD PTR \[rax\+0x80\]
  +[a-f0-9]+:	66 0f 6e c8          	movd   xmm1,eax
@@ -34,12 +34,12 @@ Disassembly of section .text:
  +[a-f0-9]+:	c5 f9 7e 88 80 00 00 00 	vmovd  DWORD PTR \[rax\+0x80\],xmm1
  +[a-f0-9]+:	c5 f9 7e 88 80 00 00 00 	vmovd  DWORD PTR \[rax\+0x80\],xmm1
  +[a-f0-9]+:	c5 f9 7e c8          	vmovd  eax,xmm1
- +[a-f0-9]+:	62 f1 7d 08 6e 48 20 	vmovd  xmm1,DWORD PTR \[rax\+0x80\]
- +[a-f0-9]+:	62 f1 7d 08 6e 48 20 	vmovd  xmm1,DWORD PTR \[rax\+0x80\]
- +[a-f0-9]+:	62 f1 7d 08 6e c8    	vmovd  xmm1,eax
- +[a-f0-9]+:	62 f1 7d 08 7e 48 20 	vmovd  DWORD PTR \[rax\+0x80\],xmm1
- +[a-f0-9]+:	62 f1 7d 08 7e 48 20 	vmovd  DWORD PTR \[rax\+0x80\],xmm1
- +[a-f0-9]+:	62 f1 7d 08 7e c8    	vmovd  eax,xmm1
+ +[a-f0-9]+:	62 f1 7d 08 6e 48 20 	\{evex\} vmovd xmm1,DWORD PTR \[rax\+0x80\]
+ +[a-f0-9]+:	62 f1 7d 08 6e 48 20 	\{evex\} vmovd xmm1,DWORD PTR \[rax\+0x80\]
+ +[a-f0-9]+:	62 f1 7d 08 6e c8    	\{evex\} vmovd xmm1,eax
+ +[a-f0-9]+:	62 f1 7d 08 7e 48 20 	\{evex\} vmovd DWORD PTR \[rax\+0x80\],xmm1
+ +[a-f0-9]+:	62 f1 7d 08 7e 48 20 	\{evex\} vmovd DWORD PTR \[rax\+0x80\],xmm1
+ +[a-f0-9]+:	62 f1 7d 08 7e c8    	\{evex\} vmovd eax,xmm1
  +[a-f0-9]+:	c4 e1 f9 6e c8       	vmovq  xmm1,rax
  +[a-f0-9]+:	c4 e1 f9 7e c8       	vmovq  rax,xmm1
 #pass

gas/testsuite/gas/i386/x86-64-movd.d

@@ -15,8 +15,8 @@ Disassembly of section .text:
  +[a-f0-9]+:	c4 e1 f9 6e c8       	vmovq  %rax,%xmm1
  +[a-f0-9]+:	c5 f9 7e 88 80 00 00 00 	vmovd  %xmm1,0x80\(%rax\)
  +[a-f0-9]+:	c4 e1 f9 7e c8       	vmovq  %xmm1,%rax
- +[a-f0-9]+:	62 f1 7d 08 6e 48 20 	vmovd  0x80\(%rax\),%xmm1
- +[a-f0-9]+:	62 f1 7d 08 7e 48 20 	vmovd  %xmm1,0x80\(%rax\)
+ +[a-f0-9]+:	62 f1 7d 08 6e 48 20 	\{evex\} vmovd 0x80\(%rax\),%xmm1
+ +[a-f0-9]+:	62 f1 7d 08 7e 48 20 	\{evex\} vmovd %xmm1,0x80\(%rax\)
  +[a-f0-9]+:	66 0f 6e 88 80 00 00 00 	movd   0x80\(%rax\),%xmm1
  +[a-f0-9]+:	66 0f 6e 88 80 00 00 00 	movd   0x80\(%rax\),%xmm1
  +[a-f0-9]+:	66 0f 6e c8          	movd   %eax,%xmm1
@@ -33,12 +33,12 @@ Disassembly of section .text:
  +[a-f0-9]+:	c5 f9 7e 88 80 00 00 00 	vmovd  %xmm1,0x80\(%rax\)
  +[a-f0-9]+:	c5 f9 7e 88 80 00 00 00 	vmovd  %xmm1,0x80\(%rax\)
  +[a-f0-9]+:	c5 f9 7e c8          	vmovd  %xmm1,%eax
- +[a-f0-9]+:	62 f1 7d 08 6e 48 20 	vmovd  0x80\(%rax\),%xmm1
- +[a-f0-9]+:	62 f1 7d 08 6e 48 20 	vmovd  0x80\(%rax\),%xmm1
- +[a-f0-9]+:	62 f1 7d 08 6e c8    	vmovd  %eax,%xmm1
- +[a-f0-9]+:	62 f1 7d 08 7e 48 20 	vmovd  %xmm1,0x80\(%rax\)
- +[a-f0-9]+:	62 f1 7d 08 7e 48 20 	vmovd  %xmm1,0x80\(%rax\)
- +[a-f0-9]+:	62 f1 7d 08 7e c8    	vmovd  %xmm1,%eax
+ +[a-f0-9]+:	62 f1 7d 08 6e 48 20 	\{evex\} vmovd 0x80\(%rax\),%xmm1
+ +[a-f0-9]+:	62 f1 7d 08 6e 48 20 	\{evex\} vmovd 0x80\(%rax\),%xmm1
+ +[a-f0-9]+:	62 f1 7d 08 6e c8    	\{evex\} vmovd %eax,%xmm1
+ +[a-f0-9]+:	62 f1 7d 08 7e 48 20 	\{evex\} vmovd %xmm1,0x80\(%rax\)
+ +[a-f0-9]+:	62 f1 7d 08 7e 48 20 	\{evex\} vmovd %xmm1,0x80\(%rax\)
+ +[a-f0-9]+:	62 f1 7d 08 7e c8    	\{evex\} vmovd %xmm1,%eax
  +[a-f0-9]+:	c4 e1 f9 6e c8       	vmovq  %rax,%xmm1
  +[a-f0-9]+:	c4 e1 f9 7e c8       	vmovq  %xmm1,%rax
 #pass

gas/testsuite/gas/i386/x86-64-optimize-5.d

@@ -203,8 +203,8 @@ Disassembly of section .text:
  +[a-f0-9]+:	62 .*	vporq  0x80\(%rax\),%ymm2,%ymm3
  +[a-f0-9]+:	62 .*	vpxord 0x80\(%rax\),%ymm2,%ymm3
  +[a-f0-9]+:	62 .*	vpxorq 0x80\(%rax\),%ymm2,%ymm3
- +[a-f0-9]+:	62 f1 f5 08 55 e9    	vandnpd %xmm1,%xmm1,%xmm5
- +[a-f0-9]+:	62 f1 f5 08 55 e9    	vandnpd %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	62 f1 f5 08 55 e9    	\{evex\} vandnpd %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	62 f1 f5 08 55 e9    	\{evex\} vandnpd %xmm1,%xmm1,%xmm5
  +[a-f0-9]+:	62 f1 7d 28 6f d1    	vmovdqa32 %ymm1,%ymm2
  +[a-f0-9]+:	62 f1 fd 28 6f d1    	vmovdqa64 %ymm1,%ymm2
  +[a-f0-9]+:	62 f1 7f 08 6f d1    	vmovdqu8 %xmm1,%xmm2

gas/testsuite/gas/i386/x86-64-optimize-6.d

@@ -203,8 +203,8 @@ Disassembly of section .text:
  +[a-f0-9]+:	62 .*	vporq  0x80\(%rax\),%ymm2,%ymm3
  +[a-f0-9]+:	62 .*	vpxord 0x80\(%rax\),%ymm2,%ymm3
  +[a-f0-9]+:	62 .*	vpxorq 0x80\(%rax\),%ymm2,%ymm3
- +[a-f0-9]+:	62 f1 f5 08 55 e9    	vandnpd %xmm1,%xmm1,%xmm5
- +[a-f0-9]+:	62 f1 f5 08 55 e9    	vandnpd %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	62 f1 f5 08 55 e9    	\{evex\} vandnpd %xmm1,%xmm1,%xmm5
+ +[a-f0-9]+:	62 f1 f5 08 55 e9    	\{evex\} vandnpd %xmm1,%xmm1,%xmm5
  +[a-f0-9]+:	62 f1 7d 28 6f d1    	vmovdqa32 %ymm1,%ymm2
  +[a-f0-9]+:	62 f1 fd 28 6f d1    	vmovdqa64 %ymm1,%ymm2
  +[a-f0-9]+:	62 f1 7f 08 6f d1    	vmovdqu8 %xmm1,%xmm2

gas/testsuite/gas/i386/x86-64-pseudos.d

@@ -18,14 +18,14 @@ Disassembly of section .text:
  +[a-f0-9]+:	c4 e1 78 28 10       	vmovaps \(%rax\),%xmm2
  +[a-f0-9]+:	c5 f8 28 10          	vmovaps \(%rax\),%xmm2
  +[a-f0-9]+:	c5 f8 28 10          	vmovaps \(%rax\),%xmm2
- +[a-f0-9]+:	62 f1 7c 08 28 10    	vmovaps \(%rax\),%xmm2
+ +[a-f0-9]+:	62 f1 7c 08 28 10    	\{evex\} vmovaps \(%rax\),%xmm2
  +[a-f0-9]+:	c5 f8 28 90 00 00 00 00 	vmovaps 0x0\(%rax\),%xmm2
- +[a-f0-9]+:	62 f1 7c 08 28 50 00 	vmovaps 0x0\(%rax\),%xmm2
- +[a-f0-9]+:	62 f1 7c 08 28 90 00 00 00 00 	vmovaps 0x0\(%rax\),%xmm2
+ +[a-f0-9]+:	62 f1 7c 08 28 50 00 	\{evex\} vmovaps 0x0\(%rax\),%xmm2
+ +[a-f0-9]+:	62 f1 7c 08 28 90 00 00 00 00 	\{evex\} vmovaps 0x0\(%rax\),%xmm2
  +[a-f0-9]+:	c5 f8 28 90 80 00 00 00 	vmovaps 0x80\(%rax\),%xmm2
  +[a-f0-9]+:	c5 f8 28 90 80 00 00 00 	vmovaps 0x80\(%rax\),%xmm2
- +[a-f0-9]+:	62 f1 7c 08 28 50 08 	vmovaps 0x80\(%rax\),%xmm2
- +[a-f0-9]+:	62 f1 7c 08 28 90 80 00 00 00 	vmovaps 0x80\(%rax\),%xmm2
+ +[a-f0-9]+:	62 f1 7c 08 28 50 08 	\{evex\} vmovaps 0x80\(%rax\),%xmm2
+ +[a-f0-9]+:	62 f1 7c 08 28 90 80 00 00 00 	\{evex\} vmovaps 0x80\(%rax\),%xmm2
  +[a-f0-9]+:	48 89 c8             	mov    %rcx,%rax
  +[a-f0-9]+:	48 8b c1             	mov    %rcx,%rax
  +[a-f0-9]+:	48 89 c8             	mov    %rcx,%rax
@@ -278,18 +278,18 @@ Disassembly of section .text:
  +[a-f0-9]+:	c5 fa 7e f8          	vmovq  %xmm0,%xmm7
  +[a-f0-9]+:	c5 fa 7e f8          	vmovq  %xmm0,%xmm7
  +[a-f0-9]+:	c5 f9 d6 c7          	vmovq  %xmm0,%xmm7
- +[a-f0-9]+:	62 f1 fe 08 7e f8    	vmovq  %xmm0,%xmm7
- +[a-f0-9]+:	62 f1 fe 08 7e f8    	vmovq  %xmm0,%xmm7
- +[a-f0-9]+:	62 f1 fd 08 d6 c7    	vmovq  %xmm0,%xmm7
+ +[a-f0-9]+:	62 f1 fe 08 7e f8    	\{evex\} vmovq %xmm0,%xmm7
+ +[a-f0-9]+:	62 f1 fe 08 7e f8    	\{evex\} vmovq %xmm0,%xmm7
+ +[a-f0-9]+:	62 f1 fd 08 d6 c7    	\{evex\} vmovq %xmm0,%xmm7
  +[a-f0-9]+:	66 0f c5 f8 00       	pextrw \$0x0,%xmm0,%edi
  +[a-f0-9]+:	66 0f c5 f8 00       	pextrw \$0x0,%xmm0,%edi
  +[a-f0-9]+:	66 0f 3a 15 c7 00    	pextrw \$0x0,%xmm0,%edi
  +[a-f0-9]+:	c5 f9 c5 f8 00       	vpextrw \$0x0,%xmm0,%edi
  +[a-f0-9]+:	c5 f9 c5 f8 00       	vpextrw \$0x0,%xmm0,%edi
  +[a-f0-9]+:	c4 e3 79 15 c7 00    	vpextrw \$0x0,%xmm0,%edi
- +[a-f0-9]+:	62 f1 7d 08 c5 f8 00 	vpextrw \$0x0,%xmm0,%edi
- +[a-f0-9]+:	62 f1 7d 08 c5 f8 00 	vpextrw \$0x0,%xmm0,%edi
- +[a-f0-9]+:	62 f3 7d 08 15 c7 00 	vpextrw \$0x0,%xmm0,%edi
+ +[a-f0-9]+:	62 f1 7d 08 c5 f8 00 	\{evex\} vpextrw \$0x0,%xmm0,%edi
+ +[a-f0-9]+:	62 f1 7d 08 c5 f8 00 	\{evex\} vpextrw \$0x0,%xmm0,%edi
+ +[a-f0-9]+:	62 f3 7d 08 15 c7 00 	\{evex\} vpextrw \$0x0,%xmm0,%edi
  +[a-f0-9]+:	66 0f 1a c3          	bndmov %bnd3,%bnd0
  +[a-f0-9]+:	66 0f 1a c3          	bndmov %bnd3,%bnd0
  +[a-f0-9]+:	66 0f 1b d8          	bndmov %bnd3,%bnd0
@@ -341,14 +341,14 @@ Disassembly of section .text:
  +[a-f0-9]+:	c4 e1 78 28 10       	vmovaps \(%rax\),%xmm2
  +[a-f0-9]+:	c5 f8 28 10          	vmovaps \(%rax\),%xmm2
  +[a-f0-9]+:	c5 f8 28 10          	vmovaps \(%rax\),%xmm2
- +[a-f0-9]+:	62 f1 7c 08 28 10    	vmovaps \(%rax\),%xmm2
+ +[a-f0-9]+:	62 f1 7c 08 28 10    	\{evex\} vmovaps \(%rax\),%xmm2
  +[a-f0-9]+:	c5 f8 28 90 00 00 00 00 	vmovaps 0x0\(%rax\),%xmm2
- +[a-f0-9]+:	62 f1 7c 08 28 50 00 	vmovaps 0x0\(%rax\),%xmm2
- +[a-f0-9]+:	62 f1 7c 08 28 90 00 00 00 00 	vmovaps 0x0\(%rax\),%xmm2
+ +[a-f0-9]+:	62 f1 7c 08 28 50 00 	\{evex\} vmovaps 0x0\(%rax\),%xmm2
+ +[a-f0-9]+:	62 f1 7c 08 28 90 00 00 00 00 	\{evex\} vmovaps 0x0\(%rax\),%xmm2
  +[a-f0-9]+:	c5 f8 28 90 80 00 00 00 	vmovaps 0x80\(%rax\),%xmm2
  +[a-f0-9]+:	c5 f8 28 90 80 00 00 00 	vmovaps 0x80\(%rax\),%xmm2
- +[a-f0-9]+:	62 f1 7c 08 28 50 08 	vmovaps 0x80\(%rax\),%xmm2
- +[a-f0-9]+:	62 f1 7c 08 28 90 80 00 00 00 	vmovaps 0x80\(%rax\),%xmm2
+ +[a-f0-9]+:	62 f1 7c 08 28 50 08 	\{evex\} vmovaps 0x80\(%rax\),%xmm2
+ +[a-f0-9]+:	62 f1 7c 08 28 90 80 00 00 00 	\{evex\} vmovaps 0x80\(%rax\),%xmm2
  +[a-f0-9]+:	48 89 c8             	mov    %rcx,%rax
  +[a-f0-9]+:	48 8b c1             	mov    %rcx,%rax
  +[a-f0-9]+:	48 89 c8             	mov    %rcx,%rax

opcodes/i386-dis-evex-len.h

@@ -2,7 +2,7 @@ static const struct dis386 evex_len_table[][3] = {
   /* EVEX_LEN_0F3816 */
   {
     { Bad_Opcode },
-    { "vpermp%XW",	{ XM, Vex, EXx }, PREFIX_DATA },
+    { "%XEvpermp%XW",	{ XM, Vex, EXx }, PREFIX_DATA },
     { "vpermp%XW",	{ XM, Vex, EXx }, PREFIX_DATA },
   },
 
@@ -30,7 +30,7 @@ static const struct dis386 evex_len_table[][3] = {
   /* EVEX_LEN_0F3836 */
   {
     { Bad_Opcode },
-    { "vperm%DQ",	{ XM, Vex, EXx }, PREFIX_DATA },
+    { "%XEvperm%DQ",	{ XM, Vex, EXx }, PREFIX_DATA },
     { "vperm%DQ",	{ XM, Vex, EXx }, PREFIX_DATA },
   },
 

opcodes/i386-dis-evex-prefix.h

@@ -1,8 +1,8 @@
   /* PREFIX_EVEX_0F5B */
   {
     { VEX_W_TABLE (EVEX_W_0F5B_P_0) },
-    { "vcvttp%XS2dq", { XM, EXx, EXxEVexS }, 0 },
-    { "vcvtp%XS2dq", { XM, EXx, EXxEVexR }, 0 },
+    { "%XEvcvttp%XS2dq", { XM, EXx, EXxEVexS }, 0 },
+    { "%XEvcvtp%XS2dq", { XM, EXx, EXxEVexR }, 0 },
   },
   /* PREFIX_EVEX_0F6F */
   {
@@ -14,9 +14,9 @@
   /* PREFIX_EVEX_0F70 */
   {
     { Bad_Opcode },
-    { "vpshufhw",	{ XM, EXx, Ib }, 0 },
+    { "%XEvpshufhw",	{ XM, EXx, Ib }, 0 },
     { VEX_W_TABLE (EVEX_W_0F70_P_2) },
-    { "vpshuflw",	{ XM, EXx, Ib }, 0 },
+    { "%XEvpshuflw",	{ XM, EXx, Ib }, 0 },
   },
   /* PREFIX_EVEX_0F78 */
   {
@@ -70,8 +70,8 @@
   {
     { Bad_Opcode },
     { VEX_W_TABLE (EVEX_W_0FE6_P_1) },
-    { "vcvttp%XD2dq%XY", { XMxmmq, EXx, EXxEVexS }, 0 },
-    { "vcvtp%XD2dq%XY", { XMxmmq, EXx, EXxEVexR }, 0 },
+    { "%XEvcvttp%XD2dq%XY", { XMxmmq, EXx, EXxEVexS }, 0 },
+    { "%XEvcvtp%XD2dq%XY", { XMxmmq, EXx, EXxEVexR }, 0 },
   },
   /* PREFIX_EVEX_0F3810 */
   {
@@ -95,7 +95,7 @@
   {
     { Bad_Opcode },
     { VEX_W_TABLE (EVEX_W_0F3813_P_1) },
-    { "vcvtph2p%XS", { XM, EXxmmq, EXxEVexS }, 0 },
+    { "%XEvcvtph2p%XS", { XM, EXxmmq, EXxEVexS }, 0 },
   },
   /* PREFIX_EVEX_0F3814 */
   {
@@ -113,31 +113,31 @@
   {
     { Bad_Opcode },
     { VEX_W_TABLE (EVEX_W_0F3820_P_1) },
-    { "vpmovsxbw",	{ XM, EXxmmq }, 0 },
+    { "%XEvpmovsxbw",	{ XM, EXxmmq }, 0 },
   },
   /* PREFIX_EVEX_0F3821 */
   {
     { Bad_Opcode },
     { VEX_W_TABLE (EVEX_W_0F3821_P_1) },
-    { "vpmovsxbd",	{ XM, EXxmmqd }, 0 },
+    { "%XEvpmovsxbd",	{ XM, EXxmmqd }, 0 },
   },
   /* PREFIX_EVEX_0F3822 */
   {
     { Bad_Opcode },
     { VEX_W_TABLE (EVEX_W_0F3822_P_1) },
-    { "vpmovsxbq",	{ XM, EXxmmdw }, 0 },
+    { "%XEvpmovsxbq",	{ XM, EXxmmdw }, 0 },
   },
   /* PREFIX_EVEX_0F3823 */
   {
     { Bad_Opcode },
     { VEX_W_TABLE (EVEX_W_0F3823_P_1) },
-    { "vpmovsxwd",	{ XM, EXxmmq }, 0 },
+    { "%XEvpmovsxwd",	{ XM, EXxmmq }, 0 },
   },
   /* PREFIX_EVEX_0F3824 */
   {
     { Bad_Opcode },
     { VEX_W_TABLE (EVEX_W_0F3824_P_1) },
-    { "vpmovsxwq",	{ XM, EXxmmqd }, 0 },
+    { "%XEvpmovsxwq",	{ XM, EXxmmqd }, 0 },
   },
   /* PREFIX_EVEX_0F3825 */
   {
@@ -179,31 +179,31 @@
   {
     { Bad_Opcode },
     { VEX_W_TABLE (EVEX_W_0F3830_P_1) },
-    { "vpmovzxbw",	{ XM, EXxmmq }, 0 },
+    { "%XEvpmovzxbw",	{ XM, EXxmmq }, 0 },
   },
   /* PREFIX_EVEX_0F3831 */
   {
     { Bad_Opcode },
     { VEX_W_TABLE (EVEX_W_0F3831_P_1) },
-    { "vpmovzxbd",	{ XM, EXxmmqd }, 0 },
+    { "%XEvpmovzxbd",	{ XM, EXxmmqd }, 0 },
   },
   /* PREFIX_EVEX_0F3832 */
   {
     { Bad_Opcode },
     { VEX_W_TABLE (EVEX_W_0F3832_P_1) },
-    { "vpmovzxbq",	{ XM, EXxmmdw }, 0 },
+    { "%XEvpmovzxbq",	{ XM, EXxmmdw }, 0 },
   },
   /* PREFIX_EVEX_0F3833 */
   {
     { Bad_Opcode },
     { VEX_W_TABLE (EVEX_W_0F3833_P_1) },
-    { "vpmovzxwd",	{ XM, EXxmmq }, 0 },
+    { "%XEvpmovzxwd",	{ XM, EXxmmq }, 0 },
   },
   /* PREFIX_EVEX_0F3834 */
   {
     { Bad_Opcode },
     { VEX_W_TABLE (EVEX_W_0F3834_P_1) },
-    { "vpmovzxwq",	{ XM, EXxmmqd }, 0 },
+    { "%XEvpmovzxwq",	{ XM, EXxmmqd }, 0 },
   },
   /* PREFIX_EVEX_0F3835 */
   {
@@ -215,19 +215,19 @@
   {
     { Bad_Opcode },
     { MOD_TABLE (MOD_EVEX_0F3838_P_1) },
-    { "vpminsb",	{ XM, Vex, EXx }, 0 },
+    { "%XEvpminsb",	{ XM, Vex, EXx }, 0 },
   },
   /* PREFIX_EVEX_0F3839 */
   {
     { Bad_Opcode },
     { "vpmov%DQ2m",	{ MaskG, EXx }, 0 },
-    { "vpmins%DQ",	{ XM, Vex, EXx }, 0 },
+    { "%XEvpmins%DQ",	{ XM, Vex, EXx }, 0 },
   },
   /* PREFIX_EVEX_0F383A */
   {
     { Bad_Opcode },
     { VEX_W_TABLE (EVEX_W_0F383A_P_1) },
-    { "vpminuw",	{ XM, Vex, EXx }, 0 },
+    { "%XEvpminuw",	{ XM, Vex, EXx }, 0 },
   },
   /* PREFIX_EVEX_0F3852 */
   {
@@ -261,28 +261,28 @@
   {
     { Bad_Opcode },
     { Bad_Opcode },
-    { "vfmsub132p%XW",	{ XM, Vex, EXx, EXxEVexR }, 0 },
+    { "%XEvfmsub132p%XW",	{ XM, Vex, EXx, EXxEVexR }, 0 },
     { "v4fmaddp%XS",	{ XM, Vex, Mxmm }, 0 },
   },
   /* PREFIX_EVEX_0F389B */
   {
     { Bad_Opcode },
     { Bad_Opcode },
-    { "vfmsub132s%XW",	{ XMScalar, VexScalar, EXdq, EXxEVexR }, 0 },
+    { "%XEvfmsub132s%XW",	{ XMScalar, VexScalar, EXdq, EXxEVexR }, 0 },
     { "v4fmadds%XS",	{ XMScalar, VexScalar, Mxmm }, 0 },
   },
   /* PREFIX_EVEX_0F38AA */
   {
     { Bad_Opcode },
     { Bad_Opcode },
-    { "vfmsub213p%XW",	{ XM, Vex, EXx, EXxEVexR }, 0 },
+    { "%XEvfmsub213p%XW",	{ XM, Vex, EXx, EXxEVexR }, 0 },
     { "v4fnmaddp%XS",	{ XM, Vex, Mxmm }, 0 },
   },
   /* PREFIX_EVEX_0F38AB */
   {
     { Bad_Opcode },
     { Bad_Opcode },
-    { "vfmsub213s%XW",	{ XMScalar, VexScalar, EXdq, EXxEVexR }, 0 },
+    { "%XEvfmsub213s%XW",	{ XMScalar, VexScalar, EXdq, EXxEVexR }, 0 },
     { "v4fnmadds%XS",	{ XMScalar, VexScalar, Mxmm }, 0 },
   },
   /* PREFIX_EVEX_0F3A08 */

opcodes/i386-dis-evex-reg.h

@@ -2,11 +2,11 @@
   {
     { Bad_Opcode },
     { Bad_Opcode },
-    { "vpsrlw",	{ Vex, EXx, Ib }, PREFIX_DATA },
+    { "%XEvpsrlw",	{ Vex, EXx, Ib }, PREFIX_DATA },
     { Bad_Opcode },
-    { "vpsraw",	{ Vex, EXx, Ib }, PREFIX_DATA },
+    { "%XEvpsraw",	{ Vex, EXx, Ib }, PREFIX_DATA },
     { Bad_Opcode },
-    { "vpsllw",	{ Vex, EXx, Ib }, PREFIX_DATA },
+    { "%XEvpsllw",	{ Vex, EXx, Ib }, PREFIX_DATA },
   },
   /* REG_EVEX_0F72 */
   {
@@ -14,7 +14,7 @@
     { "vprol%DQ",	{ Vex, EXx, Ib }, PREFIX_DATA },
     { VEX_W_TABLE (EVEX_W_0F72_R_2) },
     { Bad_Opcode },
-    { "vpsra%DQ",	{ Vex, EXx, Ib }, PREFIX_DATA },
+    { "%XEvpsra%DQ",	{ Vex, EXx, Ib }, PREFIX_DATA },
     { Bad_Opcode },
     { VEX_W_TABLE (EVEX_W_0F72_R_6) },
   },
@@ -23,11 +23,11 @@
     { Bad_Opcode },
     { Bad_Opcode },
     { VEX_W_TABLE (EVEX_W_0F73_R_2) },
-    { "vpsrldq",	{ Vex, EXx, Ib }, PREFIX_DATA },
+    { "%XEvpsrldq",	{ Vex, EXx, Ib }, PREFIX_DATA },
     { Bad_Opcode },
     { Bad_Opcode },
     { VEX_W_TABLE (EVEX_W_0F73_R_6) },
-    { "vpslldq",	{ Vex, EXx, Ib }, PREFIX_DATA },
+    { "%XEvpslldq",	{ Vex, EXx, Ib }, PREFIX_DATA },
   },
   /* REG_EVEX_0F38C6_M_0_L_2 */
   {

opcodes/i386-dis-evex-w.h

@@ -1,11 +1,11 @@
   /* EVEX_W_0F5B_P_0 */
   {
-    { "vcvtdq2ps",	{ XM, EXx, EXxEVexR }, 0 },
+    { "%XEvcvtdq2ps",	{ XM, EXx, EXxEVexR }, 0 },
     { "vcvtqq2ps%XY",	{ XMxmmq, EXx, EXxEVexR }, 0 },
   },
   /* EVEX_W_0F62 */
   {
-    { "vpunpckldq",	{ XM, Vex, EXx }, PREFIX_DATA },
+    { "%XEvpunpckldq",	{ XM, Vex, EXx }, PREFIX_DATA },
   },
   /* EVEX_W_0F66 */
   {
@@ -13,21 +13,21 @@
   },
   /* EVEX_W_0F6A */
   {
-    { "vpunpckhdq",	{ XM, Vex, EXx }, PREFIX_DATA },
+    { "%XEvpunpckhdq",	{ XM, Vex, EXx }, PREFIX_DATA },
   },
   /* EVEX_W_0F6B */
   {
-    { "vpackssdw",	{ XM, Vex, EXx }, PREFIX_DATA },
+    { "%XEvpackssdw",	{ XM, Vex, EXx }, PREFIX_DATA },
   },
   /* EVEX_W_0F6C */
   {
     { Bad_Opcode },
-    { "vpunpcklqdq",	{ XM, Vex, EXx }, PREFIX_DATA },
+    { "%XEvpunpcklqdq",	{ XM, Vex, EXx }, PREFIX_DATA },
   },
   /* EVEX_W_0F6D */
   {
     { Bad_Opcode },
-    { "vpunpckhqdq",	{ XM, Vex, EXx }, PREFIX_DATA },
+    { "%XEvpunpckhqdq",	{ XM, Vex, EXx }, PREFIX_DATA },
   },
   /* EVEX_W_0F6F_P_1 */
   {
@@ -46,25 +46,25 @@
   },
   /* EVEX_W_0F70_P_2 */
   {
-    { "vpshufd",	{ XM, EXx, Ib }, 0 },
+    { "%XEvpshufd",	{ XM, EXx, Ib }, 0 },
   },
   /* EVEX_W_0F72_R_2 */
   {
-    { "vpsrld",	{ Vex, EXx, Ib }, PREFIX_DATA },
+    { "%XEvpsrld",	{ Vex, EXx, Ib }, PREFIX_DATA },
   },
   /* EVEX_W_0F72_R_6 */
   {
-    { "vpslld",	{ Vex, EXx, Ib }, PREFIX_DATA },
+    { "%XEvpslld",	{ Vex, EXx, Ib }, PREFIX_DATA },
   },
   /* EVEX_W_0F73_R_2 */
   {
     { Bad_Opcode },
-    { "vpsrlq",	{ Vex, EXx, Ib }, PREFIX_DATA },
+    { "%XEvpsrlq",	{ Vex, EXx, Ib }, PREFIX_DATA },
   },
   /* EVEX_W_0F73_R_6 */
   {
     { Bad_Opcode },
-    { "vpsllq",	{ Vex, EXx, Ib }, PREFIX_DATA },
+    { "%XEvpsllq",	{ Vex, EXx, Ib }, PREFIX_DATA },
   },
   /* EVEX_W_0F76 */
   {
@@ -132,17 +132,17 @@
   },
   /* EVEX_W_0FD2 */
   {
-    { "vpsrld",		{ XM, Vex, EXxmm }, PREFIX_DATA },
+    { "%XEvpsrld",	{ XM, Vex, EXxmm }, PREFIX_DATA },
   },
   /* EVEX_W_0FD3 */
   {
     { Bad_Opcode },
-    { "vpsrlq",		{ XM, Vex, EXxmm }, PREFIX_DATA },
+    { "%XEvpsrlq",	{ XM, Vex, EXxmm }, PREFIX_DATA },
   },
   /* EVEX_W_0FD4 */
   {
     { Bad_Opcode },
-    { "vpaddq",		{ XM, Vex, EXx }, PREFIX_DATA },
+    { "%XEvpaddq",	{ XM, Vex, EXx }, PREFIX_DATA },
   },
   /* EVEX_W_0FD6 */
   {
@@ -151,39 +151,39 @@
   },
   /* EVEX_W_0FE6_P_1 */
   {
-    { "vcvtdq2pd",	{ XM, EXEvexHalfBcstXmmq }, 0 },
+    { "%XEvcvtdq2pd",	{ XM, EXEvexHalfBcstXmmq }, 0 },
     { "vcvtqq2pd",	{ XM, EXx, EXxEVexR }, 0 },
   },
   /* EVEX_W_0FE7 */
   {
-    { "vmovntdq",	{ EXEvexXNoBcst, XM }, PREFIX_DATA },
+    { "%XEvmovntdq",	{ EXEvexXNoBcst, XM }, PREFIX_DATA },
   },
   /* EVEX_W_0FF2 */
   {
-    { "vpslld",		{ XM, Vex, EXxmm }, PREFIX_DATA },
+    { "%XEvpslld",		{ XM, Vex, EXxmm }, PREFIX_DATA },
   },
   /* EVEX_W_0FF3 */
   {
     { Bad_Opcode },
-    { "vpsllq",		{ XM, Vex, EXxmm }, PREFIX_DATA },
+    { "%XEvpsllq",		{ XM, Vex, EXxmm }, PREFIX_DATA },
   },
   /* EVEX_W_0FF4 */
   {
     { Bad_Opcode },
-    { "vpmuludq",	{ XM, Vex, EXx }, PREFIX_DATA },
+    { "%XEvpmuludq",	{ XM, Vex, EXx }, PREFIX_DATA },
   },
   /* EVEX_W_0FFA */
   {
-    { "vpsubd",		{ XM, Vex, EXx }, PREFIX_DATA },
+    { "%XEvpsubd",		{ XM, Vex, EXx }, PREFIX_DATA },
   },
   /* EVEX_W_0FFB */
   {
     { Bad_Opcode },
-    { "vpsubq",		{ XM, Vex, EXx }, PREFIX_DATA },
+    { "%XEvpsubq",		{ XM, Vex, EXx }, PREFIX_DATA },
   },
   /* EVEX_W_0FFE */
   {
-    { "vpaddd",		{ XM, Vex, EXx }, PREFIX_DATA },
+    { "%XEvpaddd",		{ XM, Vex, EXx }, PREFIX_DATA },
   },
   /* EVEX_W_0F3810_P_1 */
   {
@@ -227,7 +227,7 @@
   /* EVEX_W_0F3819_L_n */
   {
     { "vbroadcastf32x2",	{ XM, EXq }, PREFIX_DATA },
-    { "vbroadcastsd",	{ XM, EXq }, PREFIX_DATA },
+    { "%XEvbroadcastsd",	{ XM, EXq }, PREFIX_DATA },
   },
   /* EVEX_W_0F381A_M_0_L_n */
   {
@@ -241,7 +241,7 @@
   },
   /* EVEX_W_0F381E */
   {
-    { "vpabsd",	{ XM, EXx }, PREFIX_DATA },
+    { "%XEvpabsd",	{ XM, EXx }, PREFIX_DATA },
   },
   /* EVEX_W_0F381F */
   {
@@ -274,12 +274,12 @@
   },
   /* EVEX_W_0F3825_P_2 */
   {
-    { "vpmovsxdq",	{ XM, EXxmmq }, 0 },
+    { "%XEvpmovsxdq",	{ XM, EXxmmq }, 0 },
   },
   /* EVEX_W_0F3828_P_2 */
   {
     { Bad_Opcode },
-    { "vpmuldq",	{ XM, Vex, EXx }, 0 },
+    { "%XEvpmuldq",	{ XM, Vex, EXx }, 0 },
   },
   /* EVEX_W_0F3829_P_2 */
   {
@@ -293,11 +293,11 @@
   },
   /* EVEX_W_0F382A_P_2 */
   {
-    { "vmovntdqa",	{ XM, EXEvexXNoBcst }, 0 },
+    { "%XEvmovntdqa",	{ XM, EXEvexXNoBcst }, 0 },
   },
   /* EVEX_W_0F382B */
   {
-    { "vpackusdw",	{ XM, Vex, EXx }, PREFIX_DATA },
+    { "%XEvpackusdw",	{ XM, Vex, EXx }, PREFIX_DATA },
   },
   /* EVEX_W_0F3830_P_1 */
   {
@@ -325,7 +325,7 @@
   },
   /* EVEX_W_0F3835_P_2 */
   {
-    { "vpmovzxdq",	{ XM, EXxmmq }, 0 },
+    { "%XEvpmovzxdq",	{ XM, EXxmmq }, 0 },
   },
   /* EVEX_W_0F3837 */
   {
@@ -339,7 +339,7 @@
   /* EVEX_W_0F3859 */
   {
     { "vbroadcasti32x2",	{ XM, EXq }, PREFIX_DATA },
-    { "vpbroadcastq",	{ XM, EXq }, PREFIX_DATA },
+    { "%XEvpbroadcastq",	{ XM, EXq }, PREFIX_DATA },
   },
   /* EVEX_W_0F385A_M_0_L_n */
   {

opcodes/i386-dis-evex.h

@@ -24,8 +24,8 @@ static const struct dis386 evex_table[][256] = {
     { PREFIX_TABLE (PREFIX_VEX_0F11) },
     { PREFIX_TABLE (PREFIX_VEX_0F12) },
     { MOD_TABLE (MOD_VEX_0F13) },
-    { "vunpcklpX",	{ XM, Vex, EXx }, PREFIX_OPCODE },
-    { "vunpckhpX",	{ XM, Vex, EXx }, PREFIX_OPCODE },
+    { "%XEvunpcklpX",	{ XM, Vex, EXx }, PREFIX_OPCODE },
+    { "%XEvunpckhpX",	{ XM, Vex, EXx }, PREFIX_OPCODE },
     { PREFIX_TABLE (PREFIX_VEX_0F16) },
     { MOD_TABLE (MOD_VEX_0F17) },
     /* 18 */
@@ -47,8 +47,8 @@ static const struct dis386 evex_table[][256] = {
     { Bad_Opcode },
     { Bad_Opcode },
     /* 28 */
-    { "vmovapX",	{ XM, EXx }, PREFIX_OPCODE },
-    { "vmovapX",	{ EXxS, XM }, PREFIX_OPCODE },
+    { "%XEvmovapX",	{ XM, EXx }, PREFIX_OPCODE },
+    { "%XEvmovapX",	{ EXxS, XM }, PREFIX_OPCODE },
     { PREFIX_TABLE (PREFIX_VEX_0F2A) },
     { MOD_TABLE (MOD_VEX_0F2B) },
     { PREFIX_TABLE (PREFIX_VEX_0F2C) },
@@ -96,10 +96,10 @@ static const struct dis386 evex_table[][256] = {
     { PREFIX_TABLE (PREFIX_VEX_0F51) },
     { Bad_Opcode },
     { Bad_Opcode },
-    { "vandpX",	{ XM, Vex, EXx }, PREFIX_OPCODE },
-    { "vandnpX",	{ XM, Vex, EXx }, PREFIX_OPCODE },
-    { "vorpX",	{ XM, Vex, EXx }, PREFIX_OPCODE },
-    { "vxorpX",	{ XM, Vex, EXx }, PREFIX_OPCODE },
+    { "%XEvandpX",	{ XM, Vex, EXx }, PREFIX_OPCODE },
+    { "%XEvandnpX",	{ XM, Vex, EXx }, PREFIX_OPCODE },
+    { "%XEvorpX",	{ XM, Vex, EXx }, PREFIX_OPCODE },
+    { "%XEvxorpX",	{ XM, Vex, EXx }, PREFIX_OPCODE },
     /* 58 */
     { PREFIX_TABLE (PREFIX_VEX_0F58) },
     { PREFIX_TABLE (PREFIX_VEX_0F59) },
@@ -110,17 +110,17 @@ static const struct dis386 evex_table[][256] = {
     { PREFIX_TABLE (PREFIX_VEX_0F5E) },
     { PREFIX_TABLE (PREFIX_VEX_0F5F) },
     /* 60 */
-    { "vpunpcklbw",	{ XM, Vex, EXx }, PREFIX_DATA },
-    { "vpunpcklwd",	{ XM, Vex, EXx }, PREFIX_DATA },
+    { "%XEvpunpcklbw",	{ XM, Vex, EXx }, PREFIX_DATA },
+    { "%XEvpunpcklwd",	{ XM, Vex, EXx }, PREFIX_DATA },
     { VEX_W_TABLE (EVEX_W_0F62) },
-    { "vpacksswb",	{ XM, Vex, EXx }, PREFIX_DATA },
+    { "%XEvpacksswb",	{ XM, Vex, EXx }, PREFIX_DATA },
     { "vpcmpgtb",	{ MaskG, Vex, EXx }, PREFIX_DATA },
     { "vpcmpgtw",	{ MaskG, Vex, EXx }, PREFIX_DATA },
     { VEX_W_TABLE (EVEX_W_0F66) },
-    { "vpackuswb",	{ XM, Vex, EXx }, PREFIX_DATA },
+    { "%XEvpackuswb",	{ XM, Vex, EXx }, PREFIX_DATA },
     /* 68 */
-    { "vpunpckhbw",	{ XM, Vex, EXx }, PREFIX_DATA },
-    { "vpunpckhwd",	{ XM, Vex, EXx }, PREFIX_DATA },
+    { "%XEvpunpckhbw",	{ XM, Vex, EXx }, PREFIX_DATA },
+    { "%XEvpunpckhwd",	{ XM, Vex, EXx }, PREFIX_DATA },
     { VEX_W_TABLE (EVEX_W_0F6A) },
     { VEX_W_TABLE (EVEX_W_0F6B) },
     { VEX_W_TABLE (EVEX_W_0F6C) },
@@ -224,7 +224,7 @@ static const struct dis386 evex_table[][256] = {
     { Bad_Opcode },
     { VEX_LEN_TABLE (VEX_LEN_0FC4) },
     { VEX_LEN_TABLE (VEX_LEN_0FC5) },
-    { "vshufpX",	{ XM, Vex, EXx, Ib }, PREFIX_OPCODE },
+    { "%XEvshufpX",	{ XM, Vex, EXx, Ib }, PREFIX_OPCODE },
     { Bad_Opcode },
     /* C8 */
     { Bad_Opcode },
@@ -237,67 +237,67 @@ static const struct dis386 evex_table[][256] = {
     { Bad_Opcode },
     /* D0 */
     { Bad_Opcode },
-    { "vpsrlw",		{ XM, Vex, EXxmm }, PREFIX_DATA },
+    { "%XEvpsrlw",	{ XM, Vex, EXxmm }, PREFIX_DATA },
     { VEX_W_TABLE (EVEX_W_0FD2) },
     { VEX_W_TABLE (EVEX_W_0FD3) },
     { VEX_W_TABLE (EVEX_W_0FD4) },
-    { "vpmullw",	{ XM, Vex, EXx }, PREFIX_DATA },
+    { "%XEvpmullw",	{ XM, Vex, EXx }, PREFIX_DATA },
     { VEX_W_TABLE (EVEX_W_0FD6) },
     { Bad_Opcode },
     /* D8 */
-    { "vpsubusb",	{ XM, Vex, EXx }, PREFIX_DATA },
-    { "vpsubusw",	{ XM, Vex, EXx }, PREFIX_DATA },
-    { "vpminub",	{ XM, Vex, EXx }, PREFIX_DATA },
+    { "%XEvpsubusb",	{ XM, Vex, EXx }, PREFIX_DATA },
+    { "%XEvpsubusw",	{ XM, Vex, EXx }, PREFIX_DATA },
+    { "%XEvpminub",	{ XM, Vex, EXx }, PREFIX_DATA },
     { "vpand%DQ",	{ XM, Vex, EXx }, PREFIX_DATA },
-    { "vpaddusb",	{ XM, Vex, EXx }, PREFIX_DATA },
-    { "vpaddusw",	{ XM, Vex, EXx }, PREFIX_DATA },
-    { "vpmaxub",	{ XM, Vex, EXx }, PREFIX_DATA },
+    { "%XEvpaddusb",	{ XM, Vex, EXx }, PREFIX_DATA },
+    { "%XEvpaddusw",	{ XM, Vex, EXx }, PREFIX_DATA },
+    { "%XEvpmaxub",	{ XM, Vex, EXx }, PREFIX_DATA },
     { "vpandn%DQ",	{ XM, Vex, EXx }, PREFIX_DATA },
     /* E0 */
-    { "vpavgb",		{ XM, Vex, EXx }, PREFIX_DATA },
-    { "vpsraw",		{ XM, Vex, EXxmm }, PREFIX_DATA },
-    { "vpsra%DQ",	{ XM, Vex, EXxmm }, PREFIX_DATA },
-    { "vpavgw",		{ XM, Vex, EXx }, PREFIX_DATA },
-    { "vpmulhuw",	{ XM, Vex, EXx }, PREFIX_DATA },
-    { "vpmulhw",	{ XM, Vex, EXx }, PREFIX_DATA },
+    { "%XEvpavgb",	{ XM, Vex, EXx }, PREFIX_DATA },
+    { "%XEvpsraw",	{ XM, Vex, EXxmm }, PREFIX_DATA },
+    { "%XEvpsra%DQ",	{ XM, Vex, EXxmm }, PREFIX_DATA },
+    { "%XEvpavgw",	{ XM, Vex, EXx }, PREFIX_DATA },
+    { "%XEvpmulhuw",	{ XM, Vex, EXx }, PREFIX_DATA },
+    { "%XEvpmulhw",	{ XM, Vex, EXx }, PREFIX_DATA },
     { PREFIX_TABLE (PREFIX_EVEX_0FE6) },
     { VEX_W_TABLE (EVEX_W_0FE7) },
     /* E8 */
-    { "vpsubsb",	{ XM, Vex, EXx }, PREFIX_DATA },
-    { "vpsubsw",	{ XM, Vex, EXx }, PREFIX_DATA },
-    { "vpminsw",	{ XM, Vex, EXx }, PREFIX_DATA },
+    { "%XEvpsubsb",	{ XM, Vex, EXx }, PREFIX_DATA },
+    { "%XEvpsubsw",	{ XM, Vex, EXx }, PREFIX_DATA },
+    { "%XEvpminsw",	{ XM, Vex, EXx }, PREFIX_DATA },
     { "vpor%DQ",	{ XM, Vex, EXx }, PREFIX_DATA },
-    { "vpaddsb",	{ XM, Vex, EXx }, PREFIX_DATA },
-    { "vpaddsw",	{ XM, Vex, EXx }, PREFIX_DATA },
-    { "vpmaxsw",	{ XM, Vex, EXx }, PREFIX_DATA },
+    { "%XEvpaddsb",	{ XM, Vex, EXx }, PREFIX_DATA },
+    { "%XEvpaddsw",	{ XM, Vex, EXx }, PREFIX_DATA },
+    { "%XEvpmaxsw",	{ XM, Vex, EXx }, PREFIX_DATA },
     { "vpxor%DQ",	{ XM, Vex, EXx }, PREFIX_DATA },
     /* F0 */
     { Bad_Opcode },
-    { "vpsllw",		{ XM, Vex, EXxmm }, PREFIX_DATA },
+    { "%XEvpsllw",	{ XM, Vex, EXxmm }, PREFIX_DATA },
     { VEX_W_TABLE (EVEX_W_0FF2) },
     { VEX_W_TABLE (EVEX_W_0FF3) },
     { VEX_W_TABLE (EVEX_W_0FF4) },
-    { "vpmaddwd",	{ XM, Vex, EXx }, PREFIX_DATA },
-    { "vpsadbw",	{ XM, Vex, EXx }, PREFIX_DATA },
+    { "%XEvpmaddwd",	{ XM, Vex, EXx }, PREFIX_DATA },
+    { "%XEvpsadbw",	{ XM, Vex, EXx }, PREFIX_DATA },
     { Bad_Opcode },
     /* F8 */
-    { "vpsubb",		{ XM, Vex, EXx }, PREFIX_DATA },
-    { "vpsubw",		{ XM, Vex, EXx }, PREFIX_DATA },
+    { "%XEvpsubb",	{ XM, Vex, EXx }, PREFIX_DATA },
+    { "%XEvpsubw",	{ XM, Vex, EXx }, PREFIX_DATA },
     { VEX_W_TABLE (EVEX_W_0FFA) },
     { VEX_W_TABLE (EVEX_W_0FFB) },
-    { "vpaddb",		{ XM, Vex, EXx }, PREFIX_DATA },
-    { "vpaddw",		{ XM, Vex, EXx }, PREFIX_DATA },
+    { "%XEvpaddb",	{ XM, Vex, EXx }, PREFIX_DATA },
+    { "%XEvpaddw",	{ XM, Vex, EXx }, PREFIX_DATA },
     { VEX_W_TABLE (EVEX_W_0FFE) },
     { Bad_Opcode },
   },
   /* EVEX_0F38 */
   {
     /* 00 */
-    { "vpshufb",	{ XM, Vex, EXx }, PREFIX_DATA },
+    { "%XEvpshufb",	{ XM, Vex, EXx }, PREFIX_DATA },
     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },
-    { "vpmaddubsw",	{ XM, Vex, EXx }, PREFIX_DATA },
+    { "%XEvpmaddubsw",	{ XM, Vex, EXx }, PREFIX_DATA },
     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },
@@ -305,9 +305,9 @@ static const struct dis386 evex_table[][256] = {
     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },
-    { "vpmulhrsw",	{ XM, Vex, EXx }, PREFIX_DATA },
+    { "%XEvpmulhrsw",	{ XM, Vex, EXx }, PREFIX_DATA },
     { VEX_W_TABLE (VEX_W_0F380C) },
-    { "vpermilp%XD", { XM, Vex, EXx }, PREFIX_DATA },
+    { "%XEvpermilp%XD", { XM, Vex, EXx }, PREFIX_DATA },
     { Bad_Opcode },
     { Bad_Opcode },
     /* 10 */
@@ -324,8 +324,8 @@ static const struct dis386 evex_table[][256] = {
     { EVEX_LEN_TABLE (EVEX_LEN_0F3819) },
     { MOD_TABLE (MOD_EVEX_0F381A) },
     { MOD_TABLE (MOD_EVEX_0F381B) },
-    { "vpabsb",		{ XM, EXx }, PREFIX_DATA },
-    { "vpabsw",		{ XM, EXx }, PREFIX_DATA },
+    { "%XEvpabsb",		{ XM, EXx }, PREFIX_DATA },
+    { "%XEvpabsw",		{ XM, EXx }, PREFIX_DATA },
     { VEX_W_TABLE (EVEX_W_0F381E) },
     { VEX_W_TABLE (EVEX_W_0F381F) },
     /* 20 */
@@ -359,13 +359,13 @@ static const struct dis386 evex_table[][256] = {
     { PREFIX_TABLE (PREFIX_EVEX_0F3838) },
     { PREFIX_TABLE (PREFIX_EVEX_0F3839) },
     { PREFIX_TABLE (PREFIX_EVEX_0F383A) },
-    { "vpminu%DQ",	{ XM, Vex, EXx }, PREFIX_DATA },
-    { "vpmaxsb",	{ XM, Vex, EXx }, PREFIX_DATA },
-    { "vpmaxs%DQ",	{ XM, Vex, EXx }, PREFIX_DATA },
-    { "vpmaxuw",	{ XM, Vex, EXx }, PREFIX_DATA },
-    { "vpmaxu%DQ",	{ XM, Vex, EXx }, PREFIX_DATA },
+    { "%XEvpminu%DQ",	{ XM, Vex, EXx }, PREFIX_DATA },
+    { "%XEvpmaxsb",	{ XM, Vex, EXx }, PREFIX_DATA },
+    { "%XEvpmaxs%DQ",	{ XM, Vex, EXx }, PREFIX_DATA },
+    { "%XEvpmaxuw",	{ XM, Vex, EXx }, PREFIX_DATA },
+    { "%XEvpmaxu%DQ",	{ XM, Vex, EXx }, PREFIX_DATA },
     /* 40 */
-    { "vpmull%DQ",	{ XM, Vex, EXx }, PREFIX_DATA },
+    { "%XEvpmull%DQ",	{ XM, Vex, EXx }, PREFIX_DATA },
     { Bad_Opcode },
     { "vgetexpp%XW",	{ XM, EXx, EXxEVexS }, PREFIX_DATA },
     { "vgetexps%XW",	{ XMScalar, VexScalar, EXdq, EXxEVexS }, PREFIX_DATA },
@@ -461,17 +461,17 @@ static const struct dis386 evex_table[][256] = {
     { "vgatherqp%XW",	{ XMGatherQ, MVexVSIBQWpX }, PREFIX_DATA },
     { Bad_Opcode },
     { Bad_Opcode },
-    { "vfmaddsub132p%XW", { XM, Vex, EXx, EXxEVexR }, PREFIX_DATA },
-    { "vfmsubadd132p%XW", { XM, Vex, EXx, EXxEVexR }, PREFIX_DATA },
+    { "%XEvfmaddsub132p%XW", { XM, Vex, EXx, EXxEVexR }, PREFIX_DATA },
+    { "%XEvfmsubadd132p%XW", { XM, Vex, EXx, EXxEVexR }, PREFIX_DATA },
     /* 98 */
-    { "vfmadd132p%XW", { XM, Vex, EXx, EXxEVexR }, PREFIX_DATA },
-    { "vfmadd132s%XW", { XMScalar, VexScalar, EXdq, EXxEVexR }, PREFIX_DATA },
+    { "%XEvfmadd132p%XW", { XM, Vex, EXx, EXxEVexR }, PREFIX_DATA },
+    { "%XEvfmadd132s%XW", { XMScalar, VexScalar, EXdq, EXxEVexR }, PREFIX_DATA },
     { PREFIX_TABLE (PREFIX_EVEX_0F389A) },
     { PREFIX_TABLE (PREFIX_EVEX_0F389B) },
-    { "vfnmadd132p%XW", { XM, Vex, EXx, EXxEVexR }, PREFIX_DATA },
-    { "vfnmadd132s%XW", { XMScalar, VexScalar, EXdq, EXxEVexR }, PREFIX_DATA },
-    { "vfnmsub132p%XW", { XM, Vex, EXx, EXxEVexR }, PREFIX_DATA },
-    { "vfnmsub132s%XW", { XMScalar, VexScalar, EXdq, EXxEVexR }, PREFIX_DATA },
+    { "%XEvfnmadd132p%XW", { XM, Vex, EXx, EXxEVexR }, PREFIX_DATA },
+    { "%XEvfnmadd132s%XW", { XMScalar, VexScalar, EXdq, EXxEVexR }, PREFIX_DATA },
+    { "%XEvfnmsub132p%XW", { XM, Vex, EXx, EXxEVexR }, PREFIX_DATA },
+    { "%XEvfnmsub132s%XW", { XMScalar, VexScalar, EXdq, EXxEVexR }, PREFIX_DATA },
     /* A0 */
     { "vpscatterd%DQ",	{ MVexVSIBDWpX, XM }, PREFIX_DATA },
     { "vpscatterq%DQ",	{ MVexVSIBQWpX, XMGatherQ }, PREFIX_DATA },
@@ -479,17 +479,17 @@ static const struct dis386 evex_table[][256] = {
     { "vscatterqp%XW",	{ MVexVSIBQWpX, XMGatherQ }, PREFIX_DATA },
     { Bad_Opcode },
     { Bad_Opcode },
-    { "vfmaddsub213p%XW", { XM, Vex, EXx, EXxEVexR }, PREFIX_DATA },
-    { "vfmsubadd213p%XW", { XM, Vex, EXx, EXxEVexR }, PREFIX_DATA },
+    { "%XEvfmaddsub213p%XW", { XM, Vex, EXx, EXxEVexR }, PREFIX_DATA },
+    { "%XEvfmsubadd213p%XW", { XM, Vex, EXx, EXxEVexR }, PREFIX_DATA },
     /* A8 */
-    { "vfmadd213p%XW", { XM, Vex, EXx, EXxEVexR }, PREFIX_DATA },
-    { "vfmadd213s%XW", { XMScalar, VexScalar, EXdq, EXxEVexR }, PREFIX_DATA },
+    { "%XEvfmadd213p%XW", { XM, Vex, EXx, EXxEVexR }, PREFIX_DATA },
+    { "%XEvfmadd213s%XW", { XMScalar, VexScalar, EXdq, EXxEVexR }, PREFIX_DATA },
     { PREFIX_TABLE (PREFIX_EVEX_0F38AA) },
     { PREFIX_TABLE (PREFIX_EVEX_0F38AB) },
-    { "vfnmadd213p%XW", { XM, Vex, EXx, EXxEVexR }, PREFIX_DATA },
-    { "vfnmadd213s%XW", { XMScalar, VexScalar, EXdq, EXxEVexR }, PREFIX_DATA },
-    { "vfnmsub213p%XW", { XM, Vex, EXx, EXxEVexR }, PREFIX_DATA },
-    { "vfnmsub213s%XW", { XMScalar, VexScalar, EXdq, EXxEVexR }, PREFIX_DATA },
+    { "%XEvfnmadd213p%XW", { XM, Vex, EXx, EXxEVexR }, PREFIX_DATA },
+    { "%XEvfnmadd213s%XW", { XMScalar, VexScalar, EXdq, EXxEVexR }, PREFIX_DATA },
+    { "%XEvfnmsub213p%XW", { XM, Vex, EXx, EXxEVexR }, PREFIX_DATA },
+    { "%XEvfnmsub213s%XW", { XMScalar, VexScalar, EXdq, EXxEVexR }, PREFIX_DATA },
     /* B0 */
     { Bad_Opcode },
     { Bad_Opcode },
@@ -497,17 +497,17 @@ static const struct dis386 evex_table[][256] = {
     { Bad_Opcode },
     { "vpmadd52luq",	{ XM, Vex, EXx }, PREFIX_DATA },
     { "vpmadd52huq",	{ XM, Vex, EXx }, PREFIX_DATA },
-    { "vfmaddsub231p%XW", { XM, Vex, EXx, EXxEVexR }, PREFIX_DATA },
-    { "vfmsubadd231p%XW", { XM, Vex, EXx, EXxEVexR }, PREFIX_DATA },
+    { "%XEvfmaddsub231p%XW", { XM, Vex, EXx, EXxEVexR }, PREFIX_DATA },
+    { "%XEvfmsubadd231p%XW", { XM, Vex, EXx, EXxEVexR }, PREFIX_DATA },
     /* B8 */
-    { "vfmadd231p%XW", { XM, Vex, EXx, EXxEVexR }, PREFIX_DATA },
-    { "vfmadd231s%XW", { XMScalar, VexScalar, EXdq, EXxEVexR }, PREFIX_DATA },
-    { "vfmsub231p%XW", { XM, Vex, EXx, EXxEVexR }, PREFIX_DATA },
-    { "vfmsub231s%XW", { XMScalar, VexScalar, EXdq, EXxEVexR }, PREFIX_DATA },
-    { "vfnmadd231p%XW", { XM, Vex, EXx, EXxEVexR }, PREFIX_DATA },
-    { "vfnmadd231s%XW", { XMScalar, VexScalar, EXdq, EXxEVexR }, PREFIX_DATA },
-    { "vfnmsub231p%XW", { XM, Vex, EXx, EXxEVexR }, PREFIX_DATA },
-    { "vfnmsub231s%XW", { XMScalar, VexScalar, EXdq, EXxEVexR }, PREFIX_DATA },
+    { "%XEvfmadd231p%XW", { XM, Vex, EXx, EXxEVexR }, PREFIX_DATA },
+    { "%XEvfmadd231s%XW", { XMScalar, VexScalar, EXdq, EXxEVexR }, PREFIX_DATA },
+    { "%XEvfmsub231p%XW", { XM, Vex, EXx, EXxEVexR }, PREFIX_DATA },
+    { "%XEvfmsub231s%XW", { XMScalar, VexScalar, EXdq, EXxEVexR }, PREFIX_DATA },
+    { "%XEvfnmadd231p%XW", { XM, Vex, EXx, EXxEVexR }, PREFIX_DATA },
+    { "%XEvfnmadd231s%XW", { XMScalar, VexScalar, EXdq, EXxEVexR }, PREFIX_DATA },
+    { "%XEvfnmsub231p%XW", { XM, Vex, EXx, EXxEVexR }, PREFIX_DATA },
+    { "%XEvfnmsub231s%XW", { XMScalar, VexScalar, EXdq, EXxEVexR }, PREFIX_DATA },
     /* C0 */
     { Bad_Opcode },
     { Bad_Opcode },
@@ -540,10 +540,10 @@ static const struct dis386 evex_table[][256] = {
     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },
-    { "vaesenc",	{ XM, Vex, EXx }, PREFIX_DATA },
-    { "vaesenclast",	{ XM, Vex, EXx }, PREFIX_DATA },
-    { "vaesdec",	{ XM, Vex, EXx }, PREFIX_DATA },
-    { "vaesdeclast",	{ XM, Vex, EXx }, PREFIX_DATA },
+    { "%XEvaesenc",	{ XM, Vex, EXx }, PREFIX_DATA },
+    { "%XEvaesenclast",	{ XM, Vex, EXx }, PREFIX_DATA },
+    { "%XEvaesdec",	{ XM, Vex, EXx }, PREFIX_DATA },
+    { "%XEvaesdeclast",	{ XM, Vex, EXx }, PREFIX_DATA },
     /* E0 */
     { Bad_Opcode },
     { Bad_Opcode },
@@ -589,7 +589,7 @@ static const struct dis386 evex_table[][256] = {
     { Bad_Opcode },
     { "valign%DQ",	{ XM, Vex, EXx, Ib }, PREFIX_DATA },
     { VEX_W_TABLE (VEX_W_0F3A04) },
-    { "vpermilp%XD", { XM, EXx, Ib }, PREFIX_DATA },
+    { "%XEvpermilp%XD", { XM, EXx, Ib }, PREFIX_DATA },
     { Bad_Opcode },
     { Bad_Opcode },
     /* 08 */
@@ -600,7 +600,7 @@ static const struct dis386 evex_table[][256] = {
     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },
-    { "vpalignr",	{ XM, Vex, EXx, Ib }, PREFIX_DATA },
+    { "%XEvpalignr",	{ XM, Vex, EXx, Ib }, PREFIX_DATA },
     /* 10 */
     { Bad_Opcode },
     { Bad_Opcode },
@@ -660,7 +660,7 @@ static const struct dis386 evex_table[][256] = {
     { Bad_Opcode },
     { VEX_W_TABLE (EVEX_W_0F3A42) },
     { EVEX_LEN_TABLE (EVEX_LEN_0F3A43) },
-    { "vpclmulqdq",	{ XM, Vex, EXx, PCLMUL }, PREFIX_DATA },
+    { "%XEvpclmulqdq",	{ XM, Vex, EXx, PCLMUL }, PREFIX_DATA },
     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },

opcodes/i386-dis.c

@@ -1759,6 +1759,8 @@ struct dis386 {
    "XH" => print 'h' if EVEX.W=0, EVEX.W=1 is not a valid encoding (for FP16)
    "XS" => print 's' if !EVEX or EVEX.W=0, EVEX.W=1 is not a valid encoding
    "XV" => print "{vex} " pseudo prefix
+   "XE" => print "{evex} " pseudo prefix if no EVEX-specific functionality is
+	   is used by an EVEX-encoded (AVX512VL) instruction.
    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand, cond
 	   being false, or no operand at all in 64bit mode, or if suffix_always
 	   is true.
@@ -3564,71 +3566,71 @@ static const struct dis386 prefix_table[][4] = {
 
   /* PREFIX_VEX_0F10 */
   {
-    { "vmovupX",	{ XM, EXEvexXNoBcst }, PREFIX_OPCODE },
-    { "vmovs%XS",	{ XMScalar, VexScalarR, EXd }, 0 },
-    { "vmovupX",	{ XM, EXEvexXNoBcst }, PREFIX_OPCODE },
-    { "vmovs%XD",	{ XMScalar, VexScalarR, EXq }, 0 },
+    { "%XEvmovupX",	{ XM, EXEvexXNoBcst }, 0 },
+    { "%XEvmovs%XS",	{ XMScalar, VexScalarR, EXd }, 0 },
+    { "%XEvmovupX",	{ XM, EXEvexXNoBcst }, 0 },
+    { "%XEvmovs%XD",	{ XMScalar, VexScalarR, EXq }, 0 },
   },
 
   /* PREFIX_VEX_0F11 */
   {
-    { "vmovupX",	{ EXxS, XM }, PREFIX_OPCODE },
-    { "vmovs%XS",	{ EXdS, VexScalarR, XMScalar }, 0 },
-    { "vmovupX",	{ EXxS, XM }, PREFIX_OPCODE },
-    { "vmovs%XD",	{ EXqS, VexScalarR, XMScalar }, 0 },
+    { "%XEvmovupX",	{ EXxS, XM }, 0 },
+    { "%XEvmovs%XS",	{ EXdS, VexScalarR, XMScalar }, 0 },
+    { "%XEvmovupX",	{ EXxS, XM }, 0 },
+    { "%XEvmovs%XD",	{ EXqS, VexScalarR, XMScalar }, 0 },
   },
 
   /* PREFIX_VEX_0F12 */
   {
     { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
-    { "vmov%XSldup",	{ XM, EXEvexXNoBcst }, 0 },
+    { "%XEvmov%XSldup",	{ XM, EXEvexXNoBcst }, 0 },
     { MOD_TABLE (MOD_VEX_0F12_PREFIX_2) },
-    { "vmov%XDdup",	{ XM, EXymmq }, 0 },
+    { "%XEvmov%XDdup",	{ XM, EXymmq }, 0 },
   },
 
   /* PREFIX_VEX_0F16 */
   {
     { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
-    { "vmov%XShdup",	{ XM, EXEvexXNoBcst }, 0 },
+    { "%XEvmov%XShdup",	{ XM, EXEvexXNoBcst }, 0 },
     { MOD_TABLE (MOD_VEX_0F16_PREFIX_2) },
   },
 
   /* PREFIX_VEX_0F2A */
   {
     { Bad_Opcode },
-    { "vcvtsi2ss{%LQ|}",	{ XMScalar, VexScalar, EXxEVexR, Edq }, 0 },
+    { "%XEvcvtsi2ss{%LQ|}",	{ XMScalar, VexScalar, EXxEVexR, Edq }, 0 },
     { Bad_Opcode },
-    { "vcvtsi2sd{%LQ|}",	{ XMScalar, VexScalar, EXxEVexR64, Edq }, 0 },
+    { "%XEvcvtsi2sd{%LQ|}",	{ XMScalar, VexScalar, EXxEVexR64, Edq }, 0 },
   },
 
   /* PREFIX_VEX_0F2C */
   {
     { Bad_Opcode },
-    { "vcvttss2si",	{ Gdq, EXd, EXxEVexS }, 0 },
+    { "%XEvcvttss2si",	{ Gdq, EXd, EXxEVexS }, 0 },
     { Bad_Opcode },
-    { "vcvttsd2si",	{ Gdq, EXq, EXxEVexS }, 0 },
+    { "%XEvcvttsd2si",	{ Gdq, EXq, EXxEVexS }, 0 },
   },
 
   /* PREFIX_VEX_0F2D */
   {
     { Bad_Opcode },
-    { "vcvtss2si",	{ Gdq, EXd, EXxEVexR }, 0 },
+    { "%XEvcvtss2si",	{ Gdq, EXd, EXxEVexR }, 0 },
     { Bad_Opcode },
-    { "vcvtsd2si",	{ Gdq, EXq, EXxEVexR }, 0 },
+    { "%XEvcvtsd2si",	{ Gdq, EXq, EXxEVexR }, 0 },
   },
 
   /* PREFIX_VEX_0F2E */
   {
-    { "vucomisX",	{ XMScalar, EXd, EXxEVexS }, PREFIX_OPCODE },
+    { "%XEvucomisX",	{ XMScalar, EXd, EXxEVexS }, 0 },
     { Bad_Opcode },
-    { "vucomisX",	{ XMScalar, EXq, EXxEVexS }, PREFIX_OPCODE },
+    { "%XEvucomisX",	{ XMScalar, EXq, EXxEVexS }, 0 },
   },
 
   /* PREFIX_VEX_0F2F */
   {
-    { "vcomisX",	{ XMScalar, EXd, EXxEVexS }, PREFIX_OPCODE },
+    { "%XEvcomisX",	{ XMScalar, EXd, EXxEVexS }, 0 },
     { Bad_Opcode },
-    { "vcomisX",	{ XMScalar, EXq, EXxEVexS }, PREFIX_OPCODE },
+    { "%XEvcomisX",	{ XMScalar, EXq, EXxEVexS }, 0 },
   },
 
   /* PREFIX_VEX_0F41_L_1_M_1_W_0 */
@@ -3743,10 +3745,10 @@ static const struct dis386 prefix_table[][4] = {
 
   /* PREFIX_VEX_0F51 */
   {
-    { "vsqrtpX",	{ XM, EXx, EXxEVexR }, PREFIX_OPCODE },
-    { "vsqrts%XS",	{ XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
-    { "vsqrtpX",	{ XM, EXx, EXxEVexR }, PREFIX_OPCODE },
-    { "vsqrts%XD",	{ XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
+    { "%XEvsqrtpX",	{ XM, EXx, EXxEVexR }, 0 },
+    { "%XEvsqrts%XS",	{ XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
+    { "%XEvsqrtpX",	{ XM, EXx, EXxEVexR }, 0 },
+    { "%XEvsqrts%XD",	{ XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
   },
 
   /* PREFIX_VEX_0F52 */
@@ -3763,26 +3765,26 @@ static const struct dis386 prefix_table[][4] = {
 
   /* PREFIX_VEX_0F58 */
   {
-    { "vaddpX",		{ XM, Vex, EXx, EXxEVexR }, PREFIX_OPCODE },
-    { "vadds%XS",	{ XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
-    { "vaddpX",		{ XM, Vex, EXx, EXxEVexR }, PREFIX_OPCODE },
-    { "vadds%XD",	{ XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
+    { "%XEvaddpX",	{ XM, Vex, EXx, EXxEVexR }, 0 },
+    { "%XEvadds%XS",	{ XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
+    { "%XEvaddpX",	{ XM, Vex, EXx, EXxEVexR }, 0 },
+    { "%XEvadds%XD",	{ XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
   },
 
   /* PREFIX_VEX_0F59 */
   {
-    { "vmulpX",		{ XM, Vex, EXx, EXxEVexR }, PREFIX_OPCODE },
-    { "vmuls%XS",	{ XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
-    { "vmulpX",		{ XM, Vex, EXx, EXxEVexR }, PREFIX_OPCODE },
-    { "vmuls%XD",	{ XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
+    { "%XEvmulpX",	{ XM, Vex, EXx, EXxEVexR }, 0 },
+    { "%XEvmuls%XS",	{ XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
+    { "%XEvmulpX",	{ XM, Vex, EXx, EXxEVexR }, 0 },
+    { "%XEvmuls%XD",	{ XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
   },
 
   /* PREFIX_VEX_0F5A */
   {
-    { "vcvtp%XS2pd", { XM, EXEvexHalfBcstXmmq, EXxEVexS }, 0 },
-    { "vcvts%XS2sd", { XMScalar, VexScalar, EXd, EXxEVexS }, 0 },
-    { "vcvtp%XD2ps%XY", { XMxmmq, EXx, EXxEVexR }, 0 },
-    { "vcvts%XD2ss", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
+    { "%XEvcvtp%XS2pd", { XM, EXEvexHalfBcstXmmq, EXxEVexS }, 0 },
+    { "%XEvcvts%XS2sd", { XMScalar, VexScalar, EXd, EXxEVexS }, 0 },
+    { "%XEvcvtp%XD2ps%XY", { XMxmmq, EXx, EXxEVexR }, 0 },
+    { "%XEvcvts%XD2ss", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
   },
 
   /* PREFIX_VEX_0F5B */
@@ -3794,34 +3796,34 @@ static const struct dis386 prefix_table[][4] = {
 
   /* PREFIX_VEX_0F5C */
   {
-    { "vsubpX",		{ XM, Vex, EXx, EXxEVexR }, PREFIX_OPCODE },
-    { "vsubs%XS",	{ XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
-    { "vsubpX",		{ XM, Vex, EXx, EXxEVexR }, PREFIX_OPCODE },
-    { "vsubs%XD",	{ XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
+    { "%XEvsubpX",	{ XM, Vex, EXx, EXxEVexR }, 0 },
+    { "%XEvsubs%XS",	{ XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
+    { "%XEvsubpX",	{ XM, Vex, EXx, EXxEVexR }, 0 },
+    { "%XEvsubs%XD",	{ XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
   },
 
   /* PREFIX_VEX_0F5D */
   {
-    { "vminpX",		{ XM, Vex, EXx, EXxEVexS }, PREFIX_OPCODE },
-    { "vmins%XS",	{ XMScalar, VexScalar, EXd, EXxEVexS }, 0 },
-    { "vminpX",		{ XM, Vex, EXx, EXxEVexS }, PREFIX_OPCODE },
-    { "vmins%XD",	{ XMScalar, VexScalar, EXq, EXxEVexS }, 0 },
+    { "%XEvminpX",	{ XM, Vex, EXx, EXxEVexS }, 0 },
+    { "%XEvmins%XS",	{ XMScalar, VexScalar, EXd, EXxEVexS }, 0 },
+    { "%XEvminpX",	{ XM, Vex, EXx, EXxEVexS }, 0 },
+    { "%XEvmins%XD",	{ XMScalar, VexScalar, EXq, EXxEVexS }, 0 },
   },
 
   /* PREFIX_VEX_0F5E */
   {
-    { "vdivpX",		{ XM, Vex, EXx, EXxEVexR }, PREFIX_OPCODE },
-    { "vdivs%XS",	{ XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
-    { "vdivpX",		{ XM, Vex, EXx, EXxEVexR }, PREFIX_OPCODE },
-    { "vdivs%XD",	{ XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
+    { "%XEvdivpX",	{ XM, Vex, EXx, EXxEVexR }, 0 },
+    { "%XEvdivs%XS",	{ XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
+    { "%XEvdivpX",	{ XM, Vex, EXx, EXxEVexR }, 0 },
+    { "%XEvdivs%XD",	{ XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
   },
 
   /* PREFIX_VEX_0F5F */
   {
-    { "vmaxpX",		{ XM, Vex, EXx, EXxEVexS }, PREFIX_OPCODE },
-    { "vmaxs%XS",	{ XMScalar, VexScalar, EXd, EXxEVexS }, 0 },
-    { "vmaxpX",		{ XM, Vex, EXx, EXxEVexS }, PREFIX_OPCODE },
-    { "vmaxs%XD",	{ XMScalar, VexScalar, EXq, EXxEVexS }, 0 },
+    { "%XEvmaxpX",	{ XM, Vex, EXx, EXxEVexS }, 0 },
+    { "%XEvmaxs%XS",	{ XMScalar, VexScalar, EXd, EXxEVexS }, 0 },
+    { "%XEvmaxpX",	{ XM, Vex, EXx, EXxEVexS }, 0 },
+    { "%XEvmaxs%XD",	{ XMScalar, VexScalar, EXq, EXxEVexS }, 0 },
   },
 
   /* PREFIX_VEX_0F6F */
@@ -6681,32 +6683,32 @@ static const struct dis386 vex_table[][256] = {
 static const struct dis386 vex_len_table[][2] = {
   /* VEX_LEN_0F12_P_0_M_0 / VEX_LEN_0F12_P_2_M_0 */
   {
-    { "vmovlpX",	{ XM, Vex, EXq }, PREFIX_OPCODE },
+    { "%XEvmovlpX",	{ XM, Vex, EXq }, 0 },
   },
 
   /* VEX_LEN_0F12_P_0_M_1 */
   {
-    { "vmovhlp%XS",	{ XM, Vex, EXq }, 0 },
+    { "%XEvmovhlp%XS",	{ XM, Vex, EXq }, 0 },
   },
 
   /* VEX_LEN_0F13_M_0 */
   {
-    { "vmovlpX",	{ EXq, XM }, PREFIX_OPCODE },
+    { "%XEvmovlpX",	{ EXq, XM }, PREFIX_OPCODE },
   },
 
   /* VEX_LEN_0F16_P_0_M_0 / VEX_LEN_0F16_P_2_M_0 */
   {
-    { "vmovhpX",	{ XM, Vex, EXq }, PREFIX_OPCODE },
+    { "%XEvmovhpX",	{ XM, Vex, EXq }, 0 },
   },
 
   /* VEX_LEN_0F16_P_0_M_1 */
   {
-    { "vmovlhp%XS",	{ XM, Vex, EXq }, 0 },
+    { "%XEvmovlhp%XS",	{ XM, Vex, EXq }, 0 },
   },
 
   /* VEX_LEN_0F17_M_0 */
   {
-    { "vmovhpX",	{ EXq, XM }, PREFIX_OPCODE },
+    { "%XEvmovhpX",	{ EXq, XM }, PREFIX_OPCODE },
   },
 
   /* VEX_LEN_0F41 */
@@ -6758,7 +6760,7 @@ static const struct dis386 vex_len_table[][2] = {
 
   /* VEX_LEN_0F6E */
   {
-    { "vmovK",		{ XMScalar, Edq }, PREFIX_DATA },
+    { "%XEvmovK",	{ XMScalar, Edq }, PREFIX_DATA },
   },
 
   /* VEX_LEN_0F77 */
@@ -6769,12 +6771,12 @@ static const struct dis386 vex_len_table[][2] = {
 
   /* VEX_LEN_0F7E_P_1 */
   {
-    { "vmovq",		{ XMScalar, EXq }, 0 },
+    { "%XEvmovq",	{ XMScalar, EXq }, 0 },
   },
 
   /* VEX_LEN_0F7E_P_2 */
   {
-    { "vmovK",		{ Edq, XMScalar }, 0 },
+    { "%XEvmovK",	{ Edq, XMScalar }, 0 },
   },
 
   /* VEX_LEN_0F90 */
@@ -6819,17 +6821,17 @@ static const struct dis386 vex_len_table[][2] = {
 
   /* VEX_LEN_0FC4 */
   {
-    { "vpinsrw",	{ XM, Vex, Edw, Ib }, PREFIX_DATA },
+    { "%XEvpinsrw",	{ XM, Vex, Edw, Ib }, PREFIX_DATA },
   },
 
   /* VEX_LEN_0FC5 */
   {
-    { "vpextrw",	{ Gd, XS, Ib }, PREFIX_DATA },
+    { "%XEvpextrw",	{ Gd, XS, Ib }, PREFIX_DATA },
   },
 
   /* VEX_LEN_0FD6 */
   {
-    { "vmovq",		{ EXqS, XMScalar }, PREFIX_DATA },
+    { "%XEvmovq",	{ EXqS, XMScalar }, PREFIX_DATA },
   },
 
   /* VEX_LEN_0FF7 */
@@ -6986,22 +6988,22 @@ static const struct dis386 vex_len_table[][2] = {
 
   /* VEX_LEN_0F3A14 */
   {
-    { "vpextrb",	{ Edb, XM, Ib }, PREFIX_DATA },
+    { "%XEvpextrb",	{ Edb, XM, Ib }, PREFIX_DATA },
   },
 
   /* VEX_LEN_0F3A15 */
   {
-    { "vpextrw",	{ Edw, XM, Ib }, PREFIX_DATA },
+    { "%XEvpextrw",	{ Edw, XM, Ib }, PREFIX_DATA },
   },
 
   /* VEX_LEN_0F3A16  */
   {
-    { "vpextrK",	{ Edq, XM, Ib }, PREFIX_DATA },
+    { "%XEvpextrK",	{ Edq, XM, Ib }, PREFIX_DATA },
   },
 
   /* VEX_LEN_0F3A17 */
   {
-    { "vextractps",	{ Ed, XM, Ib }, PREFIX_DATA },
+    { "%XEvextractps",	{ Ed, XM, Ib }, PREFIX_DATA },
   },
 
   /* VEX_LEN_0F3A18 */
@@ -7018,17 +7020,17 @@ static const struct dis386 vex_len_table[][2] = {
 
   /* VEX_LEN_0F3A20 */
   {
-    { "vpinsrb",	{ XM, Vex, Edb, Ib }, PREFIX_DATA },
+    { "%XEvpinsrb",	{ XM, Vex, Edb, Ib }, PREFIX_DATA },
   },
 
   /* VEX_LEN_0F3A21 */
   {
-    { "vinsertps",	{ XM, Vex, EXd, Ib }, PREFIX_DATA },
+    { "%XEvinsertps",	{ XM, Vex, EXd, Ib }, PREFIX_DATA },
   },
 
   /* VEX_LEN_0F3A22 */
   {
-    { "vpinsrK",	{ XM, Vex, Edq, Ib }, PREFIX_DATA },
+    { "%XEvpinsrK",	{ XM, Vex, Edq, Ib }, PREFIX_DATA },
   },
 
   /* VEX_LEN_0F3A30 */
@@ -7470,7 +7472,7 @@ static const struct dis386 vex_w_table[][2] = {
   },
   {
     /* VEX_W_0F380C  */
-    { "vpermilps",	{ XM, Vex, EXx }, PREFIX_DATA },
+    { "%XEvpermilps",	{ XM, Vex, EXx }, PREFIX_DATA },
   },
   {
     /* VEX_W_0F380D  */
@@ -7494,7 +7496,7 @@ static const struct dis386 vex_w_table[][2] = {
   },
   {
     /* VEX_W_0F3818 */
-    { "vbroadcastss",	{ XM, EXd }, PREFIX_DATA },
+    { "%XEvbroadcastss",	{ XM, EXd }, PREFIX_DATA },
   },
   {
     /* VEX_W_0F3819_L_1 */
@@ -7570,7 +7572,7 @@ static const struct dis386 vex_w_table[][2] = {
   },
   {
     /* VEX_W_0F3858 */
-    { "vpbroadcastd", { XM, EXd }, PREFIX_DATA },
+    { "%XEvpbroadcastd", { XM, EXd }, PREFIX_DATA },
   },
   {
     /* VEX_W_0F3859 */
@@ -7606,25 +7608,25 @@ static const struct dis386 vex_w_table[][2] = {
   },
   {
     /* VEX_W_0F3878 */
-    { "vpbroadcastb",	{ XM, EXb }, PREFIX_DATA },
+    { "%XEvpbroadcastb",	{ XM, EXb }, PREFIX_DATA },
   },
   {
     /* VEX_W_0F3879 */
-    { "vpbroadcastw",	{ XM, EXw }, PREFIX_DATA },
+    { "%XEvpbroadcastw",	{ XM, EXw }, PREFIX_DATA },
   },
   {
     /* VEX_W_0F38CF */
-    { "vgf2p8mulb", { XM, Vex, EXx }, PREFIX_DATA },
+    { "%XEvgf2p8mulb", { XM, Vex, EXx }, PREFIX_DATA },
   },
   {
     /* VEX_W_0F3A00_L_1 */
     { Bad_Opcode },
-    { "vpermq",		{ XM, EXx, Ib }, PREFIX_DATA },
+    { "%XEvpermq",		{ XM, EXx, Ib }, PREFIX_DATA },
   },
   {
     /* VEX_W_0F3A01_L_1 */
     { Bad_Opcode },
-    { "vpermpd",	{ XM, EXx, Ib }, PREFIX_DATA },
+    { "%XEvpermpd",	{ XM, EXx, Ib }, PREFIX_DATA },
   },
   {
     /* VEX_W_0F3A02 */
@@ -7632,7 +7634,7 @@ static const struct dis386 vex_w_table[][2] = {
   },
   {
     /* VEX_W_0F3A04 */
-    { "vpermilps",	{ XM, EXx, Ib }, PREFIX_DATA },
+    { "%XEvpermilps",	{ XM, EXx, Ib }, PREFIX_DATA },
   },
   {
     /* VEX_W_0F3A05 */
@@ -7652,7 +7654,7 @@ static const struct dis386 vex_w_table[][2] = {
   },
   {
     /* VEX_W_0F3A1D */
-    { "vcvtps2ph", { EXxmmq, XM, EXxEVexS, Ib }, PREFIX_DATA },
+    { "%XEvcvtps2ph", { EXxmmq, XM, EXxEVexS, Ib }, PREFIX_DATA },
   },
   {
     /* VEX_W_0F3A38_L_1 */
@@ -7681,12 +7683,12 @@ static const struct dis386 vex_w_table[][2] = {
   {
     /* VEX_W_0F3ACE */
     { Bad_Opcode },
-    { "vgf2p8affineqb", { XM, Vex, EXx, Ib }, PREFIX_DATA },
+    { "%XEvgf2p8affineqb", { XM, Vex, EXx, Ib }, PREFIX_DATA },
   },
   {
     /* VEX_W_0F3ACF */
     { Bad_Opcode },
-    { "vgf2p8affineinvqb",  { XM, Vex, EXx, Ib }, PREFIX_DATA },
+    { "%XEvgf2p8affineinvqb",  { XM, Vex, EXx, Ib }, PREFIX_DATA },
   },
   /* VEX_W_0FXOP_08_85_L_0 */
   {
@@ -8218,7 +8220,7 @@ static const struct dis386 mod_table[][2] = {
   },
   {
     /* MOD_VEX_0F2B */
-    { "vmovntpX",	{ Mx, XM }, PREFIX_OPCODE },
+    { "%XEvmovntpX",	{ Mx, XM }, PREFIX_OPCODE },
   },
   {
     /* MOD_VEX_0F41_L_1 */
@@ -10469,7 +10471,41 @@ putop (instr_info *ins, const char *in_template, int sizeflag)
 	  else
 	    *ins->obufp++ = 'w';
 	  break;
-	case 'E':		/* For jcxz/jecxz */
+	case 'E':
+	  if (l == 1)
+	    {
+	      switch (last[0])
+		{
+		case 'X':
+		  if (!ins->vex.evex || ins->vex.b || ins->vex.ll >= 2
+		      || !ins->vex.r
+		      || (ins->modrm.mod == 3 && (ins->rex & REX_X))
+		      || !ins->vex.v || ins->vex.mask_register_specifier)
+		    break;
+		  /* AVX512 extends a number of V*D insns to also have V*Q variants,
+		     merely distinguished by EVEX.W.  Look for a use of the
+		     respective macro.  */
+		  if (ins->vex.w)
+		    {
+		      const char *pct = strchr (p + 1, '%');
+
+		      if (pct != NULL && pct[1] == 'D' && pct[2] == 'Q')
+			break;
+		    }
+		  *ins->obufp++ = '{';
+		  *ins->obufp++ = 'e';
+		  *ins->obufp++ = 'v';
+		  *ins->obufp++ = 'e';
+		  *ins->obufp++ = 'x';
+		  *ins->obufp++ = '}';
+		  *ins->obufp++ = ' ';
+		  break;
+		default:
+		  abort ();
+		}
+		break;
+	    }
+	  /* For jcxz/jecxz */
 	  if (ins->address_mode == mode_64bit)
 	    {
 	      if (sizeflag & AFLAG)