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[aarch64] GAS doesn't validate the architecture version for any tlbi registers. Fixed with this patch. 

* gas/config/tc-aarch64.c (parse_sys_reg): Call to
	aarch64_sys_ins_reg_supported_p instead of aarch64_sys_reg_supported_p.
	(parse_sys_ins_reg): Add aarch64_sys_reg_deprecated_p check.
	* include/opcode/aarch64.h (aarch64_sys_reg_deprecated_p): Functions
	paramaters changed.
	(aarch64_sys_reg_supported_p): Function removed.
	(aarch64_sys_ins_reg_supported_p): Functions paramaters changed.
	* opcodes/aarch64-opc.c (aarch64_print_operand):
	(aarch64_sys_reg_deprecated_p): Functions paramaters changed.
	(aarch64_sys_reg_supported_p): Function removed.
	(aarch64_sys_ins_reg_supported_p): Functions paramaters changed.
	(aarch64_sys_ins_reg_supported_p): Merged aarch64_sys_reg_supported_p
	into this function.
	* gas/testsuite/gas/aarch64/illegal-sysreg-5.d: New test.
	* gas/testsuite/gas/aarch64/illegal-sysreg-5.l: New test.
	* gas/testsuite/gas/aarch64/sysreg-5.s: New test.
gdb-10-branch
Przemyslaw Wirkus 6 years ago
committed by Nick Clifton
parent
f8e3fe0d27
commit
f7cb161ea6
9 changed files with 153 additions and 111 deletions
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  1. 20
      gas/ChangeLog
  2. 16
      gas/config/tc-aarch64.c
  3. 3
      gas/testsuite/gas/aarch64/illegal-sysreg-5.d
  4. 2
      gas/testsuite/gas/aarch64/illegal-sysreg-5.l
  5. 1
      gas/testsuite/gas/aarch64/sysreg-5.s
  6. 7
      include/ChangeLog
  7. 8
      include/opcode/aarch64.h
  8. 9
      opcodes/ChangeLog
  9. 198
      opcodes/aarch64-opc.c

20
gas/ChangeLog
View File

@ -1,3 +1,23 @@
* include/opcode/aarch64.h (aarch64_sys_reg_deprecated_p): Functions
paramaters changed.
(aarch64_sys_reg_supported_p): Function removed.
(aarch64_sys_ins_reg_supported_p): Functions paramaters changed.
* opcodes/aarch64-opc.c (aarch64_print_operand):
(aarch64_sys_reg_deprecated_p): Functions paramaters changed.
(aarch64_sys_reg_supported_p): Function removed.
(aarch64_sys_ins_reg_supported_p): Functions paramaters changed.
(aarch64_sys_ins_reg_supported_p): Merged aarch64_sys_reg_supported_p
into this function.
2020-08-10 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
* config/tc-aarch64.c (parse_sys_reg): Call to
aarch64_sys_ins_reg_supported_p instead of
aarch64_sys_reg_supported_p.
(parse_sys_ins_reg): Add aarch64_sys_reg_deprecated_p check.
* testsuite/gas/aarch64/illegal-sysreg-5.d: New test.
* testsuite/gas/aarch64/illegal-sysreg-5.l: New test.
* testsuite/gas/aarch64/sysreg-5.s: New test.
2020-08-10 Alan Modra <amodra@gmail.com>
* testsuite/gas/ppc/power8.d,

16
gas/config/tc-aarch64.c
View File

@ -4137,10 +4137,12 @@ parse_sys_reg (char **str, struct hash_control *sys_regs,
if (pstatefield_p && !aarch64_pstatefield_supported_p (cpu_variant, o))
as_bad (_("selected processor does not support PSTATE field "
"name '%s'"), buf);
if (!pstatefield_p && !aarch64_sys_reg_supported_p (cpu_variant, o))
if (!pstatefield_p
&& !aarch64_sys_ins_reg_supported_p (cpu_variant, o->value,
o->flags, o->features))
as_bad (_("selected processor does not support system register "
"name '%s'"), buf);
if (aarch64_sys_reg_deprecated_p (o))
if (aarch64_sys_reg_deprecated_p (o->flags))
as_warn (_("system register name '%s' is deprecated and may be "
"removed in a future release"), buf);
value = o->value;
@ -4172,9 +4174,12 @@ parse_sys_ins_reg (char **str, struct hash_control *sys_ins_regs)
if (!o)
return NULL;
if (!aarch64_sys_ins_reg_supported_p (cpu_variant, o))
if (!aarch64_sys_ins_reg_supported_p (cpu_variant, o->value, o->flags, 0))
as_bad (_("selected processor does not support system register "
"name '%s'"), buf);
if (aarch64_sys_reg_deprecated_p (o->flags))
as_warn (_("system register name '%s' is deprecated and may be "
"removed in a future release"), buf);
*str = q;
return o;
@ -4328,7 +4333,10 @@ reencode_movzn_to_movn (uint32_t opcode)
static fixS *
fix_new_aarch64 (fragS * frag,
int where,
short int size, expressionS * exp, int pc_rel, int reloc)
short int size,
expressionS * exp,
int pc_rel,
int reloc)
{
fixS *new_fix;

3
gas/testsuite/gas/aarch64/illegal-sysreg-5.d
View File

@ -0,0 +1,3 @@
#as: -march=armv8.3-a
#source: sysreg-5.s
#error_output: illegal-sysreg-5.l

2
gas/testsuite/gas/aarch64/illegal-sysreg-5.l
View File

@ -0,0 +1,2 @@
[^:]*: Assembler messages:
[^:]*:[0-9]+: Error: selected processor does not support system register name 'rvae1is'

1
gas/testsuite/gas/aarch64/sysreg-5.s
View File

@ -0,0 +1 @@
tlbi rvae1is, x0

7
include/ChangeLog
View File

@ -1,3 +1,10 @@
2020-08-10 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
* opcode/aarch64.h (aarch64_sys_reg_deprecated_p): Functions
paramaters changed.
(aarch64_sys_reg_supported_p): Function removed.
(aarch64_sys_ins_reg_supported_p): Functions paramaters changed.
2020-07-28 Caroline Tice <cmtice@google.com>
* dwarf2.h (enum dwarf_sect_v5): A new enum section for the

8
include/opcode/aarch64.h
View File

@ -956,9 +956,7 @@ typedef struct
extern const aarch64_sys_reg aarch64_sys_regs [];
extern const aarch64_sys_reg aarch64_pstatefields [];
extern bfd_boolean aarch64_sys_reg_deprecated_p (const aarch64_sys_reg *);
extern bfd_boolean aarch64_sys_reg_supported_p (const aarch64_feature_set,
const aarch64_sys_reg *);
extern bfd_boolean aarch64_sys_reg_deprecated_p (const uint32_t);
extern bfd_boolean aarch64_pstatefield_supported_p (const aarch64_feature_set,
const aarch64_sys_reg *);
@ -971,8 +969,8 @@ typedef struct
extern bfd_boolean aarch64_sys_ins_reg_has_xt (const aarch64_sys_ins_reg *);
extern bfd_boolean
aarch64_sys_ins_reg_supported_p (const aarch64_feature_set,
const aarch64_sys_ins_reg *);
aarch64_sys_ins_reg_supported_p (const aarch64_feature_set, aarch64_insn,
uint32_t, aarch64_feature_set);
extern const aarch64_sys_ins_reg aarch64_sys_regs_ic [];
extern const aarch64_sys_ins_reg aarch64_sys_regs_dc [];

9
opcodes/ChangeLog
View File

@ -1,3 +1,12 @@
2020-08-10 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
* aarch64-opc.c (aarch64_print_operand):
(aarch64_sys_reg_deprecated_p): Functions paramaters changed.
(aarch64_sys_reg_supported_p): Function removed.
(aarch64_sys_ins_reg_supported_p): Functions paramaters changed.
(aarch64_sys_ins_reg_supported_p): Merged aarch64_sys_reg_supported_p
into this function.
2020-08-10 Alan Modra <amodra@gmail.com>
* ppc-opc.c (powerpc_opcodes): Add many mtspr and mfspr extended

198
opcodes/aarch64-opc.c
View File

@ -3695,7 +3695,7 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
/* Try and find an exact match, But if that fails, return the first
partial match that was found. */
if (aarch64_sys_regs[i].value == opnd->sysreg.value
&& ! aarch64_sys_reg_deprecated_p (&aarch64_sys_regs[i])
&& ! aarch64_sys_reg_deprecated_p (aarch64_sys_regs[i].flags)
&& (name == NULL || exact_match))
{
name = aarch64_sys_regs[i].name;
@ -4245,72 +4245,9 @@ const aarch64_sys_reg aarch64_sys_regs [] =
};
bfd_boolean
aarch64_sys_reg_deprecated_p (const aarch64_sys_reg *reg)
aarch64_sys_reg_deprecated_p (const uint32_t reg_flags)
{
return (reg->flags & F_DEPRECATED) != 0;
}
bfd_boolean
aarch64_sys_reg_supported_p (const aarch64_feature_set features,
const aarch64_sys_reg *reg)
{
if (!(reg->flags & F_ARCHEXT))
return TRUE;
if (!AARCH64_CPU_HAS_ALL_FEATURES (features, reg->features))
return FALSE;
/* ARMv8.4 TLB instructions. */
if ((reg->value == CPENS (0, C8, C1, 0)
|| reg->value == CPENS (0, C8, C1, 1)
|| reg->value == CPENS (0, C8, C1, 2)
|| reg->value == CPENS (0, C8, C1, 3)
|| reg->value == CPENS (0, C8, C1, 5)
|| reg->value == CPENS (0, C8, C1, 7)
|| reg->value == CPENS (4, C8, C4, 0)
|| reg->value == CPENS (4, C8, C4, 4)
|| reg->value == CPENS (4, C8, C1, 1)
|| reg->value == CPENS (4, C8, C1, 5)
|| reg->value == CPENS (4, C8, C1, 6)
|| reg->value == CPENS (6, C8, C1, 1)
|| reg->value == CPENS (6, C8, C1, 5)
|| reg->value == CPENS (4, C8, C1, 0)
|| reg->value == CPENS (4, C8, C1, 4)
|| reg->value == CPENS (6, C8, C1, 0)
|| reg->value == CPENS (0, C8, C6, 1)
|| reg->value == CPENS (0, C8, C6, 3)
|| reg->value == CPENS (0, C8, C6, 5)
|| reg->value == CPENS (0, C8, C6, 7)
|| reg->value == CPENS (0, C8, C2, 1)
|| reg->value == CPENS (0, C8, C2, 3)
|| reg->value == CPENS (0, C8, C2, 5)
|| reg->value == CPENS (0, C8, C2, 7)
|| reg->value == CPENS (0, C8, C5, 1)
|| reg->value == CPENS (0, C8, C5, 3)
|| reg->value == CPENS (0, C8, C5, 5)
|| reg->value == CPENS (0, C8, C5, 7)
|| reg->value == CPENS (4, C8, C0, 2)
|| reg->value == CPENS (4, C8, C0, 6)
|| reg->value == CPENS (4, C8, C4, 2)
|| reg->value == CPENS (4, C8, C4, 6)
|| reg->value == CPENS (4, C8, C4, 3)
|| reg->value == CPENS (4, C8, C4, 7)
|| reg->value == CPENS (4, C8, C6, 1)
|| reg->value == CPENS (4, C8, C6, 5)
|| reg->value == CPENS (4, C8, C2, 1)
|| reg->value == CPENS (4, C8, C2, 5)
|| reg->value == CPENS (4, C8, C5, 1)
|| reg->value == CPENS (4, C8, C5, 5)
|| reg->value == CPENS (6, C8, C6, 1)
|| reg->value == CPENS (6, C8, C6, 5)
|| reg->value == CPENS (6, C8, C2, 1)
|| reg->value == CPENS (6, C8, C2, 5)
|| reg->value == CPENS (6, C8, C5, 1)
|| reg->value == CPENS (6, C8, C5, 5))
&& !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_4))
return FALSE;
return TRUE;
return (reg_flags & F_DEPRECATED) != 0;
}
/* The CPENC below is fairly misleading, the fields
@ -4508,55 +4445,112 @@ aarch64_sys_ins_reg_has_xt (const aarch64_sys_ins_reg *sys_ins_reg)
extern bfd_boolean
aarch64_sys_ins_reg_supported_p (const aarch64_feature_set features,
const aarch64_sys_ins_reg *reg)
aarch64_insn reg_value,
uint32_t reg_flags,
aarch64_feature_set reg_features)
{
if (!(reg->flags & F_ARCHEXT))
if (!(reg_flags & F_ARCHEXT))
return TRUE;
if (reg_features
&& AARCH64_CPU_HAS_ALL_FEATURES (features, reg_features))
return TRUE;
/* ARMv8.4 TLB instructions. */
if ((reg_value == CPENS (0, C8, C1, 0)
|| reg_value == CPENS (0, C8, C1, 1)
|| reg_value == CPENS (0, C8, C1, 2)
|| reg_value == CPENS (0, C8, C1, 3)
|| reg_value == CPENS (0, C8, C1, 5)
|| reg_value == CPENS (0, C8, C1, 7)
|| reg_value == CPENS (4, C8, C4, 0)
|| reg_value == CPENS (4, C8, C4, 4)
|| reg_value == CPENS (4, C8, C1, 1)
|| reg_value == CPENS (4, C8, C1, 5)
|| reg_value == CPENS (4, C8, C1, 6)
|| reg_value == CPENS (6, C8, C1, 1)
|| reg_value == CPENS (6, C8, C1, 5)
|| reg_value == CPENS (4, C8, C1, 0)
|| reg_value == CPENS (4, C8, C1, 4)
|| reg_value == CPENS (6, C8, C1, 0)
|| reg_value == CPENS (0, C8, C6, 1)
|| reg_value == CPENS (0, C8, C6, 3)
|| reg_value == CPENS (0, C8, C6, 5)
|| reg_value == CPENS (0, C8, C6, 7)
|| reg_value == CPENS (0, C8, C2, 1)
|| reg_value == CPENS (0, C8, C2, 3)
|| reg_value == CPENS (0, C8, C2, 5)
|| reg_value == CPENS (0, C8, C2, 7)
|| reg_value == CPENS (0, C8, C5, 1)
|| reg_value == CPENS (0, C8, C5, 3)
|| reg_value == CPENS (0, C8, C5, 5)
|| reg_value == CPENS (0, C8, C5, 7)
|| reg_value == CPENS (4, C8, C0, 2)
|| reg_value == CPENS (4, C8, C0, 6)
|| reg_value == CPENS (4, C8, C4, 2)
|| reg_value == CPENS (4, C8, C4, 6)
|| reg_value == CPENS (4, C8, C4, 3)
|| reg_value == CPENS (4, C8, C4, 7)
|| reg_value == CPENS (4, C8, C6, 1)
|| reg_value == CPENS (4, C8, C6, 5)
|| reg_value == CPENS (4, C8, C2, 1)
|| reg_value == CPENS (4, C8, C2, 5)
|| reg_value == CPENS (4, C8, C5, 1)
|| reg_value == CPENS (4, C8, C5, 5)
|| reg_value == CPENS (6, C8, C6, 1)
|| reg_value == CPENS (6, C8, C6, 5)
|| reg_value == CPENS (6, C8, C2, 1)
|| reg_value == CPENS (6, C8, C2, 5)
|| reg_value == CPENS (6, C8, C5, 1)
|| reg_value == CPENS (6, C8, C5, 5))
&& AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_4))
return TRUE;
/* DC CVAP. Values are from aarch64_sys_regs_dc. */
if (reg->value == CPENS (3, C7, C12, 1)
&& !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2))
return FALSE;
if (reg_value == CPENS (3, C7, C12, 1)
&& AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2))
return TRUE;
/* DC CVADP. Values are from aarch64_sys_regs_dc. */
if (reg->value == CPENS (3, C7, C13, 1)
&& !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_CVADP))
return FALSE;
if (reg_value == CPENS (3, C7, C13, 1)
&& AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_CVADP))
return TRUE;
/* DC <dc_op> for ARMv8.5-A Memory Tagging Extension. */
if ((reg->value == CPENS (0, C7, C6, 3)
|| reg->value == CPENS (0, C7, C6, 4)
|| reg->value == CPENS (0, C7, C10, 4)
|| reg->value == CPENS (0, C7, C14, 4)
|| reg->value == CPENS (3, C7, C10, 3)
|| reg->value == CPENS (3, C7, C12, 3)
|| reg->value == CPENS (3, C7, C13, 3)
|| reg->value == CPENS (3, C7, C14, 3)
|| reg->value == CPENS (3, C7, C4, 3)
|| reg->value == CPENS (0, C7, C6, 5)
|| reg->value == CPENS (0, C7, C6, 6)
|| reg->value == CPENS (0, C7, C10, 6)
|| reg->value == CPENS (0, C7, C14, 6)
|| reg->value == CPENS (3, C7, C10, 5)
|| reg->value == CPENS (3, C7, C12, 5)
|| reg->value == CPENS (3, C7, C13, 5)
|| reg->value == CPENS (3, C7, C14, 5)
|| reg->value == CPENS (3, C7, C4, 4))
&& !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_MEMTAG))
return FALSE;
if ((reg_value == CPENS (0, C7, C6, 3)
|| reg_value == CPENS (0, C7, C6, 4)
|| reg_value == CPENS (0, C7, C10, 4)
|| reg_value == CPENS (0, C7, C14, 4)
|| reg_value == CPENS (3, C7, C10, 3)
|| reg_value == CPENS (3, C7, C12, 3)
|| reg_value == CPENS (3, C7, C13, 3)
|| reg_value == CPENS (3, C7, C14, 3)
|| reg_value == CPENS (3, C7, C4, 3)
|| reg_value == CPENS (0, C7, C6, 5)
|| reg_value == CPENS (0, C7, C6, 6)
|| reg_value == CPENS (0, C7, C10, 6)
|| reg_value == CPENS (0, C7, C14, 6)
|| reg_value == CPENS (3, C7, C10, 5)
|| reg_value == CPENS (3, C7, C12, 5)
|| reg_value == CPENS (3, C7, C13, 5)
|| reg_value == CPENS (3, C7, C14, 5)
|| reg_value == CPENS (3, C7, C4, 4))
&& AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_MEMTAG))
return TRUE;
/* AT S1E1RP, AT S1E1WP. Values are from aarch64_sys_regs_at. */
if ((reg->value == CPENS (0, C7, C9, 0)
|| reg->value == CPENS (0, C7, C9, 1))
&& !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2))
return FALSE;
if ((reg_value == CPENS (0, C7, C9, 0)
|| reg_value == CPENS (0, C7, C9, 1))
&& AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2))
return TRUE;
/* CFP/DVP/CPP RCTX : Value are from aarch64_sys_regs_sr. */
if (reg->value == CPENS (3, C7, C3, 0)
&& !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_PREDRES))
return FALSE;
if (reg_value == CPENS (3, C7, C3, 0)
&& AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_PREDRES))
return TRUE;
return TRUE;
return FALSE;
}
#undef C0

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