riscv
/
binutils-gdb
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity
Browse Source

gas/ 

* config/tc-mips.c (is_opcode_valid): Remove expansionp.
	(macro_build): Change invocation of is_opcode_valid.
	(mips_ip): Likewise.

	gas/testsuite/
	* gas/mips/mips-no-jalx.l: Delete.
	* gas/mips/mips-no-jalx.s: Delete.
	* gas/mips/mips-jalx-2.d: New.
	* gas/mips/mips-jalx-2.s: New.
	* gas/mips/mips.exp (mips-jalx-2): Run new test.
	(mips-no-jalx): Remove deleted test.

	include/
	* opcode/mips.h (INSN_MIPS16): Remove.

	opcodes/
	* mips-dis.c (mips_arch): Remove INSN_MIPS16.
	* mips-opc.c (I16): Remove.
	(mips_builtin_op): Reclassify jalx.
gdb_7_2-branch
Catherine Moore 16 years ago
parent
f9eeb9c926
commit
f79e2745b2
13 changed files with 64 additions and 27 deletions
Whitespace
Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL
Split View
Diff Options
Show Stats Download Patch File Download Diff File
  1. 6
      gas/ChangeLog
  2. 14
      gas/config/tc-mips.c
  3. 9
      gas/testsuite/ChangeLog
  4. 15
      gas/testsuite/gas/mips/mips-jalx-2.d
  5. 10
      gas/testsuite/gas/mips/mips-jalx-2.s
  6. 2
      gas/testsuite/gas/mips/mips-no-jalx.l
  7. 3
      gas/testsuite/gas/mips/mips-no-jalx.s
  8. 2
      gas/testsuite/gas/mips/mips.exp
  9. 4
      include/opcode/ChangeLog
  10. 5
      include/opcode/mips.h
  11. 6
      opcodes/ChangeLog
  12. 10
      opcodes/mips-dis.c
  13. 5
      opcodes/mips-opc.c

6
gas/ChangeLog
View File

@ -1,3 +1,9 @@
2010-05-26 Catherine Moore <clm@codesourcery.com>
* config/tc-mips.c (is_opcode_valid): Remove expansionp.
(macro_build): Change invocation of is_opcode_valid.
(mips_ip): Likewise.
2010-05-25 Nick Clifton <nickc@redhat.com>
* Makefile.am (MOSTLYCLEANFILES): Fix typo.

14
gas/config/tc-mips.c
View File

@ -1817,11 +1817,10 @@ reg_lookup (char **s, unsigned int types, unsigned int *regnop)
}
/* Return TRUE if opcode MO is valid on the currently selected ISA and
architecture. If EXPANSIONP is TRUE then this check is done while
expanding a macro. Use is_opcode_valid_16 for MIPS16 opcodes. */
architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
static bfd_boolean
is_opcode_valid (const struct mips_opcode *mo, bfd_boolean expansionp)
is_opcode_valid (const struct mips_opcode *mo)
{
int isa = mips_opts.isa;
int fp_s, fp_d;
@ -1841,11 +1840,6 @@ is_opcode_valid (const struct mips_opcode *mo, bfd_boolean expansionp)
if (mips_opts.ase_smartmips)
isa |= INSN_SMARTMIPS;
/* For user code we don't check for mips_opts.mips16 since we want
to allow jalx if -mips16 was specified on the command line. */
if (expansionp ? mips_opts.mips16 : file_ase_mips16)
isa |= INSN_MIPS16;
/* Don't accept instructions based on the ISA if the CPU does not implement
all the coprocessor insns. */
if (NO_ISA_COP (mips_opts.arch)
@ -3638,7 +3632,7 @@ macro_build (expressionS *ep, const char *name, const char *fmt, ...)
macros will never generate MDMX, MIPS-3D, or MT instructions. */
if (strcmp (fmt, mo->args) == 0
&& mo->pinfo != INSN_MACRO
&& is_opcode_valid (mo, TRUE))
&& is_opcode_valid (mo))
break;
++mo;
@ -8776,7 +8770,7 @@ mips_ip (char *str, struct mips_cl_insn *ip)
gas_assert (strcmp (insn->name, str) == 0);
ok = is_opcode_valid (insn, FALSE);
ok = is_opcode_valid (insn);
if (! ok)
{
if (insn + 1 < &mips_opcodes[NUMOPCODES]

9
gas/testsuite/ChangeLog
View File

@ -1,3 +1,12 @@
2010-05-26 Catherine Moore <clm@codesoucery.com>
* gas/mips/mips-no-jalx.l: Delete.
* gas/mips/mips-no-jalx.s: Delete.
* gas/mips/mips-jalx-2.d: New.
* gas/mips/mips-jalx-2.s: New.
* gas/mips/mips.exp (mips-jalx-2): Run new test.
(mips-no-jalx): Remove deleted test.
2010-05-25 Daniel Jacobowitz <dan@codesourcery.com>
Joseph Myers <joseph@codesourcery.com>
Andrew Stubbs <ams@codesourcery.com>

15
gas/testsuite/gas/mips/mips-jalx-2.d
View File

@ -0,0 +1,15 @@
#objdump: -d
#as:
#name: mips jalx-2
.*: file format .*
Disassembly of section .text:
[ 0-9a-f]+ <text_sym>:
[ 0-9a-f]+: 74000000 jalx 0 <.[^>]*>
[ 0-9a-f]+: 00000000 nop
[ 0-9a-f]+ <.[^>]*>:
[ 0-9a-f]+: 6500 nop
\.\.\.

10
gas/testsuite/gas/mips/mips-jalx-2.s
View File

@ -0,0 +1,10 @@
text_sym:
.text
jalx 1f
.set mips16
.align 1
1: nop
.set nomips16
.align 2
.fill 8

2
gas/testsuite/gas/mips/mips-no-jalx.l
View File

@ -1,2 +0,0 @@
.*: Assembler messages:
.*:3: Error: opcode not supported (at this ISA level|on this processor: .*) \(mips.*\) `jalx external_label'

3
gas/testsuite/gas/mips/mips-no-jalx.s
View File

@ -1,3 +0,0 @@
# Test the generation of jalx opcodes
.set nomips16
jalx external_label

2
gas/testsuite/gas/mips/mips.exp
View File

@ -526,6 +526,7 @@ if { [istarget mips*-*-vxworks*] } {
# Check jalx handling
run_dump_test "mips16-jalx"
run_dump_test "mips-jalx"
run_dump_test "mips-jalx-2"
# Check MIPS16 HI16/LO16 relocations
run_dump_test "mips16-hilo"
if $has_newabi {
@ -533,7 +534,6 @@ if { [istarget mips*-*-vxworks*] } {
}
run_dump_test "mips16-hilo-match"
}
run_list_test "mips-no-jalx" "-32"
run_dump_test "delay"
run_dump_test "nodelay"
run_dump_test "mips4010"

4
include/opcode/ChangeLog
View File

@ -1,3 +1,7 @@
2010-05-26 Catherine Moore <clm@codesourcery.com>
* opcode/mips.h (INSN_MIPS16): Remove.
2010-04-21 Joseph Myers <joseph@codesourcery.com>
* tic6x-insn-formats.h (s_branch): Correct typo in bitmask.

5
include/opcode/mips.h
View File

@ -555,8 +555,9 @@ static const unsigned int mips_isa_table[] =
/* DSP ASE */
#define INSN_DSP 0x00001000
#define INSN_DSP64 0x00002000
/* MIPS 16 ASE */
#define INSN_MIPS16 0x00004000
/* 0x00004000 is unused. */
/* MIPS-3D ASE */
#define INSN_MIPS3D 0x00008000

6
opcodes/ChangeLog
View File

@ -1,3 +1,9 @@
2010-05-26 Catherine Moore <clm@codesoourcery.com>
* mips-dis.c (mips_arch): Remove INSN_MIPS16.
* mips-opc.c (I16): Remove.
(mips_builtin_op): Reclassify jalx.
2010-05-19 Alan Modra <amodra@gmail.com>
* ppc-opc.c (powerpc_opcodes): Enable divdeu, devweu, divde,

10
opcodes/mips-dis.c
View File

@ -472,13 +472,13 @@ const struct mips_arch_choice mips_arch_choices[] =
MIPS32 Architecture_ (MIPS Document Number MD00082, Revision 0.95),
page 1. */
{ "mips32", 1, bfd_mach_mipsisa32, CPU_MIPS32,
ISA_MIPS32 | INSN_MIPS16 | INSN_SMARTMIPS,
ISA_MIPS32 | INSN_SMARTMIPS,
mips_cp0_names_mips3264,
mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264),
mips_hwr_names_numeric },
{ "mips32r2", 1, bfd_mach_mipsisa32r2, CPU_MIPS32R2,
(ISA_MIPS32R2 | INSN_MIPS16 | INSN_SMARTMIPS | INSN_DSP | INSN_DSPR2
(ISA_MIPS32R2 | INSN_SMARTMIPS | INSN_DSP | INSN_DSPR2
| INSN_MIPS3D | INSN_MT),
mips_cp0_names_mips3264r2,
mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
@ -486,13 +486,13 @@ const struct mips_arch_choice mips_arch_choices[] =
/* For stock MIPS64, disassemble all applicable MIPS-specified ASEs. */
{ "mips64", 1, bfd_mach_mipsisa64, CPU_MIPS64,
ISA_MIPS64 | INSN_MIPS16 | INSN_MIPS3D | INSN_MDMX,
ISA_MIPS64 | INSN_MIPS3D | INSN_MDMX,
mips_cp0_names_mips3264,
mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264),
mips_hwr_names_numeric },
{ "mips64r2", 1, bfd_mach_mipsisa64r2, CPU_MIPS64R2,
(ISA_MIPS64R2 | INSN_MIPS16 | INSN_MIPS3D | INSN_DSP | INSN_DSPR2
(ISA_MIPS64R2 | INSN_MIPS3D | INSN_DSP | INSN_DSPR2
| INSN_DSP64 | INSN_MT | INSN_MDMX),
mips_cp0_names_mips3264r2,
mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
@ -524,7 +524,7 @@ const struct mips_arch_choice mips_arch_choices[] =
/* This entry, mips16, is here only for ISA/processor selection; do
not print its name. */
{ "", 1, bfd_mach_mips16, CPU_MIPS16, ISA_MIPS3 | INSN_MIPS16,
{ "", 1, bfd_mach_mips16, CPU_MIPS16, ISA_MIPS3,
mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
};

5
opcodes/mips-opc.c
View File

@ -96,9 +96,6 @@
#define I4_33 INSN_ISA4_32R2
#define I5_33 INSN_ISA5_32R2
/* MIPS16 ASE support. */
#define I16 INSN_MIPS16
/* MIPS64 MIPS-3D ASE support. */
#define M3D INSN_MIPS3D
@ -739,7 +736,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
assembler, but will never match user input (because the line above
will match first). */
{"jal", "a", 0x0c000000, 0xfc000000, UBD|WR_31, 0, I1 },
{"jalx", "a", 0x74000000, 0xfc000000, UBD|WR_31, 0, I16 },
{"jalx", "a", 0x74000000, 0xfc000000, UBD|WR_31, 0, I1 },
{"la", "t,A(b)", 0, (int) M_LA_AB, INSN_MACRO, 0, I1 },
{"lb", "t,o(b)", 0x80000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 },
{"lb", "t,A(b)", 0, (int) M_LB_AB, INSN_MACRO, 0, I1 },

Write Preview
Loading…
Cancel
Save