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* gas/config/tc-arm.c (arm_ext_adiv): New variable. 

(do_div): New function.
	(insns): Accept UDIV and SDIV in ARM state.
	(arm_cpus): The cortex-a15 option has all current v7-A extensions.
	(arm_extensions): Add 'idiv' extension.
	(aeabi_set_public_attributes): Update Tag_DIV_use values for the
	Integer Divide extension.
	* gas/doc/c-arm.texi: Document the idiv extension.
	* gas/testsuite/gas/arm/armv7-a+idiv.d: New test.
	* gas/testsuite/gas/arm/armv7-a+idiv.s: Likewise.
	* gas/testsuite/gas/arm/attr-march-all.d: Update for Integer divide extension.
	* gas/testsuite/gas/arm/attr-march-armv7-a+idiv.d: New test.
	* include/opcode/arm.h (ARM_AEXT_ADIV): New define.
	(ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
	* opcodes/arm-dis.c (arm_opcodes): Support disassembly of UDIV and SDIV in
	ARM state.
binutils-2_21-branch
Matthew Gretton-Dann 16 years ago
parent
b2a5fbdc94
commit
eea54501f7
12 changed files with 112 additions and 10 deletions
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  1. 11
      gas/ChangeLog
  2. 41
      gas/config/tc-arm.c
  3. 3
      gas/doc/c-arm.texi
  4. 7
      gas/testsuite/ChangeLog
  5. 10
      gas/testsuite/gas/arm/armv7-a+idiv.d
  6. 14
      gas/testsuite/gas/arm/armv7-a+idiv.s
  7. 1
      gas/testsuite/gas/arm/attr-march-all.d
  8. 15
      gas/testsuite/gas/arm/attr-march-armv7-a+idiv.d
  9. 5
      include/opcode/ChangeLog
  10. 6
      include/opcode/arm.h
  11. 5
      opcodes/ChangeLog
  12. 4
      opcodes/arm-dis.c

11
gas/ChangeLog
View File

@ -1,3 +1,14 @@
2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
* config/tc-arm.c (arm_ext_adiv): New variable.
(do_div): New function.
(insns): Accept UDIV and SDIV in ARM state.
(arm_cpus): The cortex-a15 option has all current v7-A extensions.
(arm_extensions): Add 'idiv' extension.
(aeabi_set_public_attributes): Update Tag_DIV_use values for the
Integer Divide extension.
* doc/c-arm.texi: Document the idiv extension.
2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
* config/tc-arm.c (arm_ext_v6m): New variable.

41
gas/config/tc-arm.c
View File

@ -200,6 +200,7 @@ static const arm_feature_set arm_ext_m =
static const arm_feature_set arm_ext_mp = ARM_FEATURE (ARM_EXT_MP, 0);
static const arm_feature_set arm_ext_sec = ARM_FEATURE (ARM_EXT_SEC, 0);
static const arm_feature_set arm_ext_os = ARM_FEATURE (ARM_EXT_OS, 0);
static const arm_feature_set arm_ext_adiv = ARM_FEATURE (ARM_EXT_ADIV, 0);
static const arm_feature_set arm_arch_any = ARM_ANY;
static const arm_feature_set arm_arch_full = ARM_FEATURE (-1, -1);
@ -7491,6 +7492,25 @@ do_dbg (void)
inst.instruction |= inst.operands[0].imm;
}
static void
do_div (void)
{
unsigned Rd, Rn, Rm;
Rd = inst.operands[0].reg;
Rn = (inst.operands[1].present
? inst.operands[1].reg : Rd);
Rm = inst.operands[2].reg;
constraint ((Rd == REG_PC), BAD_PC);
constraint ((Rn == REG_PC), BAD_PC);
constraint ((Rm == REG_PC), BAD_PC);
inst.instruction |= Rd << 16;
inst.instruction |= Rn << 0;
inst.instruction |= Rm << 8;
}
static void
do_it (void)
{
@ -17130,12 +17150,14 @@ static const struct asm_opcode insns[] =
TCE("tbb", 0, e8d0f000, 1, (TB), 0, t_tb),
TCE("tbh", 0, e8d0f010, 1, (TB), 0, t_tb),
/* Thumb-2 hardware division instructions (R and M profiles only). */
/* Hardware division instructions. */
#undef ARM_VARIANT
#define ARM_VARIANT & arm_ext_adiv
#undef THUMB_VARIANT
#define THUMB_VARIANT & arm_ext_div
TCE("sdiv", 0, fb90f0f0, 3, (RR, oRR, RR), 0, t_div),
TCE("udiv", 0, fbb0f0f0, 3, (RR, oRR, RR), 0, t_div),
TCE("sdiv", 710f010, fb90f0f0, 3, (RR, oRR, RR), div, t_div),
TCE("udiv", 730f010, fbb0f0f0, 3, (RR, oRR, RR), div, t_div),
/* ARM V6M/V7 instructions. */
#undef ARM_VARIANT
@ -22408,8 +22430,8 @@ static const struct arm_cpu_option_table arm_cpus[] =
ARM_FEATURE (0, FPU_VFP_V3
| FPU_NEON_EXT_V1),
"Cortex-A9"},
{"cortex-a15", ARM_ARCH_V7A_MP_SEC,
FPU_ARCH_NEON_VFP_V4,
{"cortex-a15", ARM_ARCH_V7A_IDIV_MP_SEC,
FPU_ARCH_NEON_VFP_V4,
"Cortex-A15"},
{"cortex-r4", ARM_ARCH_V7R, FPU_NONE, "Cortex-R4"},
{"cortex-r4f", ARM_ARCH_V7R, FPU_ARCH_VFP_V3D16,
@ -22496,6 +22518,8 @@ struct arm_option_extension_value_table
*/
static const struct arm_option_extension_value_table arm_extensions[] =
{
{"idiv", ARM_FEATURE (ARM_EXT_ADIV | ARM_EXT_DIV, 0),
ARM_FEATURE (ARM_EXT_V7A, 0)},
{"iwmmxt", ARM_FEATURE (0, ARM_CEXT_IWMMXT), ARM_ANY},
{"iwmmxt2", ARM_FEATURE (0, ARM_CEXT_IWMMXT2), ARM_ANY},
{"maverick", ARM_FEATURE (0, ARM_CEXT_MAVERICK), ARM_ANY},
@ -23177,11 +23201,10 @@ aeabi_set_public_attributes (void)
aeabi_set_attribute_int (Tag_VFP_HP_extension, 1);
/* Tag_DIV_use. */
if (ARM_CPU_HAS_FEATURE (flags, arm_ext_div))
if (ARM_CPU_HAS_FEATURE (flags, arm_ext_adiv))
aeabi_set_attribute_int (Tag_DIV_use, 2);
else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_div))
aeabi_set_attribute_int (Tag_DIV_use, 0);
/* Fill this in when gas supports v7a sdiv/udiv.
else if (... v7a with div extension used ...)
aeabi_set_attribute_int (Tag_DIV_use, 2); */
else
aeabi_set_attribute_int (Tag_DIV_use, 1);

3
gas/doc/c-arm.texi
View File

@ -148,7 +148,8 @@ been added, again in ascending alphabetical order. For example,
@code{-mcpu=ep9312+nomaverick} is equivalent to specifying @code{-mcpu=arm920}.
The following extensions are currently supported:
The following extensions are currently supported:
@code{idiv}, (Integer Divide Extensions for v7-A architecture),
@code{iwmmxt},
@code{iwmmxt2},
@code{maverick},

7
gas/testsuite/ChangeLog
View File

@ -1,3 +1,10 @@
2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
* gas/arm/armv7-a+idiv.d: New test.
* gas/arm/armv7-a+idiv.s: Likewise.
* gas/arm/attr-march-all.d: Update for Integer divide extension.
* gas/arm/attr-march-armv7-a+idiv.d: New test.
2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
* gas/arm/archv6s-m-bad.d: New test.

10
gas/testsuite/gas/arm/armv7-a+idiv.d
View File

@ -0,0 +1,10 @@
#name: Valid v7-A+IDIV
#objdump: -dr --prefix-addresses --show-raw-insn
.*: +file format .*arm.*
Disassembly of section .text:
0[0-9a-f]+ <[^>]+> e730f211 udiv r0, r1, r2
0[0-9a-f]+ <[^>]+> e710f211 sdiv r0, r1, r2
0[0-9a-f]+ <[^>]+> fbb1 f0f2 udiv r0, r1, r2
0[0-9a-f]+ <[^>]+> fb91 f0f2 sdiv r0, r1, r2

14
gas/testsuite/gas/arm/armv7-a+idiv.s
View File

@ -0,0 +1,14 @@
.syntax unified
.text
.arch armv7-a
.arch_extension idiv
foo:
udiv r0, r1, r2
sdiv r0, r1, r2
.thumb
.thumb_func
bar:
udiv r0, r1, r2
sdiv r0, r1, r2

1
gas/testsuite/gas/arm/attr-march-all.d
View File

@ -13,4 +13,5 @@ File Attributes
Tag_ARM_ISA_use: Yes
Tag_THUMB_ISA_use: Thumb-2
Tag_MPextension_use: Allowed
Tag_DIV_use: Allowed in v7-A with integer division extension
Tag_Virtualization_use: TrustZone

15
gas/testsuite/gas/arm/attr-march-armv7-a+idiv.d
View File

@ -0,0 +1,15 @@
# name: attributes for -march=armv7-a+idiv
# source: blank.s
# as: -march=armv7-a+idiv
# readelf: -A
# This test is only valid on EABI based ports.
# target: *-*-*eabi
Attribute Section: aeabi
File Attributes
Tag_CPU_name: "7-A"
Tag_CPU_arch: v7
Tag_CPU_arch_profile: Application
Tag_ARM_ISA_use: Yes
Tag_THUMB_ISA_use: Thumb-2
Tag_DIV_use: Allowed in v7-A with integer division extension

5
include/opcode/ChangeLog
View File

@ -1,3 +1,8 @@
2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
* arm.h (ARM_AEXT_ADIV): New define.
(ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
* arm.h (ARM_EXT_OS): New define.

6
include/opcode/arm.h
View File

@ -52,6 +52,8 @@
#define ARM_EXT_MP 0x08000000 /* Multiprocessing Extensions. */
#define ARM_EXT_SEC 0x10000000 /* Security extensions. */
#define ARM_EXT_OS 0x20000000 /* OS Extensions. */
#define ARM_EXT_ADIV 0x40000000 /* Integer divide extensions in ARM
state. */
/* Co-processor space extensions. */
#define ARM_CEXT_XSCALE 0x00000001 /* Allow MIA etc. */
@ -220,6 +222,10 @@
#define ARM_ARCH_V7A_MP_SEC \
ARM_FEATURE (ARM_AEXT_V7A | ARM_EXT_MP | ARM_EXT_SEC, \
0)
/* v7-a+idiv+mp+sec. */
#define ARM_ARCH_V7A_IDIV_MP_SEC \
ARM_FEATURE (ARM_AEXT_V7A | ARM_EXT_MP | ARM_EXT_SEC \
| ARM_EXT_DIV | ARM_EXT_ADIV, 0)
/* There are too many feature bits to fit in a single word, so use a
structure. For simplicity we put all core features in one word and

5
opcodes/ChangeLog
View File

@ -1,3 +1,8 @@
2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
* arm-dis.c (arm_opcodes): Support disassembly of UDIV and SDIV in
ARM state.
2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
* arm-dis.c (arm_opcodes): SMC implies Security Extensions.

4
opcodes/arm-dis.c
View File

@ -829,6 +829,10 @@ static const struct opcode32 arm_opcodes[] =
{ARM_EXT_V3M, 0x00800090, 0x0fa000f0, "%22?sumull%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
{ARM_EXT_V3M, 0x00a00090, 0x0fa000f0, "%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
/* Integer Divide Extension instructions. */
{ARM_EXT_ADIV, 0x0710f010, 0x0ff0f0f0, "sdiv%c\t%16-19r, %0-3r, %8-11r"},
{ARM_EXT_ADIV, 0x0730f010, 0x0ff0f0f0, "udiv%c\t%16-19r, %0-3r, %8-11r"},
/* MP Extension instructions. */
{ARM_EXT_MP, 0xf410f000, 0xfc70f000, "pldw\t%a"},

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