* iq2000: New target subdirectory.

* configure.ac: Add iq2000 target. * configure: Regenerate.
22 years ago · edece23776
25 changed files with 21933 additions and 0 deletions
--- a/sim/ChangeLog
+++ b/sim/ChangeLog
@ -1,3 +1,9 @@
+2005-02-18  Corinna Vinschen  <vinschen@redhat.com>
+
+	* iq2000: New target subdirectory.
+	* configure.ac: Add iq2000 target.
+	* configure: Regenerate.
+
 2005-01-29  Hans-Peter Nilsson  <hp@axis.com>

 	* Makefile.in (all, clean mostlyclean, distclean maintainer-clean)
--- a/sim/configure
+++ b/sim/configure
@ -277,6 +277,7 @@ ac_subdirs_all="$ac_subdirs_all cris"
 ac_subdirs_all="$ac_subdirs_all d10v"
 ac_subdirs_all="$ac_subdirs_all frv"
 ac_subdirs_all="$ac_subdirs_all h8300"
+ac_subdirs_all="$ac_subdirs_all iq2000"
 ac_subdirs_all="$ac_subdirs_all m32r"
 ac_subdirs_all="$ac_subdirs_all m68hc11"
 ac_subdirs_all="$ac_subdirs_all mcore"
@ -3445,6 +3446,14 @@ subdirs="$subdirs frv"

 subdirs="$subdirs h8300"

+	   testsuite=yes
+	   common=yes
+	   ;;
+       iq2000-*-*)
+
+
+subdirs="$subdirs iq2000"
+
 	   testsuite=yes
 	   common=yes
 	   ;;
--- a/sim/configure.ac
+++ b/sim/configure.ac
@ -68,6 +68,11 @@ if test "${enable_sim}" != no; then
 	   testsuite=yes
 	   common=yes
 	   ;;
+       iq2000-*-*)
+           AC_CONFIG_SUBDIRS(iq2000)
+	   testsuite=yes
+	   common=yes
+	   ;;
       m32r-*-*)
           AC_CONFIG_SUBDIRS(m32r)
 	   testsuite=yes
--- a/sim/iq2000/ChangeLog
+++ b/sim/iq2000/ChangeLog
@ -0,0 +1,181 @@
+2005-02-21  Corinna Vinschen  <vinschen@redhat.com>
+
+	* iq2000.c: Eliminate need to include gdb/sim-iq2000.h.
+
+2005-02-18  Corinna Vinschen  <vinschen@redhat.com>
+
+	* configure.ac: Rename from configure.in and pull up to autoconf 2.59.
+	* configure: Regenerate.
+
+2002-03-18  Jeff Johnston  <jjohnstn@redhat.com>
+
+	* sem-switch.c: Regenerated.
+	* sem.c: Ditto.
+
+2002-01-28  Jeff Johnston  <jjohnstn@redhat.com>
+
+	* arch.c: Regenerated.
+	* arch.h: Ditto.
+	* cpu.c: Ditto.
+	* cpu.h: Ditto.
+	* cpuall.h: Ditto.
+	* decode.c: Ditto.
+	* decode.h: Ditto.
+	* model.c: Ditto.
+	* sem-switch.c: Ditto.
+	* sem.c: Ditto.
+
+2001-11-16  Jeff Johnston  <jjohnstn@redhat.com>
+
+	* decode.c: Regenerated after putting orui into machine-specific
+	files.
+	* decode.h: Ditto.
+	* model.c: Ditto.
+	* sem-switch.c: Ditto.
+	* sem.c: Ditto.
+
+2001-11-13  Jeff Johnston  <jjohnstn@redhat.com>
+
+	* cpu.h: Regenerated after changing jump and branch operands
+	so that no bit masking is performed.
+	* decode.c: Ditto.
+	* iq2000.c (get_h_pc): Change to return h_pc directly.
+	(set_h_pc): Change to always set the insn mask bit.
+	* sim-if.c (iq2000bf_disassemble_insn): Change to pass the
+	pc untouched.
+	(sim_create_inferior): Changed so starting address is taken
+	directly from link.  If not specified, start address is
+	0 with insn mask set on.
+
+2001-11-08  Jeff Johnston  <jjohnstn@redhat.com>
+
+	* cpu.h: Regenerated after making jump operand UINT.
+	* decode.c: Ditto.
+
+2001-10-31  Jeff Johnston  <jjohnstn@redhat.com>
+
+	* sem-switch.c: Regenerated after fixing lb, lbu, lh, lw,
+	sb, sh, and sw insns handling of offset operand.
+	* sem.c: Ditto.
+
+2001-10-30  Jeff Johnston  <jjohnstn@redhat.com>
+
+	* cpu.c: Regenerated.
+	* cpu.h: Ditto.
+	* decode.c: Ditto.
+	* sem-switch.c: Ditto.
+	* sem.c: Ditto.
+	* iq2000.c (get_h_pc): New routine.
+	(set_h_pc): Ditto.
+	(fetch_str): Translate cpu data addresses to data area.
+	(do_syscall): Ditto.
+	(iq2000bf_fetch_register): Use get_h_pc.
+	(iq2000bf_store_register): Use set_h_pc.
+	* mloop.in: Change all calls to GETIMEMxxx to use CPU2INSN
+	on the pc value passed first.
+	* sim-if.c (iq2000bf_disassemble_insn): New function.
+	(sim_open): Add extra memory region for insn memory vs data memory.
+	Also change disassembler to be iq2000bf_disassemble_insn.
+	(sim_create_inferior): Translate start address using INSN2CPU macro.
+	* sim-main.h (CPU2INSN, CPU2DATA, INSN2CPU, DATA2CPU): New macros
+	to translate between Harvard and cpu addresses.
+
+2001-10-26  Jeff Johnston  <jjohnstn@redhat.com>
+
+	* sem-switch.c: Regenerated after reverting addiu
+	change.
+	* sem.c: Ditto.
+
+2001-10-25  Jeff Johnston  <jjohnstn@redhat.com>
+
+	* Makefile.in: Add -UHAVE_CPU_IQ10 for time-being until
+	iq10 simulator merged here.
+	* cpu.h: Regenerated after fixing addiu insn.
+	* cpuall.h: Ditto.
+	* decode.c: Ditto.
+	* decode.h: Ditto.
+	* model.c: Ditto.
+	* sem-switch.c: Ditto.
+	* sem.c: Ditto.
+
+2001-09-12  Stan Cox  <scox@redhat.com>
+
+	* iq2000/{cpu.c, cpu.h, decode.c, decode.h, model.c, sem-switch.c,
+	sem.c}: Regen'd.
+	* iq2000.c (do_syscall): Support system traps.
+	
+2001-07-05  Ben Elliston  <bje@redhat.com>
+
+	* Makefile.in (stamp-arch): Use $(CGEN_CPU_DIR).
+	(stamp-cpu): Likewise.
+
+2001-04-02  Ben Elliston  <bje@redhat.com>
+
+	* arch.c, arch.h: Regnerate to track recent cgen improvements.
+	* cpu.c, cpu.h, cpuall.h, decode.c, decode.h: Likewise.
+	* model.c, sem-switch.c, sem.c: Likewise.
+
+2001-01-22  Ben Elliston  <bje@redhat.com>
+
+	* cpu.h, decode.c, decode.h, model.c: Regenerate.
+	* sem.c, sem-switch.c: Likewise.
+
+	* arch.c, arch.h, cpu.c, cpu.h, cpuall.h: Regenerate.
+	* decode.c, decode.h, model.c, sem.c, sem-switch.c: Likewise.
+
+2000-07-05  Ben Elliston  <bje@redhat.com>
+
+	* configure: Regenerated to track ../common/aclocal.m4 changes.
+
+2000-07-04  Ben Elliston  <bje@redhat.com>
+
+	* sem.c, sem-switch.c: Regenerate.
+
+	* iq2000.c (do_break): Use sim_engine_halt ().
+	* arch.c, decode.c, decode.h, sem.c, sem-switch.c: Regenerate.
+
+2000-07-03  Ben Elliston  <bje@redhat.com>
+
+	* iq2000.c (do_syscall): Examine syscall register (nominally %11).
+	(do_break): Handle breakpoints.
+	* tconfig.in (SIM_HAVE_BREAKPOINTS): Define.
+	(SIM_BREAKPOINT, SIM_BREAKPOINT_SIZE): Likewise.
+
+2000-06-29  Andrew Cagney  <cagney@redhat.com>
+
+	* iq2000.c (iq2000bf_fetch_register): Implement.
+	(iq2000bf_store_register): Ditto.
+
+2000-05-17  Ben Elliston  <bje@redhat.com>
+
+	* mloop.in (extract-simple, extract-scache): Use SEM_SKIP_COMPILE
+	to set the skip count for the (skip ..) rtx.
+	(extract-pbb): Likewise.
+	(extract-pbb): Include the delay slot instruction of all CTI
+	instructions in the pbb, not just those that may nullify their
+	delay slot (eg. likely branches).
+
+	* sem.c, sem-switch.c: Regenerate.
+
+2000-05-16  Ben Elliston  <bje@redhat.com>
+
+	* arch.c, cpu.c, cpu.h, decode.c, decode.h: Regenerate.
+	* sem.c, sem-switch.c: Likewise.
+	* mloop.in (extract-pbb): Prohibit branch instructions in the
+	delay slot of branch likely instructions.
+
+2000-05-16  Ben Elliston  <bje@redhat.com>
+
+	* Makefile.in: New file.
+	* configure.in: Ditto.
+	* acconfig.h: Ditto.
+	* config.in, configure: Generate.
+	* arch.c, arch.h, cpu.c, cpu.h, cpuall.h: Ditto.
+	* decode.c, decode.h: Ditto.
+	* model.c, sem-switch.c, sem.c: Ditto.
+	* mloop.in: New file.
+	* iq2000.c: Ditto.
+	* iq2000-sim.h: Ditto.
+	* sim-if.c: Ditto.
+	* sim-main.h: Ditto.
+	* tconfig.in: Ditto
--- a/sim/iq2000/Makefile.in
+++ b/sim/iq2000/Makefile.in
@ -0,0 +1,108 @@
+# Makefile template for Configure for the IQ2000 simulator
+# Copyright (C) 1998 Free Software Foundation, Inc.
+# Contributed by Cygnus Support.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License along
+# with this program; if not, write to the Free Software Foundation, Inc.,
+# 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+## COMMON_PRE_CONFIG_FRAG
+
+IQ2000_OBJS = iq2000.o cpu.o decode.o sem.o model.o mloop.o
+
+CONFIG_DEVICES = dv-sockser.o
+CONFIG_DEVICES =
+
+SIM_OBJS = \
+	$(SIM_NEW_COMMON_OBJS) \
+	sim-cpu.o \
+	sim-hload.o \
+	sim-hrw.o \
+	sim-model.o \
+	sim-reg.o \
+	cgen-utils.o cgen-trace.o cgen-scache.o \
+	cgen-run.o sim-reason.o sim-engine.o sim-stop.o \
+	sim-if.o arch.o \
+	$(IQ2000_OBJS) \
+	$(CONFIG_DEVICES)
+
+# Extra headers included by sim-main.h.
+SIM_EXTRA_DEPS = \
+	$(CGEN_INCLUDE_DEPS) \
+	arch.h cpuall.h iq2000-sim.h $(srcdir)/../../opcodes/iq2000-desc.h
+
+SIM_EXTRA_CFLAGS =
+
+ALL_CPU_CFLAGS = -DHAVE_CPU_IQ2000BF -DHAVE_CPU_IQ10BF
+
+SIM_RUN_OBJS = nrun.o
+SIM_EXTRA_CLEAN = iq2000-clean
+
+## COMMON_POST_CONFIG_FRAG
+
+arch = iq2000
+
+sim-if.o: $(srcdir)/sim-if.c $(SIM_MAIN_DEPS) $(srcdir)/../common/sim-core.h
+
+arch.o: arch.c $(SIM_MAIN_DEPS)
+	$(CC) -c $(srcdir)/arch.c $(ALL_CFLAGS) -UHAVE_CPU_IQ10BF
+
+devices.o: $(srcdir)/devices.c $(SIM_MAIN_DEPS)
+
+# IQ2000 objs
+
+IQ2000BF_INCLUDE_DEPS = \
+	$(CGEN_MAIN_CPU_DEPS) \
+	cpu.h decode.h eng.h
+
+iq2000.o: $(srcdir)/iq2000.c $(IQ2000BF_INCLUDE_DEPS)
+
+# FIXME: Use of `mono' is wip.
+mloop.c eng.h: stamp-mloop
+stamp-mloop: $(srcdir)/../common/genmloop.sh mloop.in Makefile
+	$(SHELL) $(srccom)/genmloop.sh \
+		-mono -fast -pbb -switch sem-switch.c \
+		-cpu iq2000bf -infile $(srcdir)/mloop.in
+	$(SHELL) $(srcroot)/move-if-change eng.hin eng.h
+	$(SHELL) $(srcroot)/move-if-change mloop.cin mloop.c
+	touch stamp-mloop
+mloop.o: mloop.c $(srcdir)/sem-switch.c $(IQ2000BF_INCLUDE_DEPS)
+
+cpu.o: $(srcdir)/cpu.c $(IQ2000BF_INCLUDE_DEPS)
+decode.o: $(srcdir)/decode.c $(IQ2000BF_INCLUDE_DEPS)
+sem.o: $(srcdir)/sem.c $(IQ2000BF_INCLUDE_DEPS)
+model.o: $(srcdir)/model.c $(IQ2000BF_INCLUDE_DEPS)
+
+iq2000-clean:
+	rm -f mloop.c eng.h stamp-mloop
+	rm -f tmp-*
+	rm -f stamp-arch stamp-cpu
+
+# cgen support, enable with --enable-cgen-maint
+CGEN_MAINT = ; @true
+# The following line is commented in or out depending upon --enable-cgen-maint.
+@CGEN_MAINT@CGEN_MAINT =
+
+stamp-arch: $(CGEN_READ_SCM) $(CGEN_ARCH_SCM) $(CGEN_CPU_DIR)/iq2000.cpu Makefile
+	$(MAKE) cgen-arch $(CGEN_FLAGS_TO_PASS) mach=iq2000 \
+	  FLAGS="with-scache with-profile=fn"
+	touch stamp-arch
+arch.h arch.c cpuall.h: $(CGEN_MAINT) stamp-arch
+	@true
+
+stamp-cpu: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_DECODE_SCM) $(CGEN_CPU_DIR)/iq2000.cpu Makefile
+	$(MAKE) cgen-cpu-decode $(CGEN_FLAGS_TO_PASS) \
+	  cpu=iq2000bf mach=iq2000 FLAGS="with-scache with-profile=fn" EXTRAFILES="$(CGEN_CPU_SEM) $(CGEN_CPU_SEMSW)"
+	touch stamp-cpu
+cpu.h sem.c sem-switch.c model.c decode.c decode.h: $(CGEN_MAINT) stamp-cpu
+	@true
--- a/sim/iq2000/acconfig.h
+++ b/sim/iq2000/acconfig.h
@ -0,0 +1,15 @@
+
+/* Define to 1 if NLS is requested.  */
+#undef ENABLE_NLS
+
+/* Define as 1 if you have catgets and don't want to use GNU gettext.  */
+#undef HAVE_CATGETS
+
+/* Define as 1 if you have gettext and don't want to use GNU gettext.  */
+#undef HAVE_GETTEXT
+
+/* Define as 1 if you have the stpcpy function.  */
+#undef HAVE_STPCPY
+
+/* Define if your locale.h file contains LC_MESSAGES.  */
+#undef HAVE_LC_MESSAGES
--- a/sim/iq2000/arch.c
+++ b/sim/iq2000/arch.c
@ -0,0 +1,35 @@
+/* Simulator support for iq2000.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
+
+This file is part of the GNU simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+
+#include "sim-main.h"
+#include "bfd.h"
+
+const MACH *sim_machs[] =
+{
+#ifdef HAVE_CPU_IQ2000BF
+  & iq2000_mach,
+#endif
+  0
+};
+
--- a/sim/iq2000/arch.h
+++ b/sim/iq2000/arch.h
@ -0,0 +1,44 @@
+/* Simulator header for iq2000.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
+
+This file is part of the GNU simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+
+#ifndef IQ2000_ARCH_H
+#define IQ2000_ARCH_H
+
+#define TARGET_BIG_ENDIAN 1
+
+/* Enum declaration for model types.  */
+typedef enum model_type {
+  MODEL_IQ2000, MODEL_MAX
+} MODEL_TYPE;
+
+#define MAX_MODELS ((int) MODEL_MAX)
+
+/* Enum declaration for unit types.  */
+typedef enum unit_type {
+  UNIT_NONE, UNIT_IQ2000_U_EXEC, UNIT_MAX
+} UNIT_TYPE;
+
+#define MAX_UNITS (1)
+
+#endif /* IQ2000_ARCH_H */
--- a/sim/iq2000/config.in
+++ b/sim/iq2000/config.in
@ -0,0 +1,177 @@
+/* config.in.  Generated automatically from configure.in by autoheader.  */
+
+/* Define if using alloca.c.  */
+#undef C_ALLOCA
+
+/* Define to empty if the keyword does not work.  */
+#undef const
+
+/* Define to one of _getb67, GETB67, getb67 for Cray-2 and Cray-YMP systems.
+   This function is required for alloca.c support on those systems.  */
+#undef CRAY_STACKSEG_END
+
+/* Define if you have alloca, as a function or macro.  */
+#undef HAVE_ALLOCA
+
+/* Define if you have <alloca.h> and it should be used (not on Ultrix).  */
+#undef HAVE_ALLOCA_H
+
+/* Define if you have a working `mmap' system call.  */
+#undef HAVE_MMAP
+
+/* Define as __inline if that's what the C compiler calls it.  */
+#undef inline
+
+/* Define to `long' if <sys/types.h> doesn't define.  */
+#undef off_t
+
+/* Define if you need to in order for stat and other things to work.  */
+#undef _POSIX_SOURCE
+
+/* Define as the return type of signal handlers (int or void).  */
+#undef RETSIGTYPE
+
+/* Define to `unsigned' if <sys/types.h> doesn't define.  */
+#undef size_t
+
+/* If using the C implementation of alloca, define if you know the
+   direction of stack growth for your system; otherwise it will be
+   automatically deduced at run-time.
+ STACK_DIRECTION > 0 => grows toward higher addresses
+ STACK_DIRECTION < 0 => grows toward lower addresses
+ STACK_DIRECTION = 0 => direction of growth unknown
+ */
+#undef STACK_DIRECTION
+
+/* Define if you have the ANSI C header files.  */
+#undef STDC_HEADERS
+
+/* Define if your processor stores words with the most significant
+   byte first (like Motorola and SPARC, unlike Intel and VAX).  */
+#undef WORDS_BIGENDIAN
+
+/* Define to 1 if NLS is requested.  */
+#undef ENABLE_NLS
+
+/* Define as 1 if you have gettext and don't want to use GNU gettext.  */
+#undef HAVE_GETTEXT
+
+/* Define as 1 if you have the stpcpy function.  */
+#undef HAVE_STPCPY
+
+/* Define if your locale.h file contains LC_MESSAGES.  */
+#undef HAVE_LC_MESSAGES
+
+/* Define if you have the __argz_count function.  */
+#undef HAVE___ARGZ_COUNT
+
+/* Define if you have the __argz_next function.  */
+#undef HAVE___ARGZ_NEXT
+
+/* Define if you have the __argz_stringify function.  */
+#undef HAVE___ARGZ_STRINGIFY
+
+/* Define if you have the __setfpucw function.  */
+#undef HAVE___SETFPUCW
+
+/* Define if you have the dcgettext function.  */
+#undef HAVE_DCGETTEXT
+
+/* Define if you have the getcwd function.  */
+#undef HAVE_GETCWD
+
+/* Define if you have the getpagesize function.  */
+#undef HAVE_GETPAGESIZE
+
+/* Define if you have the getrusage function.  */
+#undef HAVE_GETRUSAGE
+
+/* Define if you have the munmap function.  */
+#undef HAVE_MUNMAP
+
+/* Define if you have the putenv function.  */
+#undef HAVE_PUTENV
+
+/* Define if you have the setenv function.  */
+#undef HAVE_SETENV
+
+/* Define if you have the setlocale function.  */
+#undef HAVE_SETLOCALE
+
+/* Define if you have the sigaction function.  */
+#undef HAVE_SIGACTION
+
+/* Define if you have the stpcpy function.  */
+#undef HAVE_STPCPY
+
+/* Define if you have the strcasecmp function.  */
+#undef HAVE_STRCASECMP
+
+/* Define if you have the strchr function.  */
+#undef HAVE_STRCHR
+
+/* Define if you have the time function.  */
+#undef HAVE_TIME
+
+/* Define if you have the <argz.h> header file.  */
+#undef HAVE_ARGZ_H
+
+/* Define if you have the <dlfcn.h> header file.  */
+#undef HAVE_DLFCN_H
+
+/* Define if you have the <errno.h> header file.  */
+#undef HAVE_ERRNO_H
+
+/* Define if you have the <fcntl.h> header file.  */
+#undef HAVE_FCNTL_H
+
+/* Define if you have the <fpu_control.h> header file.  */
+#undef HAVE_FPU_CONTROL_H
+
+/* Define if you have the <limits.h> header file.  */
+#undef HAVE_LIMITS_H
+
+/* Define if you have the <locale.h> header file.  */
+#undef HAVE_LOCALE_H
+
+/* Define if you have the <malloc.h> header file.  */
+#undef HAVE_MALLOC_H
+
+/* Define if you have the <nl_types.h> header file.  */
+#undef HAVE_NL_TYPES_H
+
+/* Define if you have the <stdlib.h> header file.  */
+#undef HAVE_STDLIB_H
+
+/* Define if you have the <string.h> header file.  */
+#undef HAVE_STRING_H
+
+/* Define if you have the <strings.h> header file.  */
+#undef HAVE_STRINGS_H
+
+/* Define if you have the <sys/param.h> header file.  */
+#undef HAVE_SYS_PARAM_H
+
+/* Define if you have the <sys/resource.h> header file.  */
+#undef HAVE_SYS_RESOURCE_H
+
+/* Define if you have the <sys/stat.h> header file.  */
+#undef HAVE_SYS_STAT_H
+
+/* Define if you have the <sys/time.h> header file.  */
+#undef HAVE_SYS_TIME_H
+
+/* Define if you have the <time.h> header file.  */
+#undef HAVE_TIME_H
+
+/* Define if you have the <unistd.h> header file.  */
+#undef HAVE_UNISTD_H
+
+/* Define if you have the <values.h> header file.  */
+#undef HAVE_VALUES_H
+
+/* Define if you have the nsl library (-lnsl).  */
+#undef HAVE_LIBNSL
+
+/* Define if you have the socket library (-lsocket).  */
+#undef HAVE_LIBSOCKET
--- a/sim/iq2000/configure
+++ b/sim/iq2000/configure
--- a/sim/iq2000/configure.ac
+++ b/sim/iq2000/configure.ac
@ -0,0 +1,21 @@
+dnl Process this file with autoconf to produce a configure script.
+AC_PREREQ(2.59)dnl
+AC_INIT(Makefile.in)
+AC_CONFIG_HEADER(config.h:config.in)
+
+sinclude(../common/aclocal.m4)
+
+# Bugs in autoconf 2.59 break the call to SIM_AC_COMMON, hack around
+# it by inlining the macro's contents.
+sinclude(../common/common.m4)
+
+SIM_AC_OPTION_ENDIAN(BIG_ENDIAN)
+SIM_AC_OPTION_ALIGNMENT(STRICT_ALIGNMENT)
+SIM_AC_OPTION_HOSTENDIAN
+SIM_AC_OPTION_SCACHE(16384)
+SIM_AC_OPTION_DEFAULT_MODEL(iq2000)
+SIM_AC_OPTION_ENVIRONMENT
+SIM_AC_OPTION_INLINE()
+SIM_AC_OPTION_CGEN_MAINT
+
+SIM_AC_OUTPUT
--- a/sim/iq2000/cpu.c
+++ b/sim/iq2000/cpu.c
@ -0,0 +1,69 @@
+/* Misc. support for CPU family iq2000bf.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
+
+This file is part of the GNU simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+
+#define WANT_CPU iq2000bf
+#define WANT_CPU_IQ2000BF
+
+#include "sim-main.h"
+#include "cgen-ops.h"
+
+/* Get the value of h-pc.  */
+
+USI
+iq2000bf_h_pc_get (SIM_CPU *current_cpu)
+{
+  return GET_H_PC ();
+}
+
+/* Set a value for h-pc.  */
+
+void
+iq2000bf_h_pc_set (SIM_CPU *current_cpu, USI newval)
+{
+  SET_H_PC (newval);
+}
+
+/* Get the value of h-gr.  */
+
+SI
+iq2000bf_h_gr_get (SIM_CPU *current_cpu, UINT regno)
+{
+  return GET_H_GR (regno);
+}
+
+/* Set a value for h-gr.  */
+
+void
+iq2000bf_h_gr_set (SIM_CPU *current_cpu, UINT regno, SI newval)
+{
+  SET_H_GR (regno, newval);
+}
+
+/* Record trace results for INSN.  */
+
+void
+iq2000bf_record_trace_results (SIM_CPU *current_cpu, CGEN_INSN *insn,
+			    int *indices, TRACE_RECORD *tr)
+{
+}
--- a/sim/iq2000/cpu.h
+++ b/sim/iq2000/cpu.h
@ -0,0 +1,531 @@
+/* CPU family header for iq2000bf.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
+
+This file is part of the GNU simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+
+#ifndef CPU_IQ2000BF_H
+#define CPU_IQ2000BF_H
+
+/* Maximum number of instructions that are fetched at a time.
+   This is for LIW type instructions sets (e.g. m32r).  */
+#define MAX_LIW_INSNS 1
+
+/* Maximum number of instructions that can be executed in parallel.  */
+#define MAX_PARALLEL_INSNS 1
+
+/* CPU state information.  */
+typedef struct {
+  /* Hardware elements.  */
+  struct {
+  /* program counter */
+  USI h_pc;
+#define GET_H_PC() get_h_pc (current_cpu)
+#define SET_H_PC(x) \
+do { \
+set_h_pc (current_cpu, (x));\
+;} while (0)
+  /* General purpose registers */
+  SI h_gr[32];
+#define GET_H_GR(index) (((index) == (0))) ? (0) : (CPU (h_gr[index]))
+#define SET_H_GR(index, x) \
+do { \
+if ((((index)) == (0))) {\
+((void) 0); /*nop*/\
+}\
+ else {\
+CPU (h_gr[(index)]) = (x);\
+}\
+;} while (0)
+  } hardware;
+#define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware)
+} IQ2000BF_CPU_DATA;
+
+/* Cover fns for register access.  */
+USI iq2000bf_h_pc_get (SIM_CPU *);
+void iq2000bf_h_pc_set (SIM_CPU *, USI);
+SI iq2000bf_h_gr_get (SIM_CPU *, UINT);
+void iq2000bf_h_gr_set (SIM_CPU *, UINT, SI);
+
+/* These must be hand-written.  */
+extern CPUREG_FETCH_FN iq2000bf_fetch_register;
+extern CPUREG_STORE_FN iq2000bf_store_register;
+
+typedef struct {
+  int empty;
+} MODEL_IQ2000_DATA;
+
+/* Instruction argument buffer.  */
+
+union sem_fields {
+  struct { /* no operands */
+    int empty;
+  } fmt_empty;
+  struct { /*  */
+    IADDR i_jmptarg;
+  } sfmt_j;
+  struct { /*  */
+    IADDR i_offset;
+    UINT f_rs;
+    UINT f_rt;
+  } sfmt_bbi;
+  struct { /*  */
+    UINT f_imm;
+    UINT f_rs;
+    UINT f_rt;
+  } sfmt_addi;
+  struct { /*  */
+    UINT f_mask;
+    UINT f_rd;
+    UINT f_rs;
+    UINT f_rt;
+  } sfmt_mrgb;
+  struct { /*  */
+    UINT f_maskl;
+    UINT f_rd;
+    UINT f_rs;
+    UINT f_rt;
+    UINT f_shamt;
+  } sfmt_ram;
+#if WITH_SCACHE_PBB
+  /* Writeback handler.  */
+  struct {
+    /* Pointer to argbuf entry for insn whose results need writing back.  */
+    const struct argbuf *abuf;
+  } write;
+  /* x-before handler */
+  struct {
+    /*const SCACHE *insns[MAX_PARALLEL_INSNS];*/
+    int first_p;
+  } before;
+  /* x-after handler */
+  struct {
+    int empty;
+  } after;
+  /* This entry is used to terminate each pbb.  */
+  struct {
+    /* Number of insns in pbb.  */
+    int insn_count;
+    /* Next pbb to execute.  */
+    SCACHE *next;
+    SCACHE *branch_target;
+  } chain;
+#endif
+};
+
+/* The ARGBUF struct.  */
+struct argbuf {
+  /* These are the baseclass definitions.  */
+  IADDR addr;
+  const IDESC *idesc;
+  char trace_p;
+  char profile_p;
+  /* ??? Temporary hack for skip insns.  */
+  char skip_count;
+  char unused;
+  /* cpu specific data follows */
+  union sem semantic;
+  int written;
+  union sem_fields fields;
+};
+
+/* A cached insn.
+
+   ??? SCACHE used to contain more than just argbuf.  We could delete the
+   type entirely and always just use ARGBUF, but for future concerns and as
+   a level of abstraction it is left in.  */
+
+struct scache {
+  struct argbuf argbuf;
+};
+
+/* Macros to simplify extraction, reading and semantic code.
+   These define and assign the local vars that contain the insn's fields.  */
+
+#define EXTRACT_IFMT_EMPTY_VARS \
+  unsigned int length;
+#define EXTRACT_IFMT_EMPTY_CODE \
+  length = 0; \
+
+#define EXTRACT_IFMT_ADD_VARS \
+  UINT f_opcode; \
+  UINT f_rs; \
+  UINT f_rt; \
+  UINT f_rd; \
+  UINT f_shamt; \
+  UINT f_func; \
+  unsigned int length;
+#define EXTRACT_IFMT_ADD_CODE \
+  length = 4; \
+  f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
+  f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
+  f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
+  f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \
+  f_shamt = EXTRACT_LSB0_UINT (insn, 32, 10, 5); \
+  f_func = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
+
+#define EXTRACT_IFMT_ADDI_VARS \
+  UINT f_opcode; \
+  UINT f_rs; \
+  UINT f_rt; \
+  UINT f_imm; \
+  unsigned int length;
+#define EXTRACT_IFMT_ADDI_CODE \
+  length = 4; \
+  f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
+  f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
+  f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
+  f_imm = EXTRACT_LSB0_UINT (insn, 32, 15, 16); \
+
+#define EXTRACT_IFMT_RAM_VARS \
+  UINT f_opcode; \
+  UINT f_rs; \
+  UINT f_rt; \
+  UINT f_rd; \
+  UINT f_shamt; \
+  UINT f_5; \
+  UINT f_maskl; \
+  unsigned int length;
+#define EXTRACT_IFMT_RAM_CODE \
+  length = 4; \
+  f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
+  f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
+  f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
+  f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \
+  f_shamt = EXTRACT_LSB0_UINT (insn, 32, 10, 5); \
+  f_5 = EXTRACT_LSB0_UINT (insn, 32, 5, 1); \
+  f_maskl = EXTRACT_LSB0_UINT (insn, 32, 4, 5); \
+
+#define EXTRACT_IFMT_SLL_VARS \
+  UINT f_opcode; \
+  UINT f_rs; \
+  UINT f_rt; \
+  UINT f_rd; \
+  UINT f_shamt; \
+  UINT f_func; \
+  unsigned int length;
+#define EXTRACT_IFMT_SLL_CODE \
+  length = 4; \
+  f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
+  f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
+  f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
+  f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \
+  f_shamt = EXTRACT_LSB0_UINT (insn, 32, 10, 5); \
+  f_func = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
+
+#define EXTRACT_IFMT_SLMV_VARS \
+  UINT f_opcode; \
+  UINT f_rs; \
+  UINT f_rt; \
+  UINT f_rd; \
+  UINT f_shamt; \
+  UINT f_func; \
+  unsigned int length;
+#define EXTRACT_IFMT_SLMV_CODE \
+  length = 4; \
+  f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
+  f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
+  f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
+  f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \
+  f_shamt = EXTRACT_LSB0_UINT (insn, 32, 10, 5); \
+  f_func = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
+
+#define EXTRACT_IFMT_SLTI_VARS \
+  UINT f_opcode; \
+  UINT f_rs; \
+  UINT f_rt; \
+  UINT f_imm; \
+  unsigned int length;
+#define EXTRACT_IFMT_SLTI_CODE \
+  length = 4; \
+  f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
+  f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
+  f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
+  f_imm = EXTRACT_LSB0_UINT (insn, 32, 15, 16); \
+
+#define EXTRACT_IFMT_BBI_VARS \
+  UINT f_opcode; \
+  UINT f_rs; \
+  UINT f_rt; \
+  SI f_offset; \
+  unsigned int length;
+#define EXTRACT_IFMT_BBI_CODE \
+  length = 4; \
+  f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
+  f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
+  f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
+  f_offset = ((((EXTRACT_LSB0_INT (insn, 32, 15, 16)) << (2))) + (((pc) + (4)))); \
+
+#define EXTRACT_IFMT_BBV_VARS \
+  UINT f_opcode; \
+  UINT f_rs; \
+  UINT f_rt; \
+  SI f_offset; \
+  unsigned int length;
+#define EXTRACT_IFMT_BBV_CODE \
+  length = 4; \
+  f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
+  f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
+  f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
+  f_offset = ((((EXTRACT_LSB0_INT (insn, 32, 15, 16)) << (2))) + (((pc) + (4)))); \
+
+#define EXTRACT_IFMT_BGEZ_VARS \
+  UINT f_opcode; \
+  UINT f_rs; \
+  UINT f_rt; \
+  SI f_offset; \
+  unsigned int length;
+#define EXTRACT_IFMT_BGEZ_CODE \
+  length = 4; \
+  f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
+  f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
+  f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
+  f_offset = ((((EXTRACT_LSB0_INT (insn, 32, 15, 16)) << (2))) + (((pc) + (4)))); \
+
+#define EXTRACT_IFMT_JALR_VARS \
+  UINT f_opcode; \
+  UINT f_rs; \
+  UINT f_rt; \
+  UINT f_rd; \
+  UINT f_shamt; \
+  UINT f_func; \
+  unsigned int length;
+#define EXTRACT_IFMT_JALR_CODE \
+  length = 4; \
+  f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
+  f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
+  f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
+  f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \
+  f_shamt = EXTRACT_LSB0_UINT (insn, 32, 10, 5); \
+  f_func = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
+
+#define EXTRACT_IFMT_JR_VARS \
+  UINT f_opcode; \
+  UINT f_rs; \
+  UINT f_rt; \
+  UINT f_rd; \
+  UINT f_shamt; \
+  UINT f_func; \
+  unsigned int length;
+#define EXTRACT_IFMT_JR_CODE \
+  length = 4; \
+  f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
+  f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
+  f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
+  f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \
+  f_shamt = EXTRACT_LSB0_UINT (insn, 32, 10, 5); \
+  f_func = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
+
+#define EXTRACT_IFMT_LB_VARS \
+  UINT f_opcode; \
+  UINT f_rs; \
+  UINT f_rt; \
+  UINT f_imm; \
+  unsigned int length;
+#define EXTRACT_IFMT_LB_CODE \
+  length = 4; \
+  f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
+  f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
+  f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
+  f_imm = EXTRACT_LSB0_UINT (insn, 32, 15, 16); \
+
+#define EXTRACT_IFMT_LUI_VARS \
+  UINT f_opcode; \
+  UINT f_rs; \
+  UINT f_rt; \
+  UINT f_imm; \
+  unsigned int length;
+#define EXTRACT_IFMT_LUI_CODE \
+  length = 4; \
+  f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
+  f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
+  f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
+  f_imm = EXTRACT_LSB0_UINT (insn, 32, 15, 16); \
+
+#define EXTRACT_IFMT_BREAK_VARS \
+  UINT f_opcode; \
+  UINT f_rs; \
+  UINT f_rt; \
+  UINT f_rd; \
+  UINT f_shamt; \
+  UINT f_func; \
+  unsigned int length;
+#define EXTRACT_IFMT_BREAK_CODE \
+  length = 4; \
+  f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
+  f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
+  f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
+  f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \
+  f_shamt = EXTRACT_LSB0_UINT (insn, 32, 10, 5); \
+  f_func = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
+
+#define EXTRACT_IFMT_SYSCALL_VARS \
+  UINT f_opcode; \
+  UINT f_excode; \
+  UINT f_func; \
+  unsigned int length;
+#define EXTRACT_IFMT_SYSCALL_CODE \
+  length = 4; \
+  f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
+  f_excode = EXTRACT_LSB0_UINT (insn, 32, 25, 20); \
+  f_func = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
+
+#define EXTRACT_IFMT_ANDOUI_VARS \
+  UINT f_opcode; \
+  UINT f_rs; \
+  UINT f_rt; \
+  UINT f_imm; \
+  unsigned int length;
+#define EXTRACT_IFMT_ANDOUI_CODE \
+  length = 4; \
+  f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
+  f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
+  f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
+  f_imm = EXTRACT_LSB0_UINT (insn, 32, 15, 16); \
+
+#define EXTRACT_IFMT_MRGB_VARS \
+  UINT f_opcode; \
+  UINT f_rs; \
+  UINT f_rt; \
+  UINT f_rd; \
+  UINT f_10; \
+  UINT f_mask; \
+  UINT f_func; \
+  unsigned int length;
+#define EXTRACT_IFMT_MRGB_CODE \
+  length = 4; \
+  f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
+  f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
+  f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
+  f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \
+  f_10 = EXTRACT_LSB0_UINT (insn, 32, 10, 1); \
+  f_mask = EXTRACT_LSB0_UINT (insn, 32, 9, 4); \
+  f_func = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
+
+#define EXTRACT_IFMT_BC0F_VARS \
+  UINT f_opcode; \
+  UINT f_rs; \
+  UINT f_rt; \
+  SI f_offset; \
+  unsigned int length;
+#define EXTRACT_IFMT_BC0F_CODE \
+  length = 4; \
+  f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
+  f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
+  f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
+  f_offset = ((((EXTRACT_LSB0_INT (insn, 32, 15, 16)) << (2))) + (((pc) + (4)))); \
+
+#define EXTRACT_IFMT_CFC0_VARS \
+  UINT f_opcode; \
+  UINT f_rs; \
+  UINT f_rt; \
+  UINT f_rd; \
+  UINT f_10_11; \
+  unsigned int length;
+#define EXTRACT_IFMT_CFC0_CODE \
+  length = 4; \
+  f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
+  f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
+  f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
+  f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \
+  f_10_11 = EXTRACT_LSB0_UINT (insn, 32, 10, 11); \
+
+#define EXTRACT_IFMT_CHKHDR_VARS \
+  UINT f_opcode; \
+  UINT f_rs; \
+  UINT f_rt; \
+  UINT f_rd; \
+  UINT f_shamt; \
+  UINT f_func; \
+  unsigned int length;
+#define EXTRACT_IFMT_CHKHDR_CODE \
+  length = 4; \
+  f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
+  f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
+  f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
+  f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \
+  f_shamt = EXTRACT_LSB0_UINT (insn, 32, 10, 5); \
+  f_func = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
+
+#define EXTRACT_IFMT_LULCK_VARS \
+  UINT f_opcode; \
+  UINT f_rs; \
+  UINT f_rt; \
+  UINT f_rd; \
+  UINT f_shamt; \
+  UINT f_func; \
+  unsigned int length;
+#define EXTRACT_IFMT_LULCK_CODE \
+  length = 4; \
+  f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
+  f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
+  f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
+  f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \
+  f_shamt = EXTRACT_LSB0_UINT (insn, 32, 10, 5); \
+  f_func = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
+
+#define EXTRACT_IFMT_PKRLR1_VARS \
+  UINT f_opcode; \
+  UINT f_rs; \
+  UINT f_rt; \
+  UINT f_count; \
+  UINT f_index; \
+  unsigned int length;
+#define EXTRACT_IFMT_PKRLR1_CODE \
+  length = 4; \
+  f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
+  f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
+  f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
+  f_count = EXTRACT_LSB0_UINT (insn, 32, 15, 7); \
+  f_index = EXTRACT_LSB0_UINT (insn, 32, 8, 9); \
+
+#define EXTRACT_IFMT_RFE_VARS \
+  UINT f_opcode; \
+  UINT f_25; \
+  UINT f_24_19; \
+  UINT f_func; \
+  unsigned int length;
+#define EXTRACT_IFMT_RFE_CODE \
+  length = 4; \
+  f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
+  f_25 = EXTRACT_LSB0_UINT (insn, 32, 25, 1); \
+  f_24_19 = EXTRACT_LSB0_UINT (insn, 32, 24, 19); \
+  f_func = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
+
+#define EXTRACT_IFMT_J_VARS \
+  UINT f_opcode; \
+  UINT f_rsrvd; \
+  USI f_jtarg; \
+  unsigned int length;
+#define EXTRACT_IFMT_J_CODE \
+  length = 4; \
+  f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
+  f_rsrvd = EXTRACT_LSB0_UINT (insn, 32, 25, 10); \
+  f_jtarg = ((((pc) & (0xf0000000))) | (((EXTRACT_LSB0_UINT (insn, 32, 15, 16)) << (2)))); \
+
+/* Collection of various things for the trace handler to use.  */
+
+typedef struct trace_record {
+  IADDR pc;
+  /* FIXME:wip */
+} TRACE_RECORD;
+
+#endif /* CPU_IQ2000BF_H */
--- a/sim/iq2000/cpuall.h
+++ b/sim/iq2000/cpuall.h
@ -0,0 +1,73 @@
+/* Simulator CPU header for iq2000.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
+
+This file is part of the GNU simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+
+#ifndef IQ2000_CPUALL_H
+#define IQ2000_CPUALL_H
+
+/* Include files for each cpu family.  */
+
+#ifdef WANT_CPU_IQ2000BF
+#include "eng.h"
+#include "cgen-engine.h"
+#include "cpu.h"
+#include "decode.h"
+#endif
+
+#ifdef WANT_CPU_IQ10BF
+#include "eng.h"
+#include "cgen-engine.h"
+#include "cpu.h"
+#include "decode.h"
+#endif
+
+extern const MACH iq2000_mach;
+
+#ifndef WANT_CPU
+/* The ARGBUF struct.  */
+struct argbuf {
+  /* These are the baseclass definitions.  */
+  IADDR addr;
+  const IDESC *idesc;
+  char trace_p;
+  char profile_p;
+  /* ??? Temporary hack for skip insns.  */
+  char skip_count;
+  char unused;
+  /* cpu specific data follows */
+};
+#endif
+
+#ifndef WANT_CPU
+/* A cached insn.
+
+   ??? SCACHE used to contain more than just argbuf.  We could delete the
+   type entirely and always just use ARGBUF, but for future concerns and as
+   a level of abstraction it is left in.  */
+
+struct scache {
+  struct argbuf argbuf;
+};
+#endif
+
+#endif /* IQ2000_CPUALL_H */
--- a/sim/iq2000/decode.c
+++ b/sim/iq2000/decode.c
--- a/sim/iq2000/decode.h
+++ b/sim/iq2000/decode.h
@ -0,0 +1,98 @@
+/* Decode header for iq2000bf.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
+
+This file is part of the GNU simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+
+#ifndef IQ2000BF_DECODE_H
+#define IQ2000BF_DECODE_H
+
+extern const IDESC *iq2000bf_decode (SIM_CPU *, IADDR,
+                                  CGEN_INSN_INT, CGEN_INSN_INT,
+                                  ARGBUF *);
+extern void iq2000bf_init_idesc_table (SIM_CPU *);
+extern void iq2000bf_sem_init_idesc_table (SIM_CPU *);
+extern void iq2000bf_semf_init_idesc_table (SIM_CPU *);
+
+/* Enum declaration for instructions in cpu family iq2000bf.  */
+typedef enum iq2000bf_insn_type {
+  IQ2000BF_INSN_X_INVALID, IQ2000BF_INSN_X_AFTER, IQ2000BF_INSN_X_BEFORE, IQ2000BF_INSN_X_CTI_CHAIN
+ , IQ2000BF_INSN_X_CHAIN, IQ2000BF_INSN_X_BEGIN, IQ2000BF_INSN_ADD, IQ2000BF_INSN_ADDI
+ , IQ2000BF_INSN_ADDIU, IQ2000BF_INSN_ADDU, IQ2000BF_INSN_ADO16, IQ2000BF_INSN_AND
+ , IQ2000BF_INSN_ANDI, IQ2000BF_INSN_ANDOI, IQ2000BF_INSN_NOR, IQ2000BF_INSN_OR
+ , IQ2000BF_INSN_ORI, IQ2000BF_INSN_RAM, IQ2000BF_INSN_SLL, IQ2000BF_INSN_SLLV
+ , IQ2000BF_INSN_SLMV, IQ2000BF_INSN_SLT, IQ2000BF_INSN_SLTI, IQ2000BF_INSN_SLTIU
+ , IQ2000BF_INSN_SLTU, IQ2000BF_INSN_SRA, IQ2000BF_INSN_SRAV, IQ2000BF_INSN_SRL
+ , IQ2000BF_INSN_SRLV, IQ2000BF_INSN_SRMV, IQ2000BF_INSN_SUB, IQ2000BF_INSN_SUBU
+ , IQ2000BF_INSN_XOR, IQ2000BF_INSN_XORI, IQ2000BF_INSN_BBI, IQ2000BF_INSN_BBIN
+ , IQ2000BF_INSN_BBV, IQ2000BF_INSN_BBVN, IQ2000BF_INSN_BEQ, IQ2000BF_INSN_BEQL
+ , IQ2000BF_INSN_BGEZ, IQ2000BF_INSN_BGEZAL, IQ2000BF_INSN_BGEZALL, IQ2000BF_INSN_BGEZL
+ , IQ2000BF_INSN_BLTZ, IQ2000BF_INSN_BLTZL, IQ2000BF_INSN_BLTZAL, IQ2000BF_INSN_BLTZALL
+ , IQ2000BF_INSN_BMB0, IQ2000BF_INSN_BMB1, IQ2000BF_INSN_BMB2, IQ2000BF_INSN_BMB3
+ , IQ2000BF_INSN_BNE, IQ2000BF_INSN_BNEL, IQ2000BF_INSN_JALR, IQ2000BF_INSN_JR
+ , IQ2000BF_INSN_LB, IQ2000BF_INSN_LBU, IQ2000BF_INSN_LH, IQ2000BF_INSN_LHU
+ , IQ2000BF_INSN_LUI, IQ2000BF_INSN_LW, IQ2000BF_INSN_SB, IQ2000BF_INSN_SH
+ , IQ2000BF_INSN_SW, IQ2000BF_INSN_BREAK, IQ2000BF_INSN_SYSCALL, IQ2000BF_INSN_ANDOUI
+ , IQ2000BF_INSN_ORUI, IQ2000BF_INSN_BGTZ, IQ2000BF_INSN_BGTZL, IQ2000BF_INSN_BLEZ
+ , IQ2000BF_INSN_BLEZL, IQ2000BF_INSN_MRGB, IQ2000BF_INSN_BCTXT, IQ2000BF_INSN_BC0F
+ , IQ2000BF_INSN_BC0FL, IQ2000BF_INSN_BC3F, IQ2000BF_INSN_BC3FL, IQ2000BF_INSN_BC0T
+ , IQ2000BF_INSN_BC0TL, IQ2000BF_INSN_BC3T, IQ2000BF_INSN_BC3TL, IQ2000BF_INSN_CFC0
+ , IQ2000BF_INSN_CFC1, IQ2000BF_INSN_CFC2, IQ2000BF_INSN_CFC3, IQ2000BF_INSN_CHKHDR
+ , IQ2000BF_INSN_CTC0, IQ2000BF_INSN_CTC1, IQ2000BF_INSN_CTC2, IQ2000BF_INSN_CTC3
+ , IQ2000BF_INSN_JCR, IQ2000BF_INSN_LUC32, IQ2000BF_INSN_LUC32L, IQ2000BF_INSN_LUC64
+ , IQ2000BF_INSN_LUC64L, IQ2000BF_INSN_LUK, IQ2000BF_INSN_LULCK, IQ2000BF_INSN_LUM32
+ , IQ2000BF_INSN_LUM32L, IQ2000BF_INSN_LUM64, IQ2000BF_INSN_LUM64L, IQ2000BF_INSN_LUR
+ , IQ2000BF_INSN_LURL, IQ2000BF_INSN_LUULCK, IQ2000BF_INSN_MFC0, IQ2000BF_INSN_MFC1
+ , IQ2000BF_INSN_MFC2, IQ2000BF_INSN_MFC3, IQ2000BF_INSN_MTC0, IQ2000BF_INSN_MTC1
+ , IQ2000BF_INSN_MTC2, IQ2000BF_INSN_MTC3, IQ2000BF_INSN_PKRL, IQ2000BF_INSN_PKRLR1
+ , IQ2000BF_INSN_PKRLR30, IQ2000BF_INSN_RB, IQ2000BF_INSN_RBR1, IQ2000BF_INSN_RBR30
+ , IQ2000BF_INSN_RFE, IQ2000BF_INSN_RX, IQ2000BF_INSN_RXR1, IQ2000BF_INSN_RXR30
+ , IQ2000BF_INSN_SLEEP, IQ2000BF_INSN_SRRD, IQ2000BF_INSN_SRRDL, IQ2000BF_INSN_SRULCK
+ , IQ2000BF_INSN_SRWR, IQ2000BF_INSN_SRWRU, IQ2000BF_INSN_TRAPQFL, IQ2000BF_INSN_TRAPQNE
+ , IQ2000BF_INSN_TRAPREL, IQ2000BF_INSN_WB, IQ2000BF_INSN_WBU, IQ2000BF_INSN_WBR1
+ , IQ2000BF_INSN_WBR1U, IQ2000BF_INSN_WBR30, IQ2000BF_INSN_WBR30U, IQ2000BF_INSN_WX
+ , IQ2000BF_INSN_WXU, IQ2000BF_INSN_WXR1, IQ2000BF_INSN_WXR1U, IQ2000BF_INSN_WXR30
+ , IQ2000BF_INSN_WXR30U, IQ2000BF_INSN_LDW, IQ2000BF_INSN_SDW, IQ2000BF_INSN_J
+ , IQ2000BF_INSN_JAL, IQ2000BF_INSN_BMB, IQ2000BF_INSN_MAX
+} IQ2000BF_INSN_TYPE;
+
+/* Enum declaration for semantic formats in cpu family iq2000bf.  */
+typedef enum iq2000bf_sfmt_type {
+  IQ2000BF_SFMT_EMPTY, IQ2000BF_SFMT_ADD, IQ2000BF_SFMT_ADDI, IQ2000BF_SFMT_ADO16
+ , IQ2000BF_SFMT_RAM, IQ2000BF_SFMT_SLL, IQ2000BF_SFMT_SLMV, IQ2000BF_SFMT_SLT
+ , IQ2000BF_SFMT_SLTI, IQ2000BF_SFMT_BBI, IQ2000BF_SFMT_BBV, IQ2000BF_SFMT_BGEZ
+ , IQ2000BF_SFMT_BGEZAL, IQ2000BF_SFMT_JALR, IQ2000BF_SFMT_JR, IQ2000BF_SFMT_LB
+ , IQ2000BF_SFMT_LH, IQ2000BF_SFMT_LUI, IQ2000BF_SFMT_LW, IQ2000BF_SFMT_SB
+ , IQ2000BF_SFMT_SH, IQ2000BF_SFMT_SW, IQ2000BF_SFMT_BREAK, IQ2000BF_SFMT_SYSCALL
+ , IQ2000BF_SFMT_ANDOUI, IQ2000BF_SFMT_MRGB, IQ2000BF_SFMT_BCTXT, IQ2000BF_SFMT_LDW
+ , IQ2000BF_SFMT_SDW, IQ2000BF_SFMT_J, IQ2000BF_SFMT_JAL
+} IQ2000BF_SFMT_TYPE;
+
+/* Function unit handlers (user written).  */
+
+extern int iq2000bf_model_iq2000_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
+
+/* Profiling before/after handlers (user written) */
+
+extern void iq2000bf_model_insn_before (SIM_CPU *, int /*first_p*/);
+extern void iq2000bf_model_insn_after (SIM_CPU *, int /*last_p*/, int /*cycles*/);
+
+#endif /* IQ2000BF_DECODE_H */
--- a/sim/iq2000/iq2000-sim.h
+++ b/sim/iq2000/iq2000-sim.h
@ -0,0 +1,35 @@
+/* collection of junk waiting time to sort out
+   Copyright (C) 1998, 1999 Free Software Foundation, Inc.
+   Contributed by Cygnus Solutions.
+
+This file is part of the GNU Simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+#ifndef IQ2000_SIM_H
+#define IQ2000_SIM_H
+
+#define GETTWI GETTSI
+#define SETTWI SETTSI
+
+
+/* Hardware/device support.
+/* sim_core_attach device argument.  */
+extern device iq2000_devices;
+
+/* FIXME: Temporary, until device support ready.  */
+struct _device { int foo; };
+
+#endif /* IQ2000_SIM_H */
--- a/sim/iq2000/iq2000.c
+++ b/sim/iq2000/iq2000.c
@ -0,0 +1,267 @@
+/* IQ2000 simulator support code
+   Copyright (C) 2000, 2004 Free Software Foundation, Inc.
+   Contributed by Cygnus Support.
+
+   This file is part of the GNU simulators.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2, or (at your option)
+   any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License along
+   with this program; if not, write to the Free Software Foundation, Inc.,
+   59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+#define WANT_CPU
+#define WANT_CPU_IQ2000BF
+
+#include "sim-main.h"
+#include "cgen-mem.h"
+#include "cgen-ops.h"
+
+enum
+{
+  GPR0_REGNUM = 0,
+  NR_GPR = 32,
+  PC_REGNUM = 32
+};
+
+enum libgloss_syscall
+{
+  SYS_exit = 1,
+  SYS_open = 2, 
+  SYS_close = 3, 
+  SYS_read = 4,
+  SYS_write = 5, 
+  SYS_lseek = 6, 
+  SYS_unlink = 7,
+  SYS_getpid = 8,
+  SYS_kill = 9,
+  SYS_fstat = 10, 
+  SYS_argvlen = 12, 
+  SYS_argv = 13,
+  SYS_chdir = 14, 
+  SYS_stat = 15, 
+  SYS_chmod = 16, 
+  SYS_utime = 17,
+  SYS_time = 18,
+  SYS_gettimeofday = 19,
+  SYS_times = 20
+};
+
+/* Read a null terminated string from memory, return in a buffer */
+static char *
+fetch_str (current_cpu, pc, addr)
+     SIM_CPU *current_cpu;
+     PCADDR pc;
+     DI addr;
+{
+  char *buf;
+  int nr = 0;
+  while (sim_core_read_1 (current_cpu,
+                          pc, read_map, CPU2DATA(addr + nr)) != 0)
+    nr++;
+  buf = NZALLOC (char, nr + 1);
+  sim_read (CPU_STATE (current_cpu), CPU2DATA(addr), buf, nr);
+  return buf;
+}
+
+void
+do_syscall (SIM_CPU *current_cpu, PCADDR pc)
+{
+#if 0
+  int syscall = H2T_4 (iq2000bf_h_gr_get (current_cpu, 11));
+#endif
+  int syscall_function = iq2000bf_h_gr_get (current_cpu, 4);
+  int i;
+  char *buf;
+  int PARM1 = iq2000bf_h_gr_get (current_cpu, 5);
+  int PARM2 = iq2000bf_h_gr_get (current_cpu, 6);
+  int PARM3 = iq2000bf_h_gr_get (current_cpu, 7);
+  const int ret_reg = 2;
+	
+  switch (syscall_function)
+    {
+    case 0:
+      switch (H2T_4 (iq2000bf_h_gr_get (current_cpu, 11)))
+	{
+	case 0:
+	  /* Pass.  */
+	  puts ("pass");
+	  exit (0);
+	case 1:
+	  /* Fail.  */
+	  puts ("fail");
+	  exit (1);
+	}
+
+    case SYS_write:
+      buf = zalloc (PARM3);
+      sim_read (CPU_STATE (current_cpu), CPU2DATA(PARM2), buf, PARM3);
+      SET_H_GR (ret_reg,
+		sim_io_write (CPU_STATE (current_cpu),
+			      PARM1, buf, PARM3));
+      zfree (buf);
+      break;
+
+    case SYS_lseek:
+      SET_H_GR (ret_reg,
+		sim_io_lseek (CPU_STATE (current_cpu),
+			      PARM1, PARM2, PARM3));
+      break;
+	    
+    case SYS_exit:
+      sim_engine_halt (CPU_STATE (current_cpu), current_cpu,
+		       NULL, pc, sim_exited, PARM1);
+      break;
+
+    case SYS_read:
+      buf = zalloc (PARM3);
+      SET_H_GR (ret_reg,
+		sim_io_read (CPU_STATE (current_cpu),
+			     PARM1, buf, PARM3));
+      sim_write (CPU_STATE (current_cpu), CPU2DATA(PARM2), buf, PARM3);
+      zfree (buf);
+      break;
+	    
+    case SYS_open:
+      buf = fetch_str (current_cpu, pc, PARM1);
+      SET_H_GR (ret_reg,
+		sim_io_open (CPU_STATE (current_cpu),
+			     buf, PARM2));
+      zfree (buf);
+      break;
+
+    case SYS_close:
+      SET_H_GR (ret_reg,
+		sim_io_close (CPU_STATE (current_cpu), PARM1));
+      break;
+
+    case SYS_time:
+      SET_H_GR (ret_reg, time (0));
+      break;
+
+    default:
+      SET_H_GR (ret_reg, -1);
+    }
+}
+
+void 
+do_break (SIM_CPU *current_cpu, PCADDR pc)
+{
+  SIM_DESC sd = CPU_STATE (current_cpu);
+  sim_engine_halt (sd, current_cpu, NULL, pc, sim_stopped, SIM_SIGTRAP);
+}
+
+/* The semantic code invokes this for invalid (unrecognized) instructions.  */
+
+SEM_PC
+sim_engine_invalid_insn (SIM_CPU *current_cpu, IADDR cia, SEM_PC vpc)
+{
+  SIM_DESC sd = CPU_STATE (current_cpu);
+  sim_engine_halt (sd, current_cpu, NULL, cia, sim_stopped, SIM_SIGILL);
+
+  return vpc;
+}
+
+
+/* Process an address exception.  */
+
+void
+iq2000_core_signal (SIM_DESC sd, SIM_CPU *current_cpu, sim_cia cia,
+                  unsigned int map, int nr_bytes, address_word addr,
+                  transfer_type transfer, sim_core_signals sig)
+{
+  sim_core_signal (sd, current_cpu, cia, map, nr_bytes, addr,
+		   transfer, sig);
+}
+
+
+/* Initialize cycle counting for an insn.
+   FIRST_P is non-zero if this is the first insn in a set of parallel
+   insns.  */
+
+void
+iq2000bf_model_insn_before (SIM_CPU *cpu, int first_p)
+{
+  /* Do nothing.  */
+}
+
+
+/* Record the cycles computed for an insn.
+   LAST_P is non-zero if this is the last insn in a set of parallel insns,
+   and we update the total cycle count.
+   CYCLES is the cycle count of the insn.  */
+
+void
+iq2000bf_model_insn_after(SIM_CPU *cpu, int last_p, int cycles)
+{
+  /* Do nothing.  */
+}
+
+
+int
+iq2000bf_model_iq2000_u_exec (SIM_CPU *cpu, const IDESC *idesc,
+			    int unit_num, int referenced)
+{
+  return idesc->timing->units[unit_num].done;
+}
+
+PCADDR
+get_h_pc (SIM_CPU *cpu)
+{
+  return CPU_CGEN_HW(cpu)->h_pc;
+}
+
+void
+set_h_pc (SIM_CPU *cpu, PCADDR addr)
+{
+  CPU_CGEN_HW(cpu)->h_pc = addr | IQ2000_INSN_MASK;
+}
+
+int
+iq2000bf_fetch_register (SIM_CPU *cpu, int nr, unsigned char *buf, int len)
+{
+  if (nr >= GPR0_REGNUM
+      && nr < (GPR0_REGNUM + NR_GPR)
+      && len == 4)
+    {
+      *((unsigned32*)buf) =
+	H2T_4 (iq2000bf_h_gr_get (cpu, nr - GPR0_REGNUM));
+      return 4;
+    }
+  else if (nr == PC_REGNUM
+	   && len == 4)
+    {
+      *((unsigned32*)buf) = H2T_4 (get_h_pc (cpu));
+      return 4;
+    }
+  else
+    return 0;
+}
+
+int
+iq2000bf_store_register (SIM_CPU *cpu, int nr, unsigned char *buf, int len)
+{
+  if (nr >= GPR0_REGNUM
+      && nr < (GPR0_REGNUM + NR_GPR)
+      && len == 4)
+    {
+      iq2000bf_h_gr_set (cpu, nr - GPR0_REGNUM, T2H_4 (*((unsigned32*)buf)));
+      return 4;
+    }
+  else if (nr == PC_REGNUM
+	   && len == 4)
+    {
+      set_h_pc (cpu, T2H_4 (*((unsigned32*)buf)));
+      return 4;
+    }
+  else
+    return 0;
+}
--- a/sim/iq2000/mloop.in
+++ b/sim/iq2000/mloop.in
@ -0,0 +1,244 @@
+# Simulator main loop for IQ2000. -*- C -*-
+# Copyright (C) 1998, 1999 Free Software Foundation, Inc.
+# Contributed by Cygnus Solutions.
+#
+# This file is part of the GNU Simulators.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2, or (at your option)
+# any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License along
+# with this program; if not, write to the Free Software Foundation, Inc.,
+# 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+# Syntax:
+# /bin/sh mainloop.in command
+#
+# Command is one of:
+#
+# init
+# support
+# extract-{simple,scache,pbb}
+# {full,fast}-exec-{simple,scache,pbb}
+#
+# A target need only provide a "full" version of one of simple,scache,pbb.
+# If the target wants it can also provide a fast version of same.
+# It can't provide more than this, however for illustration's sake the IQ2000
+# port provides examples of all.
+
+# ??? After a few more ports are done, revisit.
+# Will eventually need to machine generate a lot of this.
+
+case "x$1" in
+
+xsupport)
+
+cat <<EOF
+
+static INLINE const IDESC *
+extract (SIM_CPU *current_cpu, PCADDR pc, CGEN_INSN_INT insn, ARGBUF *abuf,
+         int fast_p)
+{
+  const IDESC *id = @cpu@_decode (current_cpu, pc, insn, insn, abuf);
+  @cpu@_fill_argbuf (current_cpu, abuf, id, pc, fast_p);
+  if (! fast_p)
+    {
+      int trace_p = PC_IN_TRACE_RANGE_P (current_cpu, pc);
+      int profile_p = PC_IN_PROFILE_RANGE_P (current_cpu, pc);
+      @cpu@_fill_argbuf_tp (current_cpu, abuf, trace_p, profile_p);
+    }
+  return id;
+}
+
+static INLINE SEM_PC
+execute (SIM_CPU *current_cpu, SCACHE *sc, int fast_p)
+{
+  SEM_PC vpc;
+
+  /* Force R0 to zero before every insn.  */
+  @cpu@_h_gr_set (current_cpu, 0, 0);
+
+  if (fast_p)
+    {
+#if ! WITH_SEM_SWITCH_FAST
+#if WITH_SCACHE
+      vpc = (*sc->argbuf.semantic.sem_fast) (current_cpu, sc);
+#else
+      vpc = (*sc->argbuf.semantic.sem_fast) (current_cpu, &sc->argbuf);
+#endif
+#else
+      abort ();
+#endif /* WITH_SEM_SWITCH_FAST */
+    }
+  else
+    {
+#if ! WITH_SEM_SWITCH_FULL
+      ARGBUF *abuf = &sc->argbuf;
+      const IDESC *idesc = abuf->idesc;
+#if WITH_SCACHE_PBB
+      int virtual_p = CGEN_ATTR_VALUE (NULL, idesc->attrs, CGEN_INSN_VIRTUAL);
+#else
+      int virtual_p = 0;
+#endif
+
+      if (! virtual_p)
+	{
+	  /* FIXME: call x-before */
+	  if (ARGBUF_PROFILE_P (abuf))
+	    PROFILE_COUNT_INSN (current_cpu, abuf->addr, idesc->num);
+	  /* FIXME: Later make cover macros: PROFILE_INSN_{INIT,FINI}.  */
+	  if (PROFILE_MODEL_P (current_cpu)
+	      && ARGBUF_PROFILE_P (abuf))
+	    @cpu@_model_insn_before (current_cpu, 1 /*first_p*/);
+	  TRACE_INSN_INIT (current_cpu, abuf, 1);
+	  TRACE_INSN (current_cpu, idesc->idata,
+		      (const struct argbuf *) abuf, abuf->addr);
+	}
+#if WITH_SCACHE
+      vpc = (*sc->argbuf.semantic.sem_full) (current_cpu, sc);
+#else
+      vpc = (*sc->argbuf.semantic.sem_full) (current_cpu, abuf);
+#endif
+      if (! virtual_p)
+	{
+	  /* FIXME: call x-after */
+	  if (PROFILE_MODEL_P (current_cpu)
+	      && ARGBUF_PROFILE_P (abuf))
+	    {
+	      int cycles;
+
+	      cycles = (*idesc->timing->model_fn) (current_cpu, sc);
+	      @cpu@_model_insn_after (current_cpu, 1 /*last_p*/, cycles);
+	    }
+	  TRACE_INSN_FINI (current_cpu, abuf, 1);
+	}
+#else
+      abort ();
+#endif /* WITH_SEM_SWITCH_FULL */
+    }
+
+  return vpc;
+}
+
+EOF
+;;
+
+xinit)
+;;
+
+xextract-simple | xextract-scache)
+
+# Inputs:  current_cpu, vpc, sc, FAST_P
+# Outputs: sc filled in
+
+cat <<EOF
+{
+  CGEN_INSN_INT insn = GETIMEMUSI (current_cpu, CPU2INSN(vpc));
+  extract (current_cpu, vpc, insn, SEM_ARGBUF (sc), FAST_P);
+  SEM_SKIP_COMPILE (current_cpu, sc, 1);
+}
+EOF
+
+;;
+
+xextract-pbb)
+
+# Inputs:  current_cpu, pc, sc, max_insns, FAST_P
+# Outputs: sc, pc
+# sc must be left pointing past the last created entry.
+# pc must be left pointing past the last created entry.
+# If the pbb is terminated by a cti insn, SET_CTI_VPC(sc) must be called
+# to record the vpc of the cti insn.
+# SET_INSN_COUNT(n) must be called to record number of real insns.
+
+cat <<EOF
+{
+  const IDESC *idesc;
+  int icount = 0;
+
+  /* Is the CTI instruction at the end of the PBB a likely branch?  */
+  int likely_cti;
+
+  while (max_insns > 0)
+    {
+      USI insn = GETIMEMUSI (current_cpu, CPU2INSN(pc));
+      
+      idesc = extract (current_cpu, pc, insn, &sc->argbuf, FAST_P);
+      SEM_SKIP_COMPILE (current_cpu, sc, 1);
+      ++sc;
+      --max_insns;
+      ++icount;
+      pc += idesc->length;
+
+      if (IDESC_CTI_P (idesc))
+        {
+          /* Likely branches annul their delay slot if the branch is
+	     not taken by using the (skip ..) rtx.  We'll rely on
+	     that.  */
+          likely_cti = (IDESC_SKIP_P (idesc));
+
+          SET_CTI_VPC (sc - 1);
+
+          if (CGEN_ATTR_VALUE (NULL, idesc->attrs, CGEN_INSN_DELAY_SLOT))
+	    {
+              USI insn = GETIMEMUSI (current_cpu, CPU2INSN(pc));
+	      idesc = extract (current_cpu, pc, insn, &sc->argbuf, FAST_P);
+
+              if (likely_cti && IDESC_CTI_P (idesc))
+	        {
+	          /* malformed program */
+	          sim_io_eprintf (CPU_STATE (current_cpu),
+		    "malformed program, \`%s' insn in branch likely delay slot\n",
+		    CGEN_INSN_NAME (idesc->idata));
+	        }
+	      else
+	        {
+	          ++sc;
+	          --max_insns;
+	          ++icount;
+	          pc += idesc->length;
+	        }
+            }  
+	  break;
+	}
+    }
+
+ Finish:
+  SET_INSN_COUNT (icount);
+}
+EOF
+
+;;
+
+xfull-exec-* | xfast-exec-*)
+
+# Inputs: current_cpu, sc, FAST_P
+# Outputs: vpc
+# vpc contains the address of the next insn to execute
+
+cat <<EOF
+{
+#if (! FAST_P && WITH_SEM_SWITCH_FULL) || (FAST_P && WITH_SEM_SWITCH_FAST)
+#define DEFINE_SWITCH
+#include "sem-switch.c"
+#else
+  vpc = execute (current_cpu, vpc, FAST_P);
+#endif
+}
+EOF
+
+;;
+
+*)
+  echo "Invalid argument to mainloop.in: $1" >&2
+  exit 1
+  ;;
+
+esac
--- a/sim/iq2000/model.c
+++ b/sim/iq2000/model.c
--- a/sim/iq2000/sem-switch.c
+++ b/sim/iq2000/sem-switch.c
--- a/sim/iq2000/sem.c
+++ b/sim/iq2000/sem.c
--- a/sim/iq2000/sim-if.c
+++ b/sim/iq2000/sim-if.c
@ -0,0 +1,203 @@
+/* Main simulator entry points specific to the IQ2000.
+   Copyright (C) 2000 Free Software Foundation, Inc.
+   Contributed by Cygnus Solutions.
+
+This file is part of the GNU simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+#include "sim-main.h"
+#ifdef HAVE_STDLIB_H
+#include <stdlib.h>
+#endif
+#include "sim-options.h"
+#include "libiberty.h"
+#include "bfd.h"
+
+static void free_state (SIM_DESC);
+
+/* Records simulator descriptor so utilities like iq2000_dump_regs can be
+   called from gdb.  */
+SIM_DESC current_state;
+
+/* Cover function for sim_cgen_disassemble_insn.  */
+
+void
+iq2000bf_disassemble_insn (SIM_CPU *cpu, const CGEN_INSN *insn,
+			  const ARGBUF *abuf, IADDR pc, char *buf)
+{
+  sim_cgen_disassemble_insn(cpu, insn, abuf, pc, buf);
+}
+
+/* Cover function of sim_state_free to free the cpu buffers as well.  */
+
+static void
+free_state (SIM_DESC sd)
+{
+  if (STATE_MODULES (sd) != NULL)
+    sim_module_uninstall (sd);
+  sim_cpu_free_all (sd);
+  sim_state_free (sd);
+}
+
+/* Create an instance of the simulator.  */
+
+SIM_DESC
+sim_open (kind, callback, abfd, argv)
+     SIM_OPEN_KIND kind;
+     host_callback *callback;
+     struct bfd *abfd;
+     char **argv;
+{
+  char c;
+  int i;
+  SIM_DESC sd = sim_state_alloc (kind, callback);
+
+  /* The cpu data is kept in a separately allocated chunk of memory.  */
+  if (sim_cpu_alloc_all (sd, 1, cgen_cpu_max_extra_bytes ()) != SIM_RC_OK)
+    {
+      free_state (sd);
+      return 0;
+    }
+
+#if 0 /* FIXME: pc is in mach-specific struct */
+  /* FIXME: watchpoints code shouldn't need this */
+  {
+    SIM_CPU *current_cpu = STATE_CPU (sd, 0);
+    STATE_WATCHPOINTS (sd)->pc = &(PC);
+    STATE_WATCHPOINTS (sd)->sizeof_pc = sizeof (PC);
+  }
+#endif
+
+  if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
+    {
+      free_state (sd);
+      return 0;
+    }
+
+#if 0 /* FIXME: 'twould be nice if we could do this */
+  /* These options override any module options.
+     Obviously ambiguity should be avoided, however the caller may wish to
+     augment the meaning of an option.  */
+  if (extra_options != NULL)
+    sim_add_option_table (sd, extra_options);
+#endif
+
+  /* getopt will print the error message so we just have to exit if this fails.
+     FIXME: Hmmm...  in the case of gdb we need getopt to call
+     print_filtered.  */
+  if (sim_parse_args (sd, argv) != SIM_RC_OK)
+    {
+      free_state (sd);
+      return 0;
+    }
+
+  /* Allocate core managed memory.  */
+  sim_do_commandf (sd, "memory region 0x%lx,0x%lx", IQ2000_INSN_VALUE, IQ2000_INSN_MEM_SIZE); 
+  sim_do_commandf (sd, "memory region 0x%lx,0x%lx", IQ2000_DATA_VALUE, IQ2000_DATA_MEM_SIZE); 
+
+  /* check for/establish the reference program image */
+  if (sim_analyze_program (sd,
+			   (STATE_PROG_ARGV (sd) != NULL
+			    ? *STATE_PROG_ARGV (sd)
+			    : NULL),
+			   abfd) != SIM_RC_OK)
+    {
+      free_state (sd);
+      return 0;
+    }
+
+  /* Establish any remaining configuration options.  */
+  if (sim_config (sd) != SIM_RC_OK)
+    {
+      free_state (sd);
+      return 0;
+    }
+
+  if (sim_post_argv_init (sd) != SIM_RC_OK)
+    {
+      free_state (sd);
+      return 0;
+    }
+
+  /* Open a copy of the cpu descriptor table.  */
+  {
+    CGEN_CPU_DESC cd = iq2000_cgen_cpu_open_1 (STATE_ARCHITECTURE (sd)->printable_name,
+					      CGEN_ENDIAN_BIG);
+
+    for (i = 0; i < MAX_NR_PROCESSORS; ++i)
+      {
+	SIM_CPU *cpu = STATE_CPU (sd, i);
+	CPU_CPU_DESC (cpu) = cd;
+	CPU_DISASSEMBLER (cpu) = iq2000bf_disassemble_insn;
+      }
+    iq2000_cgen_init_dis (cd);
+  }
+
+  /* Initialize various cgen things not done by common framework.
+     Must be done after iq2000_cgen_cpu_open.  */
+  cgen_init (sd);
+
+  /* Store in a global so things like sparc32_dump_regs can be invoked
+     from the gdb command line.  */
+  current_state = sd;
+
+  return sd;
+}
+
+void
+sim_close (sd, quitting)
+     SIM_DESC sd;
+     int quitting;
+{
+  iq2000_cgen_cpu_close (CPU_CPU_DESC (STATE_CPU (sd, 0)));
+  sim_module_uninstall (sd);
+}
+
+SIM_RC
+sim_create_inferior (sd, abfd, argv, envp)
+     SIM_DESC sd;
+     struct bfd *abfd;
+     char **argv;
+     char **envp;
+{
+  SIM_CPU *current_cpu = STATE_CPU (sd, 0);
+  SIM_ADDR addr;
+
+  if (abfd != NULL)
+    addr = bfd_get_start_address (abfd);
+  else
+    addr = CPU2INSN(0);
+  sim_pc_set (current_cpu, addr);
+
+#if 0
+  STATE_ARGV (sd) = sim_copy_argv (argv);
+  STATE_ENVP (sd) = sim_copy_argv (envp);
+#endif
+
+  return SIM_RC_OK;
+}
+
+void
+sim_do_command (sd, cmd)
+     SIM_DESC sd;
+     char *cmd;
+{ 
+  if (sim_args_command (sd, cmd) != SIM_RC_OK)
+    sim_io_eprintf (sd, "Unknown command `%s'\n", cmd);
+}
+
+
+
--- a/sim/iq2000/sim-main.h
+++ b/sim/iq2000/sim-main.h
@ -0,0 +1,84 @@
+
+/* Main header for the Vitesse IQ2000.  */
+
+#ifndef SIM_MAIN_H
+#define SIM_MAIN_H
+
+#define USING_SIM_BASE_H /* FIXME: quick hack */
+
+struct _sim_cpu; /* FIXME: should be in sim-basics.h */
+typedef struct _sim_cpu SIM_CPU;
+
+/* sim-basics.h includes config.h but cgen-types.h must be included before
+   sim-basics.h and cgen-types.h needs config.h.  */
+#include "config.h"
+
+#include "symcat.h"
+#include "sim-basics.h"
+#include "cgen-types.h"
+#include "iq2000-desc.h"
+#include "iq2000-opc.h"
+#include "arch.h"
+
+/* Pull in IQ2000_{DATA,INSN}_{MASK,VALUE}.  */
+#include "elf/iq2000.h"
+
+/* These must be defined before sim-base.h.  */
+typedef USI sim_cia;
+
+#define CIA_GET(cpu)     CPU_PC_GET (cpu)
+#define CIA_SET(cpu,val) CPU_PC_SET ((cpu), (val))
+
+#include "sim-base.h"
+#include "cgen-sim.h"
+#include "iq2000-sim.h"
+
+/* The _sim_cpu struct.  */
+
+struct _sim_cpu {
+  /* sim/common cpu base.  */
+  sim_cpu_base base;
+
+  /* Static parts of cgen.  */
+  CGEN_CPU cgen_cpu;
+
+  /* CPU specific parts go here.
+     Note that in files that don't need to access these pieces WANT_CPU_FOO
+     won't be defined and thus these parts won't appear.  This is ok in the
+     sense that things work.  It is a source of bugs though.
+     One has to of course be careful to not take the size of this
+     struct and no structure members accessed in non-cpu specific files can
+     go after here.  Oh for a better language.  */
+#if defined (WANT_CPU_IQ2000BF)
+  IQ2000BF_CPU_DATA cpu_data;
+#endif
+};
+
+/* The sim_state struct.  */
+
+struct sim_state {
+  sim_cpu *cpu;
+#define STATE_CPU(sd, n) (/*&*/ (sd)->cpu)
+
+  CGEN_STATE cgen_state;
+
+  sim_state_base base;
+};
+
+/* Misc.  */
+
+/* Catch address exceptions.  */
+extern SIM_CORE_SIGNAL_FN iq2000_core_signal;
+#define SIM_CORE_SIGNAL(SD,CPU,CIA,MAP,NR_BYTES,ADDR,TRANSFER,ERROR) \
+iq2000_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), \
+		  (TRANSFER), (ERROR))
+
+/* Convert between CPU-internal addresses and sim_core addresses.  */
+#define CPU2DATA(addr) (IQ2000_DATA_VALUE + (addr))
+#define DATA2CPU(addr) ((addr) - IQ2000_DATA_VALUE)
+#define CPU2INSN(addr) (IQ2000_INSN_VALUE + ((addr) & ~IQ2000_INSN_MASK))
+#define INSN2CPU(addr) ((addr) - IQ2000_INSN_VALUE)
+#define IQ2000_INSN_MEM_SIZE (CPU2INSN(0x800000) - CPU2INSN(0x0000))
+#define IQ2000_DATA_MEM_SIZE (CPU2DATA(0x800000) - CPU2DATA(0x0000))
+
+#endif /* SIM_MAIN_H */
--- a/sim/iq2000/tconfig.in
+++ b/sim/iq2000/tconfig.in
@ -0,0 +1,42 @@
+/* IQ2000 target configuration file.  -*- C -*- */
+
+/* Define this if the simulator can vary the size of memory.
+   See the xxx simulator for an example.
+   This enables the `-m size' option.
+   The memory size is stored in STATE_MEM_SIZE.  */
+/* Not used for IQ2000 since we use the memory module. TODO -- check this  */
+/* #define SIM_HAVE_MEM_SIZE */
+
+/* See sim-hload.c.  We properly handle LMA. -- TODO: check this */
+#define SIM_HANDLES_LMA 1
+
+/* For MSPR support.  FIXME: revisit.  */
+#define WITH_DEVICES 0
+
+/* FIXME: Revisit.  */
+#ifdef HAVE_DV_SOCKSER
+MODULE_INSTALL_FN dv_sockser_install;
+#define MODULE_LIST dv_sockser_install,
+#endif
+
+#if 0
+/* Enable watchpoints.  */
+#define WITH_WATCHPOINTS 1
+#endif
+
+/* ??? Temporary hack until model support unified.  */
+#define SIM_HAVE_MODEL
+
+/* Define this to enable the intrinsic breakpoint mechanism. */
+/* FIXME: may be able to remove SIM_HAVE_BREAKPOINTS since it essentially
+   duplicates ifdef SIM_BREAKPOINT (right?) */
+#if 1
+#define SIM_HAVE_BREAKPOINTS
+#define SIM_BREAKPOINT { 0, 0, 0, 0xD }
+#define SIM_BREAKPOINT_SIZE 4
+#endif
+
+/* This is a global setting.  Different cpu families can't mix-n-match -scache
+   and -pbb.  However some cpu families may use -simple while others use
+   one of -scache/-pbb. ???? */
+#define WITH_SCACHE_PBB 1