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@ -141,7 +141,7 @@ frv_is_media_insn (const CGEN_INSN *insn) |
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/* This table represents the allowable packing for vliw insns for the fr400.
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The fr400 has only 2 vliw slots. Represent this by not allowing any insns |
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in slots 2 and 3. |
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in the extra slots. |
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Subsets of any given row are also allowed. */ |
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static VLIW_COMBO fr400_allowed_vliw[] = |
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{ |
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@ -184,15 +184,23 @@ static CGEN_ATTR_VALUE_TYPE fr400_unit_mapping[] = |
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/* I0 */ UNIT_I0, |
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/* I1 */ UNIT_I1, |
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/* I01 */ UNIT_I01, |
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/* IALL */ UNIT_I01, /* only I0 and I1 units */ |
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/* FM0 */ UNIT_FM0, |
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/* FM1 */ UNIT_FM1, |
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/* FM01 */ UNIT_FM01, |
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/* FMALL */ UNIT_FM01,/* Only F0,F1,M0,M1 units */ |
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/* FMLOW */ UNIT_FM0, /* Only F0,M0 units */ |
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/* B0 */ UNIT_B0, /* branches only in B0 unit. */ |
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/* B1 */ UNIT_B0, |
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/* B01 */ UNIT_B0, |
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/* C */ UNIT_C, |
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/* MULT-DIV */ UNIT_I0, /* multiply and divide only in I0 unit. */ |
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/* LOAD */ UNIT_I0 /* load only in I0 unit. */ |
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/* MULT-DIV */ UNIT_I0, /* multiply and divide only in I0 unit. */ |
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/* LOAD */ UNIT_I0, /* load only in I0 unit. */ |
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/* STORE */ UNIT_I0, /* store only in I0 unit. */ |
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/* SCAN */ UNIT_I0, /* scan only in I0 unit. */ |
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/* DCPL */ UNIT_C, /* dcpl only in C unit. */ |
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/* MDUALACC */ UNIT_FM0, /* media dual acc insn only in FM0 unit. */ |
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/* MCLRACC-1*/ UNIT_FM0 /* mclracc,A==1 insn only in FM0 unit. */ |
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}; |
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static CGEN_ATTR_VALUE_TYPE fr500_unit_mapping[] = |
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@ -202,15 +210,23 @@ static CGEN_ATTR_VALUE_TYPE fr500_unit_mapping[] = |
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/* I0 */ UNIT_I0, |
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/* I1 */ UNIT_I1, |
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/* I01 */ UNIT_I01, |
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/* IALL */ UNIT_I01, /* only I0 and I1 units */ |
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/* FM0 */ UNIT_FM0, |
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/* FM1 */ UNIT_FM1, |
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/* FM01 */ UNIT_FM01, |
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/* FMALL */ UNIT_FM01,/* Only F0,F1,M0,M1 units */ |
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/* FMLOW */ UNIT_FM0, /* Only F0,M0 units */ |
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/* B0 */ UNIT_B0, |
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/* B1 */ UNIT_B1, |
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/* B01 */ UNIT_B01, |
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/* C */ UNIT_C, |
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/* MULT-DIV */ UNIT_I01, /* multiply and divide in I0 or I1 unit. */ |
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/* LOAD */ UNIT_I01 /* load in I0 or I1 unit. */ |
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/* LOAD */ UNIT_I01, /* load in I0 or I1 unit. */ |
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/* STORE */ UNIT_I0, /* store only in I0 unit. */ |
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/* SCAN */ UNIT_I01, /* scan in I0 or I1 unit. */ |
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/* DCPL */ UNIT_C, /* dcpl only in C unit. */ |
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/* MDUALACC */ UNIT_FM0, /* media dual acc insn only in FM0 unit. */ |
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/* MCLRACC-1*/ UNIT_FM01 /* mclracc,A==1 in FM0 or FM1 unit. */ |
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}; |
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void |
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@ -493,10 +509,15 @@ frv_vliw_add_insn (FRV_VLIW *vliw, const CGEN_INSN *insn) |
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if (unit == UNIT_NIL) |
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abort (); /* no UNIT specified for this insn in frv.cpu */ |
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if (vliw->mach == bfd_mach_fr400) |
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major = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR400_MAJOR); |
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else |
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major = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR500_MAJOR); |
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switch (vliw->mach) |
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{ |
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case bfd_mach_fr400: |
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major = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR400_MAJOR); |
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break; |
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default: |
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major = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR500_MAJOR); |
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break; |
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} |
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if (index <= 0) |
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{ |
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@ -1133,8 +1154,12 @@ static const CGEN_IFMT ifmt_cmbtohe = { |
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32, 32, 0x1fff0c0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_FRI_NULL) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_FRJ) }, { 0 } } |
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}; |
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static const CGEN_IFMT ifmt_mclracc = { |
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32, 32, 0x1fdffff, { { F (F_PACK) }, { F (F_ACC40SK) }, { F (F_OP) }, { F (F_A) }, { F (F_MISC_NULL_10) }, { F (F_OPE1) }, { F (F_FRJ_NULL) }, { 0 } } |
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static const CGEN_IFMT ifmt_mnop = { |
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32, 32, 0x7fffffff, { { F (F_PACK) }, { F (F_ACC40SK) }, { F (F_OP) }, { F (F_A) }, { F (F_MISC_NULL_10) }, { F (F_OPE1) }, { F (F_FRJ_NULL) }, { 0 } } |
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}; |
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static const CGEN_IFMT ifmt_mclracc_0 = { |
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32, 32, 0x1ffffff, { { F (F_PACK) }, { F (F_ACC40SK) }, { F (F_OP) }, { F (F_A) }, { F (F_MISC_NULL_10) }, { F (F_OPE1) }, { F (F_FRJ_NULL) }, { 0 } } |
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}; |
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static const CGEN_IFMT ifmt_mrdacc = { |
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@ -5560,11 +5585,23 @@ static const CGEN_OPCODE frv_cgen_insn_opcode_table[MAX_INSNS] = |
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{ { MNEM, OP (PACK), ' ', OP (FRINTJ), ',', OP (FRINTK), ',', OP (CCI), ',', OP (COND), 0 } }, |
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& ifmt_cmbtohe, { 0x1dc0080 } |
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}, |
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/* mclracc$pack $ACC40Sk,$A */ |
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/* mnop$pack */ |
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{ |
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{ 0, 0, 0, 0 }, |
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{ { MNEM, OP (PACK), 0 } }, |
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& ifmt_mnop, { 0x7fee0ec0 } |
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}, |
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/* mclracc$pack $ACC40Sk,$A0 */ |
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{ |
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{ 0, 0, 0, 0 }, |
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{ { MNEM, OP (PACK), ' ', OP (ACC40SK), ',', OP (A), 0 } }, |
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& ifmt_mclracc, { 0x1ec0ec0 } |
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{ { MNEM, OP (PACK), ' ', OP (ACC40SK), ',', OP (A0), 0 } }, |
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& ifmt_mclracc_0, { 0x1ec0ec0 } |
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}, |
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/* mclracc$pack $ACC40Sk,$A1 */ |
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{ |
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{ 0, 0, 0, 0 }, |
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{ { MNEM, OP (PACK), ' ', OP (ACC40SK), ',', OP (A1), 0 } }, |
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& ifmt_mclracc_0, { 0x1ee0ec0 } |
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}, |
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/* mrdacc$pack $ACC40Si,$FRintk */ |
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{ |
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@ -5626,10 +5663,6 @@ static const CGEN_IFMT ifmt_nop = { |
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32, 32, 0x7fffffff, { { F (F_PACK) }, { F (F_GRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_D12) }, { 0 } } |
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}; |
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static const CGEN_IFMT ifmt_mnop = { |
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32, 32, 0x7fffffff, { { F (F_PACK) }, { F (F_ACC40SK) }, { F (F_OP) }, { F (F_A) }, { F (F_MISC_NULL_10) }, { F (F_OPE1) }, { F (F_FRJ_NULL) }, { 0 } } |
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}; |
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static const CGEN_IFMT ifmt_ret = { |
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32, 32, 0x7fffffff, { { F (F_PACK) }, { F (F_INT_CC) }, { F (F_ICCI_2_NULL) }, { F (F_OP) }, { F (F_HINT) }, { F (F_OPE3) }, { F (F_CCOND_NULL) }, { F (F_S12_NULL) }, { 0 } } |
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}; |
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@ -5678,12 +5711,7 @@ static const CGEN_IBASE frv_cgen_macro_insn_table[] = |
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/* nop$pack */ |
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{ |
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-1, "nop", "nop", 32, |
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{ 0|A(ALIAS), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } |
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}, |
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/* mnop$pack */ |
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{ |
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-1, "mnop", "mnop", 32, |
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{ 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_M_3 } } |
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{ 0|A(ALIAS), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } |
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}, |
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/* ret$pack */ |
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{ |
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@ -5693,27 +5721,27 @@ static const CGEN_IBASE frv_cgen_macro_insn_table[] = |
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/* cmp$pack $GRi,$GRj,$ICCi_1 */ |
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{ |
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-1, "cmp", "cmp", 32, |
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{ 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } |
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{ 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } |
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}, |
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/* cmpi$pack $GRi,$s10,$ICCi_1 */ |
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{ |
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-1, "cmpi", "cmpi", 32, |
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{ 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } |
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{ 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } |
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}, |
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/* ccmp$pack $GRi,$GRj,$CCi,$cond */ |
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{ |
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-1, "ccmp", "ccmp", 32, |
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{ 0|A(CONDITIONAL)|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } |
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{ 0|A(CONDITIONAL)|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } |
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}, |
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/* mov$pack $GRi,$GRk */ |
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{ |
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-1, "mov", "mov", 32, |
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{ 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } |
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{ 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } |
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}, |
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/* cmov$pack $GRi,$GRk,$CCi,$cond */ |
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{ |
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-1, "cmov", "cmov", 32, |
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{ 0|A(CONDITIONAL)|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), UNIT_I01, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } |
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{ 0|A(CONDITIONAL)|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1 } } |
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}, |
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}; |
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@ -5727,12 +5755,6 @@ static const CGEN_OPCODE frv_cgen_macro_insn_opcode_table[] = |
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{ { MNEM, OP (PACK), 0 } }, |
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& ifmt_nop, { 0x880000 } |
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}, |
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/* mnop$pack */ |
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{ |
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{ 0, 0, 0, 0 }, |
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{ { MNEM, OP (PACK), 0 } }, |
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& ifmt_mnop, { 0x7fee0ec0 } |
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}, |
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/* ret$pack */ |
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{ |
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{ 0, 0, 0, 0 }, |
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Dave Brolley
23 years ago