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* R5900 COP2 function nearly complete. PKE sim now aware of new GPUIF 

masking facility for PATH3 transfers.

[ChangeLog.sky]

Sun Apr  5 12:11:45 1998  Frank Ch. Eigler  <fche@cygnus.com>

	* sky-libvpe.c (exec-inst): Added "M" bit detection for upper
 	instruction.

	* sky-pke.c (pke_check_stall): Added more assertions.
	(pke_code_mskpath3): Use new GPUIF M3P control register.

	* sky-pke.h (VU[01]_CIA): New macros that give VU CIA
 	pseudo-register addresses.

	* sky-vu.h (vu_device, VectorUnitState): Merged structs.
	(VectorUnitState.mflag): New field.
	(VU_REG_{CMSAR0,CMSAR1,FBRST}) Added missing control registers.

	* sky-vu.c (vu0_busy): New function.
	(vu0_q_busy): New function.
	(vu0_macro_issue): New function.
	(vu0_micro_interlock_released): New function.
	(vu0_busy_in_{micro,macro}_mode): Deleted stubs.
	(vu0_macro_hazard_check): Deleted stubs.
	(vu_attach): Adapted code to merged device & state struct.
	(read_vu_special_reg): Compute VBS0/VBS1 bits in STAT register.

[ChangeLog]
start-sanitize-sky
Sun Apr  5 12:05:44 1998  Frank Ch. Eigler  <fche@cygnus.com>

	* interp.c (*): Adapt code to merged VU device & state structs.
	(decode_coproc): Execute COP2 each macroinstruction without
 	pipelining, by stepping VU to completion state.  Adapted to
	read_vu_*_reg style of register access.

	* mips.igen ([SL]QC2): Removed these COP2 instructions.

	* r5900.igen ([SL]QC2): Transplanted these COP2 instructions here.

	* sim-main.h (cop_[ls]q): Enclosed in TARGET_SKY guards.

end-sanitize-sky
gdb-4_18-branch
Frank Ch. Eigler 29 years ago
parent
d61cc1d4b1
commit
ebcfd86a2e
6 changed files with 371 additions and 935 deletions
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  1. 16
      sim/mips/ChangeLog
  2. 214
      sim/mips/interp.c
  3. 1056
      sim/mips/mips.igen
  4. 8
      sim/mips/sim-main.h
  5. 9
      sim/mips/sky-pke.c
  6. 3
      sim/mips/sky-pke.h

16
sim/mips/ChangeLog
View File

@ -1,3 +1,19 @@
start-sanitize-sky
Sun Apr 5 12:05:44 1998 Frank Ch. Eigler <fche@cygnus.com>
* interp.c (*): Adapt code to merged VU device & state structs.
(decode_coproc): Execute COP2 each macroinstruction without
pipelining, by stepping VU to completion state. Adapted to
read_vu_*_reg style of register access.
* mips.igen ([SL]QC2): Removed these COP2 instructions.
* r5900.igen ([SL]QC2): Transplanted these COP2 instructions here.
* sim-main.h (cop_[ls]q): Enclosed in TARGET_SKY guards.
end-sanitize-sky
Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
* Makefile.in (SIM_OBJS): Add sim-main.o.

214
sim/mips/interp.c
View File

@ -44,6 +44,7 @@ code on the hardware.
#include "sky-vpe.h"
#include "sky-libvpe.h"
#include "sky-pke.h"
#include "idecode.h"
#endif
/* end-sanitize-sky */
@ -671,31 +672,31 @@ sim_store_register (sd,rn,memory,length)
if( rn < NUM_VU_REGS )
{
if (rn < NUM_VU_INTEGER_REGS)
return write_vu_int_reg (&(vu0_device.state->regs), rn, memory);
return write_vu_int_reg (&(vu0_device.regs), rn, memory);
else if (rn >= FIRST_VEC_REG)
{
rn -= FIRST_VEC_REG;
return write_vu_vec_reg (&(vu0_device.state->regs), rn>>2, rn&3,
return write_vu_vec_reg (&(vu0_device.regs), rn>>2, rn&3,
memory);
}
else switch (rn - NUM_VU_INTEGER_REGS)
{
case 0:
return write_vu_special_reg (vu0_device.state, VU_REG_CIA,
return write_vu_special_reg (&vu0_device, VU_REG_CIA,
memory);
case 1:
return write_vu_misc_reg (&(vu0_device.state->regs), VU_REG_MR,
return write_vu_misc_reg (&(vu0_device.regs), VU_REG_MR,
memory);
case 2: /* VU0 has no P register */
return 4;
case 3:
return write_vu_misc_reg (&(vu0_device.state->regs), VU_REG_MI,
return write_vu_misc_reg (&(vu0_device.regs), VU_REG_MI,
memory);
case 4:
return write_vu_misc_reg (&(vu0_device.state->regs), VU_REG_MQ,
return write_vu_misc_reg (&(vu0_device.regs), VU_REG_MQ,
memory);
default:
return write_vu_acc_reg (&(vu0_device.state->regs),
return write_vu_acc_reg (&(vu0_device.regs),
rn - (NUM_VU_INTEGER_REGS + 5),
memory);
}
@ -706,32 +707,32 @@ sim_store_register (sd,rn,memory,length)
if (rn < NUM_VU_REGS)
{
if (rn < NUM_VU_INTEGER_REGS)
return write_vu_int_reg (&(vu1_device.state->regs), rn, memory);
return write_vu_int_reg (&(vu1_device.regs), rn, memory);
else if (rn >= FIRST_VEC_REG)
{
rn -= FIRST_VEC_REG;
return write_vu_vec_reg (&(vu1_device.state->regs),
return write_vu_vec_reg (&(vu1_device.regs),
rn >> 2, rn & 3, memory);
}
else switch (rn - NUM_VU_INTEGER_REGS)
{
case 0:
return write_vu_special_reg (vu1_device.state, VU_REG_CIA,
return write_vu_special_reg (&vu1_device, VU_REG_CIA,
memory);
case 1:
return write_vu_misc_reg (&(vu1_device.state->regs), VU_REG_MR,
return write_vu_misc_reg (&(vu1_device.regs), VU_REG_MR,
memory);
case 2:
return write_vu_misc_reg (&(vu1_device.state->regs), VU_REG_MP,
return write_vu_misc_reg (&(vu1_device.regs), VU_REG_MP,
memory);
case 3:
return write_vu_misc_reg (&(vu1_device.state->regs), VU_REG_MI,
return write_vu_misc_reg (&(vu1_device.regs), VU_REG_MI,
memory);
case 4:
return write_vu_misc_reg (&(vu1_device.state->regs), VU_REG_MQ,
return write_vu_misc_reg (&(vu1_device.regs), VU_REG_MQ,
memory);
default:
return write_vu_acc_reg (&(vu1_device.state->regs),
return write_vu_acc_reg (&(vu1_device.regs),
rn - (NUM_VU_INTEGER_REGS + 5),
memory);
}
@ -846,31 +847,31 @@ sim_fetch_register (sd,rn,memory,length)
if (rn < NUM_VU_REGS)
{
if (rn < NUM_VU_INTEGER_REGS)
return read_vu_int_reg (&(vu0_device.state->regs), rn, memory);
return read_vu_int_reg (&(vu0_device.regs), rn, memory);
else if (rn >= FIRST_VEC_REG)
{
rn -= FIRST_VEC_REG;
return read_vu_vec_reg (&(vu0_device.state->regs), rn>>2, rn & 3,
return read_vu_vec_reg (&(vu0_device.regs), rn>>2, rn & 3,
memory);
}
else switch (rn - NUM_VU_INTEGER_REGS)
{
case 0:
return read_vu_special_reg(vu0_device.state, VU_REG_CIA, memory);
return read_vu_special_reg(&vu0_device, VU_REG_CIA, memory);
case 1:
return read_vu_misc_reg (&(vu0_device.state->regs), VU_REG_MR,
return read_vu_misc_reg (&(vu0_device.regs), VU_REG_MR,
memory);
case 2: /* VU0 has no P register */
*((int *) memory) = 0;
return 4;
case 3:
return read_vu_misc_reg (&(vu0_device.state->regs), VU_REG_MI,
return read_vu_misc_reg (&(vu0_device.regs), VU_REG_MI,
memory);
case 4:
return read_vu_misc_reg (&(vu0_device.state->regs), VU_REG_MQ,
return read_vu_misc_reg (&(vu0_device.regs), VU_REG_MQ,
memory);
default:
return read_vu_acc_reg (&(vu0_device.state->regs),
return read_vu_acc_reg (&(vu0_device.regs),
rn - (NUM_VU_INTEGER_REGS + 5),
memory);
}
@ -881,31 +882,31 @@ sim_fetch_register (sd,rn,memory,length)
if (rn < NUM_VU_REGS)
{
if (rn < NUM_VU_INTEGER_REGS)
return read_vu_int_reg (&(vu1_device.state->regs), rn, memory);
return read_vu_int_reg (&(vu1_device.regs), rn, memory);
else if (rn >= FIRST_VEC_REG)
{
rn -= FIRST_VEC_REG;
return read_vu_vec_reg (&(vu1_device.state->regs),
return read_vu_vec_reg (&(vu1_device.regs),
rn >> 2, rn & 3, memory);
}
else switch (rn - NUM_VU_INTEGER_REGS)
{
case 0:
return read_vu_special_reg(vu1_device.state, VU_REG_CIA, memory);
return read_vu_special_reg(&vu1_device, VU_REG_CIA, memory);
case 1:
return read_vu_misc_reg (&(vu1_device.state->regs),
return read_vu_misc_reg (&(vu1_device.regs),
VU_REG_MR, memory);
case 2:
return read_vu_misc_reg (&(vu1_device.state->regs),
return read_vu_misc_reg (&(vu1_device.regs),
VU_REG_MP, memory);
case 3:
return read_vu_misc_reg (&(vu1_device.state->regs),
return read_vu_misc_reg (&(vu1_device.regs),
VU_REG_MI, memory);
case 4:
return read_vu_misc_reg (&(vu1_device.state->regs),
return read_vu_misc_reg (&(vu1_device.regs),
VU_REG_MQ, memory);
default:
return read_vu_acc_reg (&(vu1_device.state->regs),
return read_vu_acc_reg (&(vu1_device.regs),
rn - (NUM_VU_INTEGER_REGS + 5),
memory);
}
@ -3213,7 +3214,7 @@ decode_coproc (SIM_DESC sd,
}
break;
case 2: /* undefined co-processor */
case 2: /* co-processor 2 */
{
int handle = 0;
@ -3223,12 +3224,14 @@ decode_coproc (SIM_DESC sd,
int i_25_21 = (instruction >> 21) & 0x1f;
int i_20_16 = (instruction >> 16) & 0x1f;
int i_20_6 = (instruction >> 6) & 0x7fff;
int i_15_11 = (instruction >> 11) & 0x1f;
int i_15_0 = instruction & 0xffff;
int i_10_1 = (instruction >> 1) & 0x3ff;
int i_10_0 = instruction & 0x7ff;
int i_10_6 = (instruction >> 6) & 0x1f;
int i_5_0 = instruction & 0x03f;
int interlock = instruction & 0x01;
int co = (instruction >> 25) & 0x01;
/* setup for semantic.c-like actions below */
typedef unsigned_4 instruction_word;
int CIA = cia;
@ -3272,101 +3275,134 @@ decode_coproc (SIM_DESC sd,
{
int rt = i_20_16;
int id = i_15_11;
address_word vu_cr_addr; /* VU control register address */
unsigned_4 data;
/* interlock checking */
if(vu0_busy_in_macro_mode()) /* busy in macro mode */
{
/* interlock bit invalid here */
if(interlock)
; /* XXX: warning */
/* POLICY: never busy in macro mode */
while(vu0_busy() && interlock)
vu0_issue(sd);
/* always check data hazard */
while(vu0_macro_hazard_check(id))
vu0_issue(sd);
}
else if(vu0_busy_in_micro_mode() && interlock)
/* perform VU register address */
if(i_25_21 == 0x01) /* QMFC2 */
{
while(vu0_busy_in_micro_mode())
vu0_issue(sd);
unsigned_16 xyzw;
/* one word at a time, argh! */
read_vu_vec_reg(&(vu0_device.regs), id, 0, A4_16(& xyzw, 3));
read_vu_vec_reg(&(vu0_device.regs), id, 1, A4_16(& xyzw, 2));
read_vu_vec_reg(&(vu0_device.regs), id, 2, A4_16(& xyzw, 1));
read_vu_vec_reg(&(vu0_device.regs), id, 3, A4_16(& xyzw, 0));
xyzw = T2H_16(xyzw);
memcpy(& GPR[rt], & xyzw, sizeof(xyzw));
}
/* compute VU register address */
if(i_25_21 == 0x01) /* QMFC2 */
vu_cr_addr = VU0_REGISTER_WINDOW_START + (id * 16);
else /* CFC2 */
vu_cr_addr = VU0_MST + (id * 16);
/* read or write word */
data = sim_core_read_aligned_4(cpu, cia, read_map, vu_cr_addr);
GPR[rt] = EXTEND64(data);
{
unsigned_4 data;
/* enum + int calculation, argh! */
id = VU_REG_MST + 16 * id;
read_vu_misc_reg(&(vu0_device.regs), id, & data);
GPR[rt] = EXTEND32(T2H_4(data));
}
}
else if((i_25_21 == 0x06 && i_10_1 == 0x000) || /* CTC2 */
(i_25_21 == 0x05)) /* QMTC2 */
{
int rt = i_20_16;
int id = i_15_11;
address_word vu_cr_addr; /* VU control register address */
unsigned_4 data;
/* interlock checking */
if(vu0_busy_in_macro_mode()) /* busy in macro mode */
/* POLICY: never busy in macro mode */
if(vu0_busy() && interlock)
{
/* interlock bit invalid here */
if(interlock)
; /* XXX: warning */
/* always check data hazard */
while(vu0_macro_hazard_check(id))
while(! vu0_micro_interlock_released())
vu0_issue(sd);
}
else if(vu0_busy_in_micro_mode())
/* perform VU register address */
if(i_25_21 == 0x05) /* QMTC2 */
{
if(interlock)
{
while(! vu0_micro_interlock_released())
vu0_issue(sd);
}
unsigned_16 xyzw;
memcpy(& xyzw, & GPR[rt], sizeof(xyzw));
xyzw = H2T_16(xyzw);
/* one word at a time, argh! */
write_vu_vec_reg(&(vu0_device.regs), id, 0, A4_16(& xyzw, 3));
write_vu_vec_reg(&(vu0_device.regs), id, 1, A4_16(& xyzw, 2));
write_vu_vec_reg(&(vu0_device.regs), id, 2, A4_16(& xyzw, 1));
write_vu_vec_reg(&(vu0_device.regs), id, 3, A4_16(& xyzw, 0));
}
/* compute VU register address */
if(i_25_21 == 0x05) /* QMTC2 */
vu_cr_addr = VU0_REGISTER_WINDOW_START + (id * 16);
else /* CTC2 */
vu_cr_addr = VU0_MST + (id * 16);
{
unsigned_4 data = H2T_4(GPR[rt]);
/* enum + int calculation, argh! */
id = VU_REG_MST + 16 * id;
write_vu_misc_reg(&(vu0_device.regs), id, & data);
}
}
else if(i_10_0 == 0x3bf) /* VWAITQ */
{
while(vu0_q_busy())
vu0_issue(sd);
}
else if(i_5_0 == 0x38) /* VCALLMS */
{
unsigned_4 data = H2T_2(i_20_6);
while(vu0_busy())
vu0_issue(sd);
/* write to reserved CIA register to get VU0 moving */
write_vu_misc_reg(&(vu0_device.regs), VU_REG_CIA, & data);
}
else if(i_5_0 == 0x39) /* VCALLMSR */
{
unsigned_4 data;
while(vu0_busy())
vu0_issue(sd);
data = GPR[rt];
sim_core_write_aligned_4(cpu, cia, write_map, vu_cr_addr, data);
read_vu_misc_reg(&(vu0_device.regs), VU_REG_CMSAR0, & data);
/* write to reserved CIA register to get VU0 moving */
write_vu_misc_reg(&(vu0_device.regs), VU_REG_CIA, & data);
}
else if( 0 /* XXX: ... upper ... */)
/* handle all remaining UPPER VU instructions in one block */
else if((i_5_0 < 0x30) || /* VADDx .. VMINI */
(i_5_0 >= 0x3c && i_10_6 < 0x0c)) /* VADDAx .. VNOP */
{
unsigned_4 vu_upper, vu_lower;
vu_upper =
0x00000000 | /* bits 31 .. 25 */
instruction & 0x01ffffff; /* bits 24 .. 0 */
0x40000000 | /* bits 31 .. 25 */
(instruction & 0x01ffffff); /* bits 24 .. 0 */
vu_lower = 0x8000033c; /* NOP */
while(vu0_busy_in_micro_mode())
/* POLICY: never busy in macro mode */
while(vu0_busy())
vu0_issue(sd);
vu0_macro_issue(vu_upper, vu_lower);
/* POLICY: wait for completion of macro-instruction */
while(vu0_busy())
vu0_issue(sd);
}
else if( 0 /* XXX: ... lower ... */)
{
/* handle all remaining LOWER VU instructions in one block */
else if((i_5_0 >= 0x30 && i_5_0 <= 0x35) || /* VIADD .. VIOR */
(i_5_0 >= 0x3c && i_10_6 >= 0x0c)) /* VMOVE .. VRXOR */
{ /* N.B.: VWAITQ already covered by prior case */
unsigned_4 vu_upper, vu_lower;
vu_upper = 0x000002ff; /* NOP */
vu_upper = 0x400002ff; /* END/NOP */
vu_lower =
0x10000000 | /* bits 31 .. 25 */
instruction & 0x01ffffff; /* bits 24 .. 0 */
(instruction & 0x01ffffff); /* bits 24 .. 0 */
while(vu0_busy_in_micro_mode())
/* POLICY: never busy in macro mode */
while(vu0_busy())
vu0_issue(sd);
vu0_macro_issue(vu_upper, vu_lower);
/* POLICY: wait for completion of macro-instruction */
while(vu0_busy())
vu0_issue(sd);
}
/* XXX */
/* ... other COP2 instructions ... */
/* ... no other COP2 instructions ... */
else
{
SignalException(ReservedInstruction, instruction);
@ -3381,7 +3417,7 @@ decode_coproc (SIM_DESC sd,
if(! handle)
{
sim_io_eprintf(sd,"COP2 instruction 0x%08X at PC = 0x%s : No handler present\n",
sim_io_eprintf(sd, "COP2 instruction 0x%08X at PC = 0x%s : No handler present\n",
instruction,pr_addr(cia));
}
}

1056
sim/mips/mips.igen
View File

File diff suppressed because it is too large

8
sim/mips/sim-main.h
View File

@ -779,12 +779,16 @@ cop_sw (SD, CPU, cia, coproc_num, coproc_reg)
cop_sd (SD, CPU, cia, coproc_num, coproc_reg)
/* start-sanitize-sky */
void cop_lq PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg, unsigned128 memword));
unsigned128 cop_sq PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg));
#ifdef TARGET_SKY
void cop_lq PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia,
int coproc_num, int coproc_reg, unsigned128 memword));
unsigned128 cop_sq PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia,
int coproc_num, int coproc_reg));
#define COP_LQ(coproc_num,coproc_reg,memword) \
cop_lq (SD, CPU, cia, coproc_num, coproc_reg, memword)
#define COP_SQ(coproc_num,coproc_reg) \
cop_sq (SD, CPU, cia, coproc_num, coproc_reg)
#endif /* TARGET_SKY */
/* end-sanitize-sky */
void decode_coproc PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, unsigned int instruction));

9
sim/mips/sky-pke.c
View File

@ -1089,16 +1089,19 @@ pke_check_stall(struct pke_device* me, enum pke_check_target what)
}
else if(what == chk_path1) /* VU -> GPUIF */
{
ASSERT(me->pke_number == 1);
if(BIT_MASK_GET(gpuif_stat, GPUIF_REG_STAT_APATH_B, GPUIF_REG_STAT_APATH_E) == 1)
any_stall = 1;
}
else if(what == chk_path2) /* PKE -> GPUIF */
{
ASSERT(me->pke_number == 1);
if(BIT_MASK_GET(gpuif_stat, GPUIF_REG_STAT_APATH_B, GPUIF_REG_STAT_APATH_E) == 2)
any_stall = 1;
}
else if(what == chk_path3) /* DMA -> GPUIF */
{
ASSERT(me->pke_number == 1);
if(BIT_MASK_GET(gpuif_stat, GPUIF_REG_STAT_APATH_B, GPUIF_REG_STAT_APATH_E) == 3)
any_stall = 1;
}
@ -1243,12 +1246,12 @@ pke_code_mskpath3(struct pke_device* me, unsigned_4 pkecode)
/* set appropriate bit */
if(BIT_MASK_GET(imm, PKE_REG_MSKPATH3_B, PKE_REG_MSKPATH3_E) != 0)
gif_mode = GIF_REG_MODE_M3R_MASK;
gif_mode = GIF_REG_STAT_M3P;
else
gif_mode = 0;
/* write register; patrickm code will look at M3R bit only */
PKE_MEM_WRITE(me, GIF_REG_MODE, & gif_mode, 4);
/* write register to "read-only" register; gpuif code will look at M3P bit only */
PKE_MEM_WRITE(me, GIF_REG_VIF_M3P, & gif_mode, 4);
/* done */
pke_pc_advance(me, 1);

3
sim/mips/sky-pke.h
View File

@ -45,6 +45,9 @@ typedef unsigned_4 quadword[4];
#define VU1_MEM0_SRCADDR_START 0x21008000
#define VU1_MEM1_SRCADDR_START 0x2100C000
#define VU0_CIA (VU0_REGISTER_WINDOW_START + VU_REG_CIA)
#define VU1_CIA (VU1_REGISTER_WINDOW_START + VU_REG_CIA)
/* GPUIF STAT register */
#define GPUIF_REG_STAT_APATH_E 11
#define GPUIF_REG_STAT_APATH_B 10

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