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sim: d10v: migrate to standard uintXX_t types 

This old port setup its own uintXX types, but since we require C11
now, we can assume the standard uintXX_t types exist and use them.

Also migrate off the sim-specific unsignedXX types.
binutils-2_38-branch
Mike Frysinger 5 years ago
parent
32267d593a
commit
eae126cb7e
4 changed files with 265 additions and 273 deletions
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  1. 44
      sim/d10v/d10v_sim.h
  2. 32
      sim/d10v/endian.c
  3. 66
      sim/d10v/interp.c
  4. 396
      sim/d10v/simops.c

44
sim/d10v/d10v_sim.h
View File

@ -24,16 +24,8 @@ extern int d10v_debug;
#include "sim-config.h"
#include "sim-types.h"
typedef unsigned8 uint8;
typedef unsigned16 uint16;
typedef signed16 int16;
typedef unsigned32 uint32;
typedef signed32 int32;
typedef unsigned64 uint64;
typedef signed64 int64;
/* FIXME: D10V defines */
typedef uint16 reg_t;
typedef uint16_t reg_t;
struct simops
{
@ -222,9 +214,9 @@ enum
struct d10v_memory
{
uint8 *insn[IMEM_SEGMENTS];
uint8 *data[DMEM_SEGMENTS];
uint8 *unif[UMEM_SEGMENTS];
uint8_t *insn[IMEM_SEGMENTS];
uint8_t *data[DMEM_SEGMENTS];
uint8_t *unif[UMEM_SEGMENTS];
};
struct _state
@ -233,8 +225,8 @@ struct _state
#define GPR(N) (State.regs[(N)] + 0)
#define SET_GPR(N,VAL) SLOT_PEND (State.regs[(N)], (VAL))
#define GPR32(N) ((((uint32) State.regs[(N) + 0]) << 16) \
| (uint16) State.regs[(N) + 1])
#define GPR32(N) ((((uint32_t) State.regs[(N) + 0]) << 16) \
| (uint16_t) State.regs[(N) + 1])
#define SET_GPR32(N,VAL) do { SET_GPR (OP[0] + 0, (VAL) >> 16); SET_GPR (OP[0] + 1, (VAL)); } while (0)
reg_t cregs[16]; /* control registers */
@ -246,7 +238,7 @@ struct _state
#define HELD_SP(N) (State.sp[(N)] + 0)
#define SET_HELD_SP(N,VAL) SLOT_PEND (State.sp[(N)], (VAL))
int64 a[2]; /* accumulators */
int64_t a[2]; /* accumulators */
#define ACC(N) (State.a[(N)] + 0)
#define SET_ACC(N,VAL) SLOT_PEND (State.a[(N)], (VAL) & MASK40)
@ -256,10 +248,10 @@ struct _state
/* trace data */
struct {
uint16 psw;
uint16_t psw;
} trace;
uint8 exe;
uint8_t exe;
int pc_changed;
/* NOTE: everything below this line is not reset by
@ -274,7 +266,7 @@ struct _state
extern struct _state State;
extern uint16 OP[4];
extern uint16_t OP[4];
extern struct simops Simops[];
enum
@ -441,8 +433,8 @@ do \
} \
while (0)
extern uint8 *dmem_addr (SIM_DESC, SIM_CPU *, uint16 offset);
extern uint8 *imem_addr (SIM_DESC, SIM_CPU *, uint32);
extern uint8_t *dmem_addr (SIM_DESC, SIM_CPU *, uint16_t offset);
extern uint8_t *imem_addr (SIM_DESC, SIM_CPU *, uint32_t);
#define RB(x) (*(dmem_addr (sd, cpu, x)))
#define SB(addr,data) ( RB(addr) = (data & 0xff))
@ -453,12 +445,12 @@ extern uint8 *imem_addr (SIM_DESC, SIM_CPU *, uint32);
#undef ENDIAN_INLINE
#else
extern uint32 get_longword (uint8 *);
extern uint16 get_word (uint8 *);
extern int64 get_longlong (uint8 *);
extern void write_word (uint8 *addr, uint16 data);
extern void write_longword (uint8 *addr, uint32 data);
extern void write_longlong (uint8 *addr, int64 data);
extern uint32_t get_longword (uint8_t *);
extern uint16_t get_word (uint8_t *);
extern int64_t get_longlong (uint8_t *);
extern void write_word (uint8_t *addr, uint16_t data);
extern void write_longword (uint8_t *addr, uint32_t data);
extern void write_longlong (uint8_t *addr, int64_t data);
#endif
#define SW(addr,data) write_word (dmem_addr (sd, cpu, addr), data)

32
sim/d10v/endian.c
View File

@ -10,35 +10,35 @@
#define ENDIAN_INLINE
#endif
ENDIAN_INLINE uint16
get_word (uint8 *x)
ENDIAN_INLINE uint16_t
get_word (uint8_t *x)
{
return ((uint16)x[0]<<8) + x[1];
return ((uint16_t)x[0]<<8) + x[1];
}
ENDIAN_INLINE uint32
get_longword (uint8 *x)
ENDIAN_INLINE uint32_t
get_longword (uint8_t *x)
{
return ((uint32)x[0]<<24) + ((uint32)x[1]<<16) + ((uint32)x[2]<<8) + ((uint32)x[3]);
return ((uint32_t)x[0]<<24) + ((uint32_t)x[1]<<16) + ((uint32_t)x[2]<<8) + ((uint32_t)x[3]);
}
ENDIAN_INLINE int64
get_longlong (uint8 *x)
ENDIAN_INLINE int64_t
get_longlong (uint8_t *x)
{
uint32 top = get_longword (x);
uint32 bottom = get_longword (x+4);
return (((int64)top)<<32) | (int64)bottom;
uint32_t top = get_longword (x);
uint32_t bottom = get_longword (x+4);
return (((int64_t)top)<<32) | (int64_t)bottom;
}
ENDIAN_INLINE void
write_word (uint8 *addr, uint16 data)
write_word (uint8_t *addr, uint16_t data)
{
addr[0] = (data >> 8) & 0xff;
addr[1] = data & 0xff;
}
ENDIAN_INLINE void
write_longword (uint8 *addr, uint32 data)
write_longword (uint8_t *addr, uint32_t data)
{
addr[0] = (data >> 24) & 0xff;
addr[1] = (data >> 16) & 0xff;
@ -47,8 +47,8 @@ write_longword (uint8 *addr, uint32 data)
}
ENDIAN_INLINE void
write_longlong (uint8 *addr, int64 data)
write_longlong (uint8_t *addr, int64_t data)
{
write_longword (addr, (uint32)(data >> 32));
write_longword (addr+4, (uint32)data);
write_longword (addr, (uint32_t)(data >> 32));
write_longword (addr+4, (uint32_t)data);
}

66
sim/d10v/interp.c
View File

@ -32,23 +32,23 @@ int old_segment_mapping;
unsigned long ins_type_counters[ (int)INS_MAX ];
uint16 OP[4];
uint16_t OP[4];
static long hash (long insn, int format);
static struct hash_entry *lookup_hash (SIM_DESC, SIM_CPU *, uint32 ins, int size);
static void get_operands (struct simops *s, uint32 ins);
static void do_long (SIM_DESC, SIM_CPU *, uint32 ins);
static void do_2_short (SIM_DESC, SIM_CPU *, uint16 ins1, uint16 ins2, enum _leftright leftright);
static void do_parallel (SIM_DESC, SIM_CPU *, uint16 ins1, uint16 ins2);
static struct hash_entry *lookup_hash (SIM_DESC, SIM_CPU *, uint32_t ins, int size);
static void get_operands (struct simops *s, uint32_t ins);
static void do_long (SIM_DESC, SIM_CPU *, uint32_t ins);
static void do_2_short (SIM_DESC, SIM_CPU *, uint16_t ins1, uint16_t ins2, enum _leftright leftright);
static void do_parallel (SIM_DESC, SIM_CPU *, uint16_t ins1, uint16_t ins2);
static char *add_commas (char *buf, int sizeof_buf, unsigned long value);
static INLINE uint8 *map_memory (SIM_DESC, SIM_CPU *, unsigned phys_addr);
static INLINE uint8_t *map_memory (SIM_DESC, SIM_CPU *, unsigned phys_addr);
#define MAX_HASH 63
struct hash_entry
{
struct hash_entry *next;
uint32 opcode;
uint32 mask;
uint32_t opcode;
uint32_t mask;
int size;
struct simops *ops;
};
@ -65,7 +65,7 @@ hash (long insn, int format)
}
INLINE static struct hash_entry *
lookup_hash (SIM_DESC sd, SIM_CPU *cpu, uint32 ins, int size)
lookup_hash (SIM_DESC sd, SIM_CPU *cpu, uint32_t ins, int size)
{
struct hash_entry *h;
@ -84,10 +84,10 @@ lookup_hash (SIM_DESC sd, SIM_CPU *cpu, uint32 ins, int size)
}
INLINE static void
get_operands (struct simops *s, uint32 ins)
get_operands (struct simops *s, uint32_t ins)
{
int i, shift, bits, flags;
uint32 mask;
uint32_t mask;
for (i=0; i < s->numops; i++)
{
shift = s->operands[3*i];
@ -102,7 +102,7 @@ get_operands (struct simops *s, uint32 ins)
}
static void
do_long (SIM_DESC sd, SIM_CPU *cpu, uint32 ins)
do_long (SIM_DESC sd, SIM_CPU *cpu, uint32_t ins)
{
struct hash_entry *h;
#ifdef DEBUG
@ -119,7 +119,7 @@ do_long (SIM_DESC sd, SIM_CPU *cpu, uint32 ins)
}
static void
do_2_short (SIM_DESC sd, SIM_CPU *cpu, uint16 ins1, uint16 ins2, enum _leftright leftright)
do_2_short (SIM_DESC sd, SIM_CPU *cpu, uint16_t ins1, uint16_t ins2, enum _leftright leftright)
{
struct hash_entry *h;
enum _ins_type first, second;
@ -171,7 +171,7 @@ do_2_short (SIM_DESC sd, SIM_CPU *cpu, uint16 ins1, uint16 ins2, enum _leftright
}
static void
do_parallel (SIM_DESC sd, SIM_CPU *cpu, uint16 ins1, uint16 ins2)
do_parallel (SIM_DESC sd, SIM_CPU *cpu, uint16_t ins1, uint16_t ins2)
{
struct hash_entry *h1, *h2;
#ifdef DEBUG
@ -293,7 +293,7 @@ enum
static void
set_dmap_register (SIM_DESC sd, int reg_nr, unsigned long value)
{
uint8 *raw = map_memory (sd, NULL, SIM_D10V_MEMORY_DATA
uint8_t *raw = map_memory (sd, NULL, SIM_D10V_MEMORY_DATA
+ DMAP0_OFFSET + 2 * reg_nr);
WRITE_16 (raw, value);
#ifdef DEBUG
@ -307,7 +307,7 @@ set_dmap_register (SIM_DESC sd, int reg_nr, unsigned long value)
static unsigned long
dmap_register (SIM_DESC sd, SIM_CPU *cpu, void *regcache, int reg_nr)
{
uint8 *raw = map_memory (sd, cpu, SIM_D10V_MEMORY_DATA
uint8_t *raw = map_memory (sd, cpu, SIM_D10V_MEMORY_DATA
+ DMAP0_OFFSET + 2 * reg_nr);
return READ_16 (raw);
}
@ -315,7 +315,7 @@ dmap_register (SIM_DESC sd, SIM_CPU *cpu, void *regcache, int reg_nr)
static void
set_imap_register (SIM_DESC sd, int reg_nr, unsigned long value)
{
uint8 *raw = map_memory (sd, NULL, SIM_D10V_MEMORY_DATA
uint8_t *raw = map_memory (sd, NULL, SIM_D10V_MEMORY_DATA
+ IMAP0_OFFSET + 2 * reg_nr);
WRITE_16 (raw, value);
#ifdef DEBUG
@ -329,7 +329,7 @@ set_imap_register (SIM_DESC sd, int reg_nr, unsigned long value)
static unsigned long
imap_register (SIM_DESC sd, SIM_CPU *cpu, void *regcache, int reg_nr)
{
uint8 *raw = map_memory (sd, cpu, SIM_D10V_MEMORY_DATA
uint8_t *raw = map_memory (sd, cpu, SIM_D10V_MEMORY_DATA
+ IMAP0_OFFSET + 2 * reg_nr);
return READ_16 (raw);
}
@ -597,11 +597,11 @@ sim_d10v_translate_addr (SIM_DESC sd,
is assumed that the client has already ensured that the access
isn't going to cross a segment boundary. */
uint8 *
uint8_t *
map_memory (SIM_DESC sd, SIM_CPU *cpu, unsigned phys_addr)
{
uint8 **memory;
uint8 *raw;
uint8_t **memory;
uint8_t *raw;
unsigned offset;
int segment = ((phys_addr >> 24) & 0xff);
@ -669,7 +669,7 @@ xfer_mem (SIM_DESC sd,
int size,
int write_p)
{
uint8 *memory;
uint8_t *memory;
unsigned long phys;
int phys_size;
phys_size = sim_d10v_translate_addr (sd, NULL, virt, size, &phys, NULL,
@ -866,16 +866,16 @@ sim_open (SIM_OPEN_KIND kind, host_callback *cb,
return sd;
}
uint8 *
dmem_addr (SIM_DESC sd, SIM_CPU *cpu, uint16 offset)
uint8_t *
dmem_addr (SIM_DESC sd, SIM_CPU *cpu, uint16_t offset)
{
unsigned long phys;
uint8 *mem;
uint8_t *mem;
int phys_size;
/* Note: DMEM address range is 0..0x10000. Calling code can compute
things like ``0xfffe + 0x0e60 == 0x10e5d''. Since offset's type
is uint16 this is modulo'ed onto 0x0e5d. */
is uint16_t this is modulo'ed onto 0x0e5d. */
phys_size = sim_d10v_translate_dmap_addr (sd, cpu, offset, 1, &phys, NULL,
dmap_register);
@ -896,11 +896,11 @@ dmem_addr (SIM_DESC sd, SIM_CPU *cpu, uint16 offset)
return mem;
}
uint8 *
imem_addr (SIM_DESC sd, SIM_CPU *cpu, uint32 offset)
uint8_t *
imem_addr (SIM_DESC sd, SIM_CPU *cpu, uint32_t offset)
{
unsigned long phys;
uint8 *mem;
uint8_t *mem;
int phys_size = sim_d10v_translate_imap_addr (sd, cpu, offset, 1, &phys, NULL,
imap_register);
if (phys_size == 0)
@ -923,12 +923,12 @@ imem_addr (SIM_DESC sd, SIM_CPU *cpu, uint32 offset)
static void
step_once (SIM_DESC sd, SIM_CPU *cpu)
{
uint32 inst;
uint8 *iaddr;
uint32_t inst;
uint8_t *iaddr;
/* TODO: Unindent this block. */
{
iaddr = imem_addr (sd, cpu, (uint32)PC << 2);
iaddr = imem_addr (sd, cpu, (uint32_t)PC << 2);
inst = get_longword( iaddr );

396
sim/d10v/simops.c
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