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@ -36,9 +36,21 @@ with this program; if not, write to the Free Software Foundation, Inc., |
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#include "sim-basics.h" |
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#if 0 |
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/* These are generated files. */ |
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#include "itable.h" |
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#include "idecode.h" |
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#include "idecode.h" |
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/* dummy - not used */ |
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typedef instruction_address sim_cia; |
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static const sim_cia null_cia = {0}; /* dummy */ |
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#define NULL_CIA null_cia |
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#else |
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typedef int sim_cia; |
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#define NULL_CIA 0 |
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#endif |
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#include "sim-base.h" |
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@ -78,6 +90,7 @@ typedef unsigned64 uword64; |
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#endif |
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/* Floating-point operations: */ |
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/* FPU registers must be one of the following types. All other values
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@ -114,6 +127,174 @@ unsigned64 SquareRoot PARAMS ((unsigned64 op, FP_formats fmt)); |
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unsigned64 convert PARAMS ((SIM_DESC sd, int rm, unsigned64 op, FP_formats from, FP_formats to)); |
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#define Convert(rm,op,from,to) convert(sd,rm,op,from,to) |
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/* Macro to update FPSR condition-code field. This is complicated by
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the fact that there is a hole in the index range of the bits within |
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the FCSR register. Also, the number of bits visible depends on the |
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MIPS ISA version being supported. */ |
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#define SETFCC(cc,v) {\ |
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int bit = ((cc == 0) ? 23 : (24 + (cc)));\ |
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FCSR = ((FCSR & ~(1 << bit)) | ((v) << bit));\ |
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} |
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#define GETFCC(cc) (((((cc) == 0) ? (FCSR & (1 << 23)) : (FCSR & (1 << (24 + (cc))))) != 0) ? 1 : 0) |
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/* This should be the COC1 value at the start of the preceding
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instruction: */ |
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#define PREVCOC1() ((STATE & simPCOC1) ? 1 : 0) |
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#if 1 |
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#define SizeFGR() (WITH_TARGET_WORD_BITSIZE) |
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#else |
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/* They depend on the CPU being simulated */ |
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#define SizeFGR() ((WITH_TARGET_WORD_BITSIZE == 64 && ((SR & status_FR) == 1)) ? 64 : 32) |
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#endif |
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/* Standard FCRS bits: */ |
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#define IR (0) /* Inexact Result */ |
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#define UF (1) /* UnderFlow */ |
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#define OF (2) /* OverFlow */ |
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#define DZ (3) /* Division by Zero */ |
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#define IO (4) /* Invalid Operation */ |
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#define UO (5) /* Unimplemented Operation */ |
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/* Get masks for individual flags: */ |
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#if 1 /* SAFE version */ |
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#define FP_FLAGS(b) (((unsigned)(b) < 5) ? (1 << ((b) + 2)) : 0) |
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#define FP_ENABLE(b) (((unsigned)(b) < 5) ? (1 << ((b) + 7)) : 0) |
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#define FP_CAUSE(b) (((unsigned)(b) < 6) ? (1 << ((b) + 12)) : 0) |
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#else |
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#define FP_FLAGS(b) (1 << ((b) + 2)) |
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#define FP_ENABLE(b) (1 << ((b) + 7)) |
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#define FP_CAUSE(b) (1 << ((b) + 12)) |
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#endif |
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#define FP_FS (1 << 24) /* MIPS III onwards : Flush to Zero */ |
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#define FP_MASK_RM (0x3) |
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#define FP_SH_RM (0) |
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#define FP_RM_NEAREST (0) /* Round to nearest (Round) */ |
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#define FP_RM_TOZERO (1) /* Round to zero (Trunc) */ |
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#define FP_RM_TOPINF (2) /* Round to Plus infinity (Ceil) */ |
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#define FP_RM_TOMINF (3) /* Round to Minus infinity (Floor) */ |
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#define GETRM() (int)((FCSR >> FP_SH_RM) & FP_MASK_RM) |
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/* Integer ALU operations: */ |
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#include "sim-alu.h" |
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#define ALU32_END(ANS) \ |
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if (ALU32_HAD_OVERFLOW) \ |
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SignalExceptionIntegerOverflow (); \ |
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(ANS) = alu_overflow_val; |
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#define ALU64_END(ANS) \ |
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if (ALU64_HAD_OVERFLOW) \ |
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SignalExceptionIntegerOverflow (); \ |
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(ANS) = alu_val; |
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/* start-sanitize-r5900 */ |
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#define BYTES_IN_MMI_REGS (sizeof(signed_word) + sizeof(signed_word)) |
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#define HALFWORDS_IN_MMI_REGS (BYTES_IN_MMI_REGS/2) |
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#define WORDS_IN_MMI_REGS (BYTES_IN_MMI_REGS/4) |
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#define DOUBLEWORDS_IN_MMI_REGS (BYTES_IN_MMI_REGS/8) |
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#define BYTES_IN_MIPS_REGS (sizeof(signed_word)) |
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#define HALFWORDS_IN_MIPS_REGS (BYTES_IN_MIPS_REGS/2) |
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#define WORDS_IN_MIPS_REGS (BYTES_IN_MIPS_REGS/4) |
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#define DOUBLEWORDS_IN_MIPS_REGS (BYTES_IN_MIPS_REGS/8) |
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/* SUB_REG_FETCH - return as lvalue some sub-part of a "register"
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T - type of the sub part |
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TC - # of T's in the mips part of the "register" |
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I - index (from 0) of desired sub part |
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A - low part of "register" |
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A1 - high part of register |
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*/ |
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#define SUB_REG_FETCH(T,TC,A,A1,I) \ |
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(*(((I) < (TC) ? (T*)(A) : (T*)(A1)) \ |
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+ (CURRENT_HOST_BYTE_ORDER == BIG_ENDIAN \ |
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? ((TC) - 1 - (I) % (TC)) \ |
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: ((I) % (TC)) \ |
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) \ |
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) \ |
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) |
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/*
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GPR_<type>(R,I) - return, as lvalue, the I'th <type> of general register R |
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where <type> has two letters: |
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1 is S=signed or U=unsigned |
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2 is B=byte H=halfword W=word D=doubleword |
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*/ |
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#define SUB_REG_SB(A,A1,I) SUB_REG_FETCH(signed8, BYTES_IN_MIPS_REGS, A, A1, I) |
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#define SUB_REG_SH(A,A1,I) SUB_REG_FETCH(signed16, HALFWORDS_IN_MIPS_REGS, A, A1, I) |
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#define SUB_REG_SW(A,A1,I) SUB_REG_FETCH(signed32, WORDS_IN_MIPS_REGS, A, A1, I) |
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#define SUB_REG_SD(A,A1,I) SUB_REG_FETCH(signed64, DOUBLEWORDS_IN_MIPS_REGS, A, A1, I) |
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#define SUB_REG_UB(A,A1,I) SUB_REG_FETCH(unsigned8, BYTES_IN_MIPS_REGS, A, A1, I) |
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#define SUB_REG_UH(A,A1,I) SUB_REG_FETCH(unsigned16, HALFWORDS_IN_MIPS_REGS, A, A1, I) |
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#define SUB_REG_UW(A,A1,I) SUB_REG_FETCH(unsigned32, WORDS_IN_MIPS_REGS, A, A1, I) |
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#define SUB_REG_UD(A,A1,I) SUB_REG_FETCH(unsigned64, DOUBLEWORDS_IN_MIPS_REGS, A, A1, I) |
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#define GPR_SB(R,I) SUB_REG_SB(®ISTERS[R], ®ISTERS1[R], I) |
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#define GPR_SH(R,I) SUB_REG_SH(®ISTERS[R], ®ISTERS1[R], I) |
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#define GPR_SW(R,I) SUB_REG_SW(®ISTERS[R], ®ISTERS1[R], I) |
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#define GPR_SD(R,I) SUB_REG_SD(®ISTERS[R], ®ISTERS1[R], I) |
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#define GPR_UB(R,I) SUB_REG_UB(®ISTERS[R], ®ISTERS1[R], I) |
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#define GPR_UH(R,I) SUB_REG_UH(®ISTERS[R], ®ISTERS1[R], I) |
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#define GPR_UW(R,I) SUB_REG_UW(®ISTERS[R], ®ISTERS1[R], I) |
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#define GPR_UD(R,I) SUB_REG_UD(®ISTERS[R], ®ISTERS1[R], I) |
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#define RS_SB(I) SUB_REG_SB(&rs_reg, &rs_reg1, I) |
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#define RS_SH(I) SUB_REG_SH(&rs_reg, &rs_reg1, I) |
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#define RS_SW(I) SUB_REG_SW(&rs_reg, &rs_reg1, I) |
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#define RS_SD(I) SUB_REG_SD(&rs_reg, &rs_reg1, I) |
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#define RS_UB(I) SUB_REG_UB(&rs_reg, &rs_reg1, I) |
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#define RS_UH(I) SUB_REG_UH(&rs_reg, &rs_reg1, I) |
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#define RS_UW(I) SUB_REG_UW(&rs_reg, &rs_reg1, I) |
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#define RS_UD(I) SUB_REG_UD(&rs_reg, &rs_reg1, I) |
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#define RT_SB(I) SUB_REG_SB(&rt_reg, &rt_reg1, I) |
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#define RT_SH(I) SUB_REG_SH(&rt_reg, &rt_reg1, I) |
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#define RT_SW(I) SUB_REG_SW(&rt_reg, &rt_reg1, I) |
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#define RT_SD(I) SUB_REG_SD(&rt_reg, &rt_reg1, I) |
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#define RT_UB(I) SUB_REG_UB(&rt_reg, &rt_reg1, I) |
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#define RT_UH(I) SUB_REG_UH(&rt_reg, &rt_reg1, I) |
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#define RT_UW(I) SUB_REG_UW(&rt_reg, &rt_reg1, I) |
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#define RT_UD(I) SUB_REG_UD(&rt_reg, &rt_reg1, I) |
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#define LO_SB(I) SUB_REG_SB(&LO, &LO1, I) |
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#define LO_SH(I) SUB_REG_SH(&LO, &LO1, I) |
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#define LO_SW(I) SUB_REG_SW(&LO, &LO1, I) |
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#define LO_SD(I) SUB_REG_SD(&LO, &LO1, I) |
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#define LO_UB(I) SUB_REG_UB(&LO, &LO1, I) |
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#define LO_UH(I) SUB_REG_UH(&LO, &LO1, I) |
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#define LO_UW(I) SUB_REG_UW(&LO, &LO1, I) |
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#define LO_UD(I) SUB_REG_UD(&LO, &LO1, I) |
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#define HI_SB(I) SUB_REG_SB(&HI, &HI1, I) |
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#define HI_SH(I) SUB_REG_SH(&HI, &HI1, I) |
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#define HI_SW(I) SUB_REG_SW(&HI, &HI1, I) |
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#define HI_SD(I) SUB_REG_SD(&HI, &HI1, I) |
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#define HI_UB(I) SUB_REG_UB(&HI, &HI1, I) |
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#define HI_UH(I) SUB_REG_UH(&HI, &HI1, I) |
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#define HI_UW(I) SUB_REG_UW(&HI, &HI1, I) |
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#define HI_UD(I) SUB_REG_UD(&HI, &HI1, I) |
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/* end-sanitize-r5900 */ |
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@ -121,11 +302,16 @@ struct _sim_cpu { |
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/* The following are internal simulator state variables: */ |
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sim_cia cia; |
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#define CPU_CIA(CPU) ((CPU)->cia) |
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address_word ipc; /* internal Instruction PC */ |
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address_word dspc; /* delay-slot PC */ |
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#define IPC ((STATE_CPU (sd,0))->ipc) |
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#define DSPC ((STATE_CPU (sd,0))->dspc) |
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#define NULLIFY_NIA() { nia.ip = cia.dp + 4; nia.dp = nia.ip += 4; } |
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/* State of the simulator */ |
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unsigned int state; |
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@ -133,6 +319,20 @@ struct _sim_cpu { |
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#define STATE ((STATE_CPU (sd,0))->state) |
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#define DSSTATE ((STATE_CPU (sd,0))->dsstate) |
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/* Flags in the "state" variable: */ |
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#define simHALTEX (1 << 2) /* 0 = run; 1 = halt on exception */ |
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#define simHALTIN (1 << 3) /* 0 = run; 1 = halt on interrupt */ |
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#define simTRACE (1 << 8) /* 0 = do nothing; 1 = trace address activity */ |
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#define simPROFILE (1 << 9) /* 0 = do nothing; 1 = gather profiling samples */ |
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#define simPCOC0 (1 << 17) /* COC[1] from current */ |
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#define simPCOC1 (1 << 18) /* COC[1] from previous */ |
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#define simDELAYSLOT (1 << 24) /* 0 = do nothing; 1 = delay slot entry exists */ |
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#define simSKIPNEXT (1 << 25) /* 0 = do nothing; 1 = skip instruction */ |
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#define simSIGINT (1 << 28) /* 0 = do nothing; 1 = SIGINT has occured */ |
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#define simJALDELAYSLOT (1 << 29) /* 1 = in jal delay slot */ |
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/* This is nasty, since we have to rely on matching the register
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numbers used by GDB. Unfortunately, depending on the MIPS target |
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@ -211,6 +411,22 @@ struct _sim_cpu { |
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#define PENDING_SLOT_REG ((STATE_CPU (sd, 0))->pending_slot_reg) |
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#define PENDING_SLOT_VALUE ((STATE_CPU (sd, 0))->pending_slot_value) |
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/* The following are not used for MIPS IV onwards: */ |
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#define PENDING_FILL(r,v) {\ |
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/* printf("DBG: FILL BEFORE pending_in = %d, pending_out = %d, pending_total = %d\n",PENDING_IN,PENDING_OUT,PENDING_TOTAL); */\ |
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if (PENDING_SLOT_REG[PENDING_IN] != (LAST_EMBED_REGNUM + 1))\ |
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sim_io_eprintf(sd,"Attempt to over-write pending value\n");\ |
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PENDING_SLOT_COUNT[PENDING_IN] = 2;\ |
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PENDING_SLOT_REG[PENDING_IN] = (r);\ |
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PENDING_SLOT_VALUE[PENDING_IN] = (uword64)(v);\ |
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/*printf("DBG: FILL reg %d value = 0x%s\n",(r),pr_addr(v));*/\ |
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PENDING_TOTAL++;\ |
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PENDING_IN++;\ |
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if (PENDING_IN == PSLOTS)\ |
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PENDING_IN = 0;\ |
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/*printf("DBG: FILL AFTER pending_in = %d, pending_out = %d, pending_total = %d\n",PENDING_IN,PENDING_OUT,PENDING_TOTAL);*/\ |
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} |
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/* LLBIT = Load-Linked bit. A bit of "virtual" state used by atomic
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read-write instructions. It is set when a linked load occurs. It |
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@ -318,6 +534,65 @@ struct sim_state { |
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}; |
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/* Status information: */ |
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/* TODO : these should be the bitmasks for these bits within the
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status register. At the moment the following are VR4300 |
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bit-positions: */ |
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#define status_KSU_mask (0x3) /* mask for KSU bits */ |
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#define status_KSU_shift (3) /* shift for field */ |
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#define ksu_kernel (0x0) |
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#define ksu_supervisor (0x1) |
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#define ksu_user (0x2) |
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#define ksu_unknown (0x3) |
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#define status_IE (1 << 0) /* Interrupt enable */ |
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#define status_EXL (1 << 1) /* Exception level */ |
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#define status_RE (1 << 25) /* Reverse Endian in user mode */ |
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#define status_FR (1 << 26) /* enables MIPS III additional FP registers */ |
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#define status_SR (1 << 20) /* soft reset or NMI */ |
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#define status_BEV (1 << 22) /* Location of general exception vectors */ |
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#define status_TS (1 << 21) /* TLB shutdown has occurred */ |
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#define status_ERL (1 << 2) /* Error level */ |
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#define status_RP (1 << 27) /* Reduced Power mode */ |
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#define cause_BD ((unsigned)1 << 31) /* Exception in branch delay slot */ |
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/* NOTE: We keep the following status flags as bit values (1 for true,
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0 for false). This allows them to be used in binary boolean |
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operations without worrying about what exactly the non-zero true |
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value is. */ |
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/* UserMode */ |
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#define UserMode ((((SR & status_KSU_mask) >> status_KSU_shift) == ksu_user) ? 1 : 0) |
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/* BigEndianMem */ |
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/* Hardware configuration. Affects endianness of LoadMemory and
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StoreMemory and the endianness of Kernel and Supervisor mode |
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execution. The value is 0 for little-endian; 1 for big-endian. */ |
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#define BigEndianMem (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN) |
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/*(state & simBE) ? 1 : 0)*/ |
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/* ByteSwapMem */ |
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/* This is true if the host and target have different endianness. */ |
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#define ByteSwapMem (CURRENT_TARGET_BYTE_ORDER != CURRENT_HOST_BYTE_ORDER) |
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/* ReverseEndian */ |
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/* This mode is selected if in User mode with the RE bit being set in
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SR (Status Register). It reverses the endianness of load and store |
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instructions. */ |
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#define ReverseEndian (((SR & status_RE) && UserMode) ? 1 : 0) |
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/* BigEndianCPU */ |
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/* The endianness for load and store instructions (0=little;1=big). In
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User mode this endianness may be switched by setting the state_RE |
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bit in the SR register. Thus, BigEndianCPU may be computed as |
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(BigEndianMem EOR ReverseEndian). */ |
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#define BigEndianCPU (BigEndianMem ^ ReverseEndian) /* Already bits */ |
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/* Exceptions: */ |
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/* NOTE: These numbers depend on the processor architecture being
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@ -369,10 +644,43 @@ uword64 cop_sd PARAMS ((SIM_DESC sd, int coproc_num, int coproc_reg)); |
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#define COP_SW(coproc_num,coproc_reg) cop_sw(sd,coproc_num,coproc_reg) |
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#define COP_SD(coproc_num,coproc_reg) cop_sd(sd,coproc_num,coproc_reg) |
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void decode_coproc PARAMS ((SIM_DESC sd,unsigned int instruction)); |
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#define DecodeCoproc(instruction) decode_coproc(sd, (instruction)) |
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/* Memory accesses */ |
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/* The following are generic to all versions of the MIPS architecture
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to date: */ |
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/* Memory Access Types (for CCA): */ |
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#define Uncached (0) |
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#define CachedNoncoherent (1) |
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#define CachedCoherent (2) |
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#define Cached (3) |
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#define isINSTRUCTION (1 == 0) /* FALSE */ |
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#define isDATA (1 == 1) /* TRUE */ |
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#define isLOAD (1 == 0) /* FALSE */ |
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#define isSTORE (1 == 1) /* TRUE */ |
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#define isREAL (1 == 0) /* FALSE */ |
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#define isRAW (1 == 1) /* TRUE */ |
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#define isTARGET (1 == 0) /* FALSE */ |
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#define isHOST (1 == 1) /* TRUE */ |
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/* The "AccessLength" specifications for Loads and Stores. NOTE: This
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is the number of bytes minus 1. */ |
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#define AccessLength_BYTE (0) |
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#define AccessLength_HALFWORD (1) |
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#define AccessLength_TRIPLEBYTE (2) |
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#define AccessLength_WORD (3) |
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#define AccessLength_QUINTIBYTE (4) |
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#define AccessLength_SEXTIBYTE (5) |
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#define AccessLength_SEPTIBYTE (6) |
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#define AccessLength_DOUBLEWORD (7) |
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#define AccessLength_QUADWORD (15) |
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int address_translation PARAMS ((SIM_DESC sd, uword64 vAddr, int IorD, int LorS, uword64 *pAddr, int *CCA, int host, int raw)); |
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#define AddressTranslation(vAddr,IorD,LorS,pAddr,CCA,host,raw) \ |
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address_translation(sd, vAddr,IorD,LorS,pAddr,CCA,host,raw) |
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@ -388,4 +696,13 @@ store_memory(sd,CCA,AccessLength,MemElem,MemElem1,pAddr,vAddr,raw) |
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void cache_op PARAMS ((SIM_DESC sd, int op, uword64 pAddr, uword64 vAddr, unsigned int instruction)); |
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#define CacheOp(op,pAddr,vAddr,instruction) cache_op(sd,op,pAddr,vAddr,instruction) |
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void sync_operation PARAMS ((SIM_DESC sd, int stype)); |
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#define SyncOperation(stype) sync_operation (sd, (stype)) |
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void prefetch PARAMS ((SIM_DESC sd, int CCA, uword64 pAddr, uword64 vAddr, int DATA, int hint)); |
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#define Prefetch(CCA,pAddr,vAddr,DATA,hint) prefetch(sd,CCA,pAddr,vAddr,DATA,hint) |
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#define IMEM(CIA) 0 /* FIXME */ |
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#endif |
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Andrew Cagney
29 years ago