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include/opcode/ 

* aarch64.h (AARCH64_FEATURE_CRC): New macro.

opcodes/

	* aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
	(aarch64_feature_crc): New static.
	(CRC): New macro.
	(aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w,
	crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions.
	* aarch64-asm-2.c: Re-generate.
	* aarch64-dis-2.c: Ditto.
	* aarch64-opc-2.c: Ditto.

gas/

	* config/tc-aarch64.c (aarch64_features): Add the 'crc' option.

gas/testsuite/

	* gas/aarch64/crc32.s: New test.
	* gas/aarch64/crc32.d: Ditto.
gdb_7_6-branch
Yufeng Zhang 14 years ago
parent
86a3263fff
commit
e60bb1dd35
12 changed files with 575 additions and 390 deletions
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  1. 4
      gas/ChangeLog
  2. 1
      gas/config/tc-aarch64.c
  3. 5
      gas/testsuite/ChangeLog
  4. 16
      gas/testsuite/gas/aarch64/crc32.d
  5. 31
      gas/testsuite/gas/aarch64/crc32.s
  6. 4
      include/opcode/ChangeLog
  7. 1
      include/opcode/aarch64.h
  8. 11
      opcodes/ChangeLog
  9. 134
      opcodes/aarch64-asm-2.c
  10. 668
      opcodes/aarch64-dis-2.c
  11. 66
      opcodes/aarch64-opc-2.c
  12. 24
      opcodes/aarch64-tbl.h

4
gas/ChangeLog
View File

@ -1,3 +1,7 @@
2013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
* config/tc-aarch64.c (aarch64_features): Add the 'crc' option.
2013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
* config/tc-aarch64.c (parse_sys_reg): Allow the full range of CRn

1
gas/config/tc-aarch64.c
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@ -6991,6 +6991,7 @@ struct aarch64_option_cpu_value_table
};
static const struct aarch64_option_cpu_value_table aarch64_features[] = {
{"crc", AARCH64_FEATURE (AARCH64_FEATURE_CRC, 0)},
{"crypto", AARCH64_FEATURE (AARCH64_FEATURE_CRYPTO, 0)},
{"fp", AARCH64_FEATURE (AARCH64_FEATURE_FP, 0)},
{"simd", AARCH64_FEATURE (AARCH64_FEATURE_SIMD, 0)},

5
gas/testsuite/ChangeLog
View File

@ -1,3 +1,8 @@
2013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
* gas/aarch64/crc32.s: New test.
* gas/aarch64/crc32.d: Ditto.
2013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
* gas/aarch64/illegal.l: Delete the error message for

16
gas/testsuite/gas/aarch64/crc32.d
View File

@ -0,0 +1,16 @@
#objdump: -dr
#as: -march=armv8-a+crc
.*: file format .*
Disassembly of section \.text:
0000000000000000 <.*>:
0: 1acf40e3 crc32b w3, w7, w15
4: 1ac345e7 crc32h w7, w15, w3
8: 1ac7486f crc32w w15, w3, w7
c: 9acf4ce3 crc32x w3, w7, x15
10: 1acf50e3 crc32cb w3, w7, w15
14: 1ac355e7 crc32ch w7, w15, w3
18: 1ac7586f crc32cw w15, w3, w7
1c: 9acf5ce3 crc32cx w3, w7, x15

31
gas/testsuite/gas/aarch64/crc32.s
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@ -0,0 +1,31 @@
/* crc32.s Test file for AArch64 CRC-32 and CRC-32C checksum instructions.
Copyright 2013 Free Software Foundation, Inc.
Contributed by ARM Ltd.
This file is part of GAS.
GAS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the license, or
(at your option) any later version.
GAS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; see the file COPYING3. If not,
see <http://www.gnu.org/licenses/>. */
.text
crc32b w3, w7, w15
crc32h w7, w15, w3
crc32w w15, w3, w7
crc32x w3, w7, x15
crc32cb w3, w7, w15
crc32ch w7, w15, w3
crc32cw w15, w3, w7
crc32cx w3, w7, x15

4
include/opcode/ChangeLog
View File

@ -1,3 +1,7 @@
2013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
* aarch64.h (AARCH64_FEATURE_CRC): New macro.
2013-02-06 Sandra Loosemore <sandra@codesourcery.com>
Andrew Jenner <andrew@codesourcery.com>

1
include/opcode/aarch64.h
View File

@ -37,6 +37,7 @@ typedef uint32_t aarch64_insn;
#define AARCH64_FEATURE_CRYPTO 0x00010000 /* Crypto instructions. */
#define AARCH64_FEATURE_FP 0x00020000 /* FP instructions. */
#define AARCH64_FEATURE_SIMD 0x00040000 /* SIMD instructions. */
#define AARCH64_FEATURE_CRC 0x00080000 /* CRC instructions. */
/* Architectures are the sum of the base and extensions. */
#define AARCH64_ARCH_V8 AARCH64_FEATURE (AARCH64_FEATURE_V8, \

11
opcodes/ChangeLog
View File

@ -1,3 +1,14 @@
2013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
* aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
(aarch64_feature_crc): New static.
(CRC): New macro.
(aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w,
crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions.
* aarch64-asm-2.c: Re-generate.
* aarch64-dis-2.c: Ditto.
* aarch64-opc-2.c: Ditto.
2013-02-27 Alan Modra <amodra@gmail.com>
* rl78-decode.opc (rl78_decode_opcode): Fix typo.

134
opcodes/aarch64-asm-2.c
View File

@ -134,101 +134,101 @@ aarch64_find_real_opcode (const aarch64_opcode *opcode)
case 563: /* ror */
value = 562; /* --> rorv. */
break;
case 565: /* mul */
value = 564; /* --> madd. */
case 573: /* mul */
value = 572; /* --> madd. */
break;
case 567: /* mneg */
value = 566; /* --> msub. */
case 575: /* mneg */
value = 574; /* --> msub. */
break;
case 569: /* smull */
value = 568; /* --> smaddl. */
case 577: /* smull */
value = 576; /* --> smaddl. */
break;
case 571: /* smnegl */
value = 570; /* --> smsubl. */
case 579: /* smnegl */
value = 578; /* --> smsubl. */
break;
case 574: /* umull */
value = 573; /* --> umaddl. */
case 582: /* umull */
value = 581; /* --> umaddl. */
break;
case 576: /* umnegl */
value = 575; /* --> umsubl. */
case 584: /* umnegl */
value = 583; /* --> umsubl. */
break;
case 587: /* ror */
value = 586; /* --> extr. */
case 595: /* ror */
value = 594; /* --> extr. */
break;
case 687: /* strb */
value = 685; /* --> sturb. */
case 695: /* strb */
value = 693; /* --> sturb. */
break;
case 688: /* ldrb */
value = 686; /* --> ldurb. */
case 696: /* ldrb */
value = 694; /* --> ldurb. */
break;
case 690: /* ldrsb */
value = 689; /* --> ldursb. */
case 698: /* ldrsb */
value = 697; /* --> ldursb. */
break;
case 693: /* str */
value = 691; /* --> stur. */
case 701: /* str */
value = 699; /* --> stur. */
break;
case 694: /* ldr */
value = 692; /* --> ldur. */
case 702: /* ldr */
value = 700; /* --> ldur. */
break;
case 697: /* strh */
value = 695; /* --> sturh. */
case 705: /* strh */
value = 703; /* --> sturh. */
break;
case 698: /* ldrh */
value = 696; /* --> ldurh. */
case 706: /* ldrh */
value = 704; /* --> ldurh. */
break;
case 700: /* ldrsh */
value = 699; /* --> ldursh. */
case 708: /* ldrsh */
value = 707; /* --> ldursh. */
break;
case 703: /* str */
value = 701; /* --> stur. */
case 711: /* str */
value = 709; /* --> stur. */
break;
case 704: /* ldr */
value = 702; /* --> ldur. */
case 712: /* ldr */
value = 710; /* --> ldur. */
break;
case 706: /* ldrsw */
value = 705; /* --> ldursw. */
case 714: /* ldrsw */
value = 713; /* --> ldursw. */
break;
case 708: /* prfm */
value = 707; /* --> prfum. */
case 716: /* prfm */
value = 715; /* --> prfum. */
break;
case 750: /* bic */
value = 749; /* --> and. */
case 758: /* bic */
value = 757; /* --> and. */
break;
case 752: /* mov */
value = 751; /* --> orr. */
case 760: /* mov */
value = 759; /* --> orr. */
break;
case 755: /* tst */
value = 754; /* --> ands. */
case 763: /* tst */
value = 762; /* --> ands. */
break;
case 760: /* uxtw */
case 759: /* mov */
value = 758; /* --> orr. */
case 768: /* uxtw */
case 767: /* mov */
value = 766; /* --> orr. */
break;
case 762: /* mvn */
value = 761; /* --> orn. */
case 770: /* mvn */
value = 769; /* --> orn. */
break;
case 766: /* tst */
value = 765; /* --> ands. */
case 774: /* tst */
value = 773; /* --> ands. */
break;
case 769: /* mov */
value = 768; /* --> movn. */
case 777: /* mov */
value = 776; /* --> movn. */
break;
case 771: /* mov */
value = 770; /* --> movz. */
case 779: /* mov */
value = 778; /* --> movz. */
break;
case 782: /* sevl */
case 781: /* sev */
case 780: /* wfi */
case 779: /* wfe */
case 778: /* yield */
case 777: /* nop */
value = 776; /* --> hint. */
case 790: /* sevl */
case 789: /* sev */
case 788: /* wfi */
case 787: /* wfe */
case 786: /* yield */
case 785: /* nop */
value = 784; /* --> hint. */
break;
case 791: /* tlbi */
case 790: /* ic */
case 789: /* dc */
case 788: /* at */
value = 787; /* --> sys. */
case 799: /* tlbi */
case 798: /* ic */
case 797: /* dc */
case 796: /* at */
value = 795; /* --> sys. */
break;
default: return NULL;
}

668
opcodes/aarch64-dis-2.c
View File

File diff suppressed because it is too large

66
opcodes/aarch64-opc-2.c
View File

@ -119,48 +119,48 @@ const struct aarch64_operand aarch64_operands[] =
static const unsigned op_enum_table [] =
{
0,
652,
653,
654,
657,
658,
659,
660,
661,
655,
656,
662,
665,
666,
667,
668,
669,
663,
685,
686,
689,
695,
696,
699,
701,
702,
691,
692,
705,
664,
670,
671,
693,
694,
697,
703,
704,
707,
745,
746,
747,
748,
709,
710,
699,
700,
713,
715,
753,
754,
755,
756,
12,
510,
511,
768,
770,
772,
752,
771,
769,
776,
778,
780,
760,
779,
777,
259,
499,
509,
508,
750,
758,
505,
502,
495,
@ -169,19 +169,19 @@ static const unsigned op_enum_table [] =
504,
506,
507,
760,
768,
526,
529,
532,
527,
530,
618,
626,
160,
161,
162,
163,
420,
587,
595,
314,
316,
336,

24
opcodes/aarch64-tbl.h
View File

@ -163,12 +163,24 @@
QLF2(X,X), \
}
/* e.g. CRC32B <Wd>, <Wn>, <Wm>. */
#define QL_I3SAMEW \
{ \
QLF3(W,W,W), \
}
/* e.g. SMULH <Xd>, <Xn>, <Xm>. */
#define QL_I3SAMEX \
{ \
QLF3(X,X,X), \
}
/* e.g. CRC32X <Wd>, <Wn>, <Xm>. */
#define QL_I3WWX \
{ \
QLF3(W,W,X), \
}
/* e.g. UDIV <Xd>, <Xn>, <Xm>. */
#define QL_I3SAMER \
{ \
@ -1199,11 +1211,14 @@ static const aarch64_feature_set aarch64_feature_simd =
AARCH64_FEATURE (AARCH64_FEATURE_SIMD, 0);
static const aarch64_feature_set aarch64_feature_crypto =
AARCH64_FEATURE (AARCH64_FEATURE_CRYPTO, 0);
static const aarch64_feature_set aarch64_feature_crc =
AARCH64_FEATURE (AARCH64_FEATURE_CRC, 0);
#define CORE &aarch64_feature_v8
#define FP &aarch64_feature_fp
#define SIMD &aarch64_feature_simd
#define CRYPTO &aarch64_feature_crypto
#define CRC &aarch64_feature_crc
struct aarch64_opcode aarch64_opcode_table[] =
{
@ -1810,6 +1825,15 @@ struct aarch64_opcode aarch64_opcode_table[] =
{"asr", 0x1ac02800, 0x7fe0fc00, dp_2src, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF | F_ALIAS},
{"rorv", 0x1ac02c00, 0x7fe0fc00, dp_2src, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF | F_HAS_ALIAS},
{"ror", 0x1ac02c00, 0x7fe0fc00, dp_2src, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF | F_ALIAS},
/* CRC instructions. */
{"crc32b", 0x1ac04000, 0xffe0fc00, dp_2src, 0, CRC, OP3 (Rd, Rn, Rm), QL_I3SAMEW, 0},
{"crc32h", 0x1ac04400, 0xffe0fc00, dp_2src, 0, CRC, OP3 (Rd, Rn, Rm), QL_I3SAMEW, 0},
{"crc32w", 0x1ac04800, 0xffe0fc00, dp_2src, 0, CRC, OP3 (Rd, Rn, Rm), QL_I3SAMEW, 0},
{"crc32x", 0x9ac04c00, 0xffe0fc00, dp_2src, 0, CRC, OP3 (Rd, Rn, Rm), QL_I3WWX, 0},
{"crc32cb", 0x1ac05000, 0xffe0fc00, dp_2src, 0, CRC, OP3 (Rd, Rn, Rm), QL_I3SAMEW, 0},
{"crc32ch", 0x1ac05400, 0xffe0fc00, dp_2src, 0, CRC, OP3 (Rd, Rn, Rm), QL_I3SAMEW, 0},
{"crc32cw", 0x1ac05800, 0xffe0fc00, dp_2src, 0, CRC, OP3 (Rd, Rn, Rm), QL_I3SAMEW, 0},
{"crc32cx", 0x9ac05c00, 0xffe0fc00, dp_2src, 0, CRC, OP3 (Rd, Rn, Rm), QL_I3WWX, 0},
/* Data-processing (3 source). */
{"madd", 0x1b000000, 0x7fe08000, dp_3src, 0, CORE, OP4 (Rd, Rn, Rm, Ra), QL_I4SAMER, F_HAS_ALIAS | F_SF},
{"mul", 0x1b007c00, 0x7fe0fc00, dp_3src, 0, CORE, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_ALIAS | F_SF},

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