* mips-dis.c (print_insn_mips): Remove OPCODE_IS_MEMBER's gp32

argument.
	* mips-opc.c (G6): Undefine.
	(mips_builtin_opcodes): Remove gp32 entry for "move".  Add macro
	as the first "move" alternative.

opcodes/ChangeLog

@@ -1,3 +1,11 @@
+2001-08-10  Richard Sandiford  <rsandifo@redhat.com>
+
+	* mips-dis.c (print_insn_mips): Remove OPCODE_IS_MEMBER's gp32
+	argument.
+	* mips-opc.c (G6): Undefine.
+	(mips_builtin_opcodes): Remove gp32 entry for "move".  Add macro
+	as the first "move" alternative.
+
 2001-08-10  Andreas Jaeger  <aj@suse.de>
 
 	* configure.in: Add -Wstrict-prototypes and -Wmissing-prototypes

opcodes/mips-dis.c

@@ -469,7 +469,7 @@ print_insn_mips (memaddr, word, info)
 	    {
 	      register const char *d;
 
-	      if (! OPCODE_IS_MEMBER (op, mips_isa, target_processor, 0))
+	      if (! OPCODE_IS_MEMBER (op, mips_isa, target_processor))
 		continue;
 
 	      (*info->fprintf_func) (info->stream, "%s", op->name);

opcodes/mips-opc.c

@@ -96,8 +96,6 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  *
 #define G3 (I4             \
             )
 
-#define G6      INSN_GP32
-
 /* The order of overloaded instructions matters.  Label arguments and
    register arguments look the same. Instructions that can have either
    for arguments must apear in the correct order in this table for the
@@ -121,7 +119,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"li",      "t,j",      0x24000000, 0xffe00000, WR_t,			I1	}, /* addiu */
 {"li",	    "t,i",	0x34000000, 0xffe00000, WR_t,			I1	}, /* ori */
 {"li",      "t,I",	0,    (int) M_LI,	INSN_MACRO,		I1	},
-{"move",    "d,s",	0x00000025, 0xfc1f07ff,	WR_d|RD_s,		I1|G6	},/* or */
+{"move",    "d,s",	0,    (int) M_MOVE,	INSN_MACRO,		I1	},
 {"move",    "d,s",	0x0000002d, 0xfc1f07ff, WR_d|RD_s,		I3	},/* daddu */
 {"move",    "d,s",	0x00000021, 0xfc1f07ff, WR_d|RD_s,		I1	},/* addu */
 {"move",    "d,s",	0x00000025, 0xfc1f07ff,	WR_d|RD_s,		I1	},/* or */