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cpu,gas,opcodes: remove no longer needed workaround from the BPF port 

cpu/ChangeLog:

2020-06-02  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* bpf.cpu (define-bpf-isa): Set base-insn-bitsize to 64.
	* bpf.opc (bpf_print_insn): Do not set endian_code here.

gas/ChangeLog:

2020-06-04  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* config/tc-bpf.c (md_begin): Pass CGEN_CPU_OPEN_INSN_ENDIAN to
	bpf_cgen_cpu_open.
	(md_assemble): Remove no longer needed hack.

opcodes/ChangeLog:

2020-06-04  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* disassemble.c (disassemble_init_for_target): Set endian_code for
	bpf targets.
	* bpf-desc.c: Regenerate.
	* bpf-opc.c: Likewise.
	* bpf-dis.c: Likewise.
binutils-2_35-branch
Jose E. Marchesi 6 years ago
parent
e9bffec9af
commit
d8740be159
10 changed files with 51 additions and 39 deletions
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  1. 5
      cpu/ChangeLog
  2. 10
      cpu/bpf.cpu
  3. 1
      cpu/bpf.opc
  4. 6
      gas/ChangeLog
  5. 6
      gas/config/tc-bpf.c
  6. 8
      opcodes/ChangeLog
  7. 4
      opcodes/bpf-desc.c
  8. 1
      opcodes/bpf-dis.c
  9. 48
      opcodes/bpf-opc.c
  10. 1
      opcodes/disassemble.c

5
cpu/ChangeLog
View File

@ -1,3 +1,8 @@
2020-06-02 Jose E. Marchesi <jose.marchesi@oracle.com>
* bpf.cpu (define-bpf-isa): Set base-insn-bitsize to 64.
* bpf.opc (bpf_print_insn): Do not set endian_code here.
2020-06-02 Jose E. Marchesi <jose.marchesi@oracle.com>
* mep.opc (print_slot_insn): Pass the insn endianness to

10
cpu/bpf.cpu
View File

@ -98,13 +98,9 @@
;; Length of an unknown instruction. Used by disassembly and by the
;; simulator's invalid insn handler.
(default-insn-bitsize 64)
;; Number of bits of insn that can be initially fetched. XXX this
;; should be 64 (the size of the smallest insn) but until CGEN
;; gets fixed to place constant fields in their own words, we have
;; to use this workaround to avoid the opcode byte to be placed at
;; the wrong side of the instruction when assembling in
;; big-endian.
(base-insn-bitsize 8)))
;; Number of bits of insn that can be initially fetched. This is
;; the size of the smallest insn.
(base-insn-bitsize 64)))
(define-bpf-isa le)
(define-bpf-isa be)

1
cpu/bpf.opc
View File

@ -129,7 +129,6 @@ bpf_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
info->bytes_per_chunk = 1;
info->bytes_per_line = 8;
info->endian_code = BFD_ENDIAN_BIG;
/* Attempt to read the base part of the insn. */
buflen = cd->base_insn_bitsize / 8;

6
gas/ChangeLog
View File

@ -1,3 +1,9 @@
2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com>
* config/tc-bpf.c (md_begin): Pass CGEN_CPU_OPEN_INSN_ENDIAN to
bpf_cgen_cpu_open.
(md_assemble): Remove no longer needed hack.
2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com>
* cgen.c (gas_cgen_finish_insn): Pass the endianness to

6
gas/config/tc-bpf.c
View File

@ -174,6 +174,8 @@ md_begin (void)
gas_cgen_cpu_desc = bpf_cgen_cpu_open (CGEN_CPU_OPEN_ENDIAN,
target_big_endian ?
CGEN_ENDIAN_BIG : CGEN_ENDIAN_LITTLE,
CGEN_CPU_OPEN_INSN_ENDIAN,
CGEN_ENDIAN_LITTLE,
CGEN_CPU_OPEN_ISAS,
bpf_isa,
CGEN_CPU_OPEN_END);
@ -354,10 +356,6 @@ md_assemble (char *str)
CGEN_INSN_INT buffer[CGEN_MAX_INSN_SIZE / sizeof (CGEN_INT_INSN_P)];
#else
unsigned char buffer[CGEN_MAX_INSN_SIZE];
memset (buffer, 0, CGEN_MAX_INSN_SIZE); /* XXX to remove when CGEN
is fixed to handle
opcodes-in-words
properly. */
#endif
gas_cgen_init_parse ();

8
opcodes/ChangeLog
View File

@ -1,3 +1,11 @@
2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com>
* disassemble.c (disassemble_init_for_target): Set endian_code for
bpf targets.
* bpf-desc.c: Regenerate.
* bpf-opc.c: Likewise.
* bpf-dis.c: Likewise.
2020-06-03 Jose E. Marchesi <jose.marchesi@oracle.com>
* cgen-opc.c (cgen_get_insn_value): Get an `endian' argument.

4
opcodes/bpf-desc.c
View File

@ -119,8 +119,8 @@ const CGEN_ATTR_TABLE bpf_cgen_insn_attr_table[] =
/* Instruction set variants. */
static const CGEN_ISA bpf_cgen_isa_table[] = {
{ "ebpfle", 64, 8, 64, 128 },
{ "ebpfbe", 64, 8, 64, 128 },
{ "ebpfle", 64, 64, 64, 128 },
{ "ebpfbe", 64, 64, 64, 128 },
{ 0, 0, 0, 0, 0 }
};

1
opcodes/bpf-dis.c
View File

@ -75,7 +75,6 @@ bpf_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
info->bytes_per_chunk = 1;
info->bytes_per_line = 8;
info->endian_code = BFD_ENDIAN_BIG;
/* Attempt to read the base part of the insn. */
buflen = cd->base_insn_bitsize / 8;

48
opcodes/bpf-opc.c
View File

@ -50,99 +50,99 @@ static const CGEN_IFMT ifmt_empty ATTRIBUTE_UNUSED = {
};
static const CGEN_IFMT ifmt_addile ATTRIBUTE_UNUSED = {
8, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_CODE) }, { F (F_DSTLE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_CODE) }, { F (F_DSTLE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
};
static const CGEN_IFMT ifmt_addrle ATTRIBUTE_UNUSED = {
8, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_CODE) }, { F (F_DSTLE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_CODE) }, { F (F_DSTLE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
};
static const CGEN_IFMT ifmt_negle ATTRIBUTE_UNUSED = {
8, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_CODE) }, { F (F_DSTLE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_CODE) }, { F (F_DSTLE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
};
static const CGEN_IFMT ifmt_addibe ATTRIBUTE_UNUSED = {
8, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_CODE) }, { F (F_SRCBE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_CODE) }, { F (F_SRCBE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
};
static const CGEN_IFMT ifmt_addrbe ATTRIBUTE_UNUSED = {
8, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_CODE) }, { F (F_SRCBE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_CODE) }, { F (F_SRCBE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
};
static const CGEN_IFMT ifmt_negbe ATTRIBUTE_UNUSED = {
8, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_CODE) }, { F (F_SRCBE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_CODE) }, { F (F_SRCBE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
};
static const CGEN_IFMT ifmt_endlele ATTRIBUTE_UNUSED = {
8, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_CODE) }, { F (F_DSTLE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_CODE) }, { F (F_DSTLE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
};
static const CGEN_IFMT ifmt_endlebe ATTRIBUTE_UNUSED = {
8, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_CODE) }, { F (F_SRCBE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_CODE) }, { F (F_SRCBE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
};
static const CGEN_IFMT ifmt_lddwle ATTRIBUTE_UNUSED = {
8, 128, 0xff, { { F (F_IMM64) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_DSTLE) }, { F (F_OP_CLASS) }, { 0 } }
64, 128, 0xff, { { F (F_IMM64) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_DSTLE) }, { F (F_OP_CLASS) }, { 0 } }
};
static const CGEN_IFMT ifmt_lddwbe ATTRIBUTE_UNUSED = {
8, 128, 0xff, { { F (F_IMM64) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_SRCBE) }, { F (F_OP_CLASS) }, { 0 } }
64, 128, 0xff, { { F (F_IMM64) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_SRCBE) }, { F (F_OP_CLASS) }, { 0 } }
};
static const CGEN_IFMT ifmt_ldabsw ATTRIBUTE_UNUSED = {
8, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_REGS) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_OP_CLASS) }, { 0 } }
64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_REGS) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_OP_CLASS) }, { 0 } }
};
static const CGEN_IFMT ifmt_ldindwle ATTRIBUTE_UNUSED = {
8, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_DSTLE) }, { F (F_OP_CLASS) }, { 0 } }
64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_DSTLE) }, { F (F_OP_CLASS) }, { 0 } }
};
static const CGEN_IFMT ifmt_ldindwbe ATTRIBUTE_UNUSED = {
8, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_SRCBE) }, { F (F_OP_CLASS) }, { 0 } }
64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_SRCBE) }, { F (F_OP_CLASS) }, { 0 } }
};
static const CGEN_IFMT ifmt_ldxwle ATTRIBUTE_UNUSED = {
8, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_DSTLE) }, { F (F_OP_CLASS) }, { 0 } }
64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_DSTLE) }, { F (F_OP_CLASS) }, { 0 } }
};
static const CGEN_IFMT ifmt_ldxwbe ATTRIBUTE_UNUSED = {
8, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_SRCBE) }, { F (F_OP_CLASS) }, { 0 } }
64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_SRCBE) }, { F (F_OP_CLASS) }, { 0 } }
};
static const CGEN_IFMT ifmt_stble ATTRIBUTE_UNUSED = {
8, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_DSTLE) }, { F (F_OP_CLASS) }, { 0 } }
64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_DSTLE) }, { F (F_OP_CLASS) }, { 0 } }
};
static const CGEN_IFMT ifmt_stbbe ATTRIBUTE_UNUSED = {
8, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_SRCBE) }, { F (F_OP_CLASS) }, { 0 } }
64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_SRCBE) }, { F (F_OP_CLASS) }, { 0 } }
};
static const CGEN_IFMT ifmt_jeqile ATTRIBUTE_UNUSED = {
8, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_CODE) }, { F (F_DSTLE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_CODE) }, { F (F_DSTLE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
};
static const CGEN_IFMT ifmt_jeqrle ATTRIBUTE_UNUSED = {
8, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_CODE) }, { F (F_DSTLE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_CODE) }, { F (F_DSTLE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
};
static const CGEN_IFMT ifmt_jeqibe ATTRIBUTE_UNUSED = {
8, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_CODE) }, { F (F_SRCBE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_CODE) }, { F (F_SRCBE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
};
static const CGEN_IFMT ifmt_jeqrbe ATTRIBUTE_UNUSED = {
8, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_CODE) }, { F (F_SRCBE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_CODE) }, { F (F_SRCBE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
};
static const CGEN_IFMT ifmt_callle ATTRIBUTE_UNUSED = {
8, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_REGS) }, { F (F_OP_CODE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_REGS) }, { F (F_OP_CODE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
};
static const CGEN_IFMT ifmt_ja ATTRIBUTE_UNUSED = {
8, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_REGS) }, { F (F_OP_CODE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_REGS) }, { F (F_OP_CODE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
};
static const CGEN_IFMT ifmt_exit ATTRIBUTE_UNUSED = {
8, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_REGS) }, { F (F_OP_CODE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
64, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_REGS) }, { F (F_OP_CODE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
};
#undef F

1
opcodes/disassemble.c
View File

@ -660,6 +660,7 @@ disassemble_init_for_target (struct disassemble_info * info)
#endif
#ifdef ARCH_bpf
case bfd_arch_bpf:
info->endian_code = BFD_ENDIAN_LITTLE;
if (!info->private_data)
{
info->private_data = cgen_bitset_create (ISA_EBPFMAX);

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