riscv
/
binutils-gdb
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity
Browse Source

Add support for relaxation of bit manipulation instructions.

cagney_bigcore-20040122-branch
Nick Clifton 23 years ago
parent
a94154757c
commit
ca9a79a174
11 changed files with 277 additions and 25 deletions
Whitespace
Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL
Split View
Diff Options
Show Stats Download Patch File Download Diff File
  1. 27
      bfd/coff-h8300.c
  2. 52
      bfd/elf32-h8300.c
  3. 5
      gas/ChangeLog
  4. 22
      gas/config/tc-h8300.c
  5. 4
      include/opcode/ChangeLog
  6. 4
      include/opcode/h8300.h
  7. 9
      ld/testsuite/ChangeLog
  8. 4
      ld/testsuite/ld-h8300/h8300.exp
  9. 52
      ld/testsuite/ld-h8300/relax-4-coff.d
  10. 51
      ld/testsuite/ld-h8300/relax-4.d
  11. 72
      ld/testsuite/ld-h8300/relax-4.s

27
bfd/coff-h8300.c
View File

@ -1,6 +1,6 @@
/* BFD back-end for Renesas H8/300 COFF binaries.
Copyright 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
2000, 2001, 2002, 2003
2000, 2001, 2002, 2003, 2004
Free Software Foundation, Inc.
Written by Steve Chamberlain, <sac@cygnus.com>.
@ -666,6 +666,7 @@ h8300_reloc16_extra_cases (bfd *abfd, struct bfd_link_info *link_info,
bfd_vma value;
bfd_vma dot;
int gap, tmp;
unsigned char temp_code;
switch (reloc->howto->type)
{
@ -947,8 +948,12 @@ h8300_reloc16_extra_cases (bfd *abfd, struct bfd_link_info *link_info,
if (data[dst_address - 2] != 0x6a)
abort ();
temp_code = data[src_address - 1];
if ((temp_code & 0x10) != 0x10)
temp_code &= 0xf0;
/* Fix up the opcode. */
switch (data[src_address - 1] & 0xf0)
switch (temp_code)
{
case 0x00:
data[dst_address - 2] = (data[src_address - 1] & 0xf) | 0x20;
@ -956,6 +961,12 @@ h8300_reloc16_extra_cases (bfd *abfd, struct bfd_link_info *link_info,
case 0x80:
data[dst_address - 2] = (data[src_address - 1] & 0xf) | 0x30;
break;
case 0x18:
data[dst_address - 2] = 0x7f;
break;
case 0x10:
data[dst_address - 2] = 0x7e;
break;
default:
abort ();
}
@ -972,8 +983,12 @@ h8300_reloc16_extra_cases (bfd *abfd, struct bfd_link_info *link_info,
if (data[dst_address - 2] != 0x6a)
abort ();
temp_code = data[src_address - 1];
if ((temp_code & 0x30) != 0x30)
temp_code &= 0xf0;
/* Fix up the opcode. */
switch (data[src_address - 1] & 0xf0)
switch (temp_code)
{
case 0x20:
data[dst_address - 2] = (data[src_address - 1] & 0xf) | 0x20;
@ -981,6 +996,12 @@ h8300_reloc16_extra_cases (bfd *abfd, struct bfd_link_info *link_info,
case 0xa0:
data[dst_address - 2] = (data[src_address - 1] & 0xf) | 0x30;
break;
case 0x38:
data[dst_address - 2] = 0x7f;
break;
case 0x30:
data[dst_address - 2] = 0x7e;
break;
default:
abort ();
}

52
bfd/elf32-h8300.c
View File

@ -1010,6 +1010,7 @@ elf32_h8_relax_section (bfd *abfd, asection *sec,
if (value >= 0xffffff00u)
{
unsigned char code;
unsigned char temp_code;
/* Note that we've changed the relocs, section contents,
etc. */
@ -1024,18 +1025,29 @@ elf32_h8_relax_section (bfd *abfd, asection *sec,
if (code != 0x6a)
abort ();
code = bfd_get_8 (abfd, contents + irel->r_offset - 1);
temp_code = code = bfd_get_8 (abfd, contents + irel->r_offset - 1);
if ((temp_code & 0x10) != 0x10)
temp_code &= 0xf0;
if ((code & 0xf0) == 0x00)
bfd_put_8 (abfd,
(code & 0xf) | 0x20,
contents + irel->r_offset - 2);
else if ((code & 0xf0) == 0x80)
bfd_put_8 (abfd,
(code & 0xf) | 0x30,
contents + irel->r_offset - 2);
else
abort ();
switch (temp_code)
{
case 0x00:
bfd_put_8 (abfd, (code & 0xf) | 0x20,
contents + irel->r_offset - 2);
break;
case 0x80:
bfd_put_8 (abfd, (code & 0xf) | 0x30,
contents + irel->r_offset - 2);
break;
case 0x18:
bfd_put_8 (abfd, 0x7f, contents + irel->r_offset - 2);
break;
case 0x10:
bfd_put_8 (abfd, 0x7e, contents + irel->r_offset - 2);
break;
default:
abort ();
}
/* Fix the relocation's type. */
irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info),
@ -1066,6 +1078,7 @@ elf32_h8_relax_section (bfd *abfd, asection *sec,
if (value >= 0xffffff00u)
{
unsigned char code;
unsigned char temp_code;
/* Note that we've changed the relocs, section contents,
etc. */
@ -1080,9 +1093,12 @@ elf32_h8_relax_section (bfd *abfd, asection *sec,
if (code != 0x6a)
abort ();
code = bfd_get_8 (abfd, contents + irel->r_offset - 1);
temp_code = code = bfd_get_8 (abfd, contents + irel->r_offset - 1);
if ((temp_code & 0x30) != 0x30)
temp_code &= 0xf0;
switch (code & 0xf0)
switch (temp_code)
{
case 0x20:
bfd_put_8 (abfd, (code & 0xf) | 0x20,
@ -1092,8 +1108,14 @@ elf32_h8_relax_section (bfd *abfd, asection *sec,
bfd_put_8 (abfd, (code & 0xf) | 0x30,
contents + irel->r_offset - 2);
break;
case 0x38:
bfd_put_8 (abfd, 0x7f, contents + irel->r_offset - 2);
break;
case 0x30:
bfd_put_8 (abfd, 0x7e, contents + irel->r_offset - 2);
break;
default:
abort ();
abort();
}
/* Fix the relocation's type. */
@ -1113,7 +1135,7 @@ elf32_h8_relax_section (bfd *abfd, asection *sec,
}
}
/* FALLTHRU */
/* Fall through. */
/* This is a 24/32bit absolute address in a "mov" insn, which may
become a 16-bit absolute address if it is in the right range. */

5
gas/ChangeLog
View File

@ -1,3 +1,8 @@
2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
* config/tc-h8300.c (build_bytes): Apply relaxation to bit
manipulation insns.
2004-01-12 Richard Sandiford <rsandifo@redhat.com>
* config/tc-mips.c (macro_build_jalr): When adding an R_MIPS_JALR

22
gas/config/tc-h8300.c
View File

@ -1,6 +1,6 @@
/* tc-h8300.c -- Assemble code for the Renesas H8/300
Copyright 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 2000,
2001, 2002, 2003 Free Software Foundation, Inc.
2001, 2002, 2003, 2004 Free Software Foundation, Inc.
This file is part of GAS, the GNU Assembler.
@ -1578,9 +1578,23 @@ build_bytes (const struct h8_instruction *this_try, struct h8_op *operand)
for (i = 0; i < this_try->length; i++)
output[i] = (asnibbles[i * 2] << 4) | asnibbles[i * 2 + 1];
/* Note if this is a movb instruction -- there's a special relaxation
which only applies to them. */
if (this_try->opcode->how == O (O_MOV, SB))
/* Note if this is a movb or a bit manipulation instruction
there is a special relaxation which only applies. */
if ( this_try->opcode->how == O (O_MOV, SB)
|| this_try->opcode->how == O (O_BCLR, SB)
|| this_try->opcode->how == O (O_BAND, SB)
|| this_try->opcode->how == O (O_BIAND, SB)
|| this_try->opcode->how == O (O_BILD, SB)
|| this_try->opcode->how == O (O_BIOR, SB)
|| this_try->opcode->how == O (O_BIST, SB)
|| this_try->opcode->how == O (O_BIXOR, SB)
|| this_try->opcode->how == O (O_BLD, SB)
|| this_try->opcode->how == O (O_BNOT, SB)
|| this_try->opcode->how == O (O_BOR, SB)
|| this_try->opcode->how == O (O_BSET, SB)
|| this_try->opcode->how == O (O_BST, SB)
|| this_try->opcode->how == O (O_BTST, SB)
|| this_try->opcode->how == O (O_BXOR, SB))
movb = 1;
/* Output any fixes. */

4
include/opcode/ChangeLog
View File

@ -1,3 +1,7 @@
2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
* h8300.h (BITOP): Pass MEMRELAX flag.
2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
* h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32

4
include/opcode/h8300.h
View File

@ -895,8 +895,8 @@ struct h8_opcode
{code, AV_H8, 2, name, {{imm, RD8, E}}, {{op00, op01, imm, RD8, E}}}, \
{code, AV_H8, 6, name, {{imm, RDIND, E}}, {{op10, op11, B30 | RDIND, 0, op00, op01, imm, 0, E}}}, \
{code, AV_H8, 6, name, {{imm, ABS8DST, E}}, {{op20, op21, DSTABS8LIST, op00, op01, imm, 0, E}}}, \
{code, AV_H8S, 6, name, {{imm, ABS16DST, E}}, {{0x6, 0xa, 0x1, op30, DST | ABS16LIST, op00, op01, imm, op4, E}}}, \
{code, AV_H8S, 6, name, {{imm, ABS32DST, E}}, {{0x6, 0xa, 0x3, op30, DST | ABS32LIST, op00, op01, imm, op4, E}}}
{code, AV_H8S, 6, name, {{imm, ABS16DST, E}}, {{0x6, 0xa, 0x1, op30, DST | MEMRELAX | ABS16LIST , op00, op01, imm, op4, E}}}, \
{code, AV_H8S, 6, name, {{imm, ABS32DST, E}}, {{0x6, 0xa, 0x3, op30, DST | MEMRELAX | ABS32LIST , op00, op01, imm, op4, E}}}
#define BITOP_B(code, imm, name, op00, op01, op10, op11, op20, op21, op30, op4) \
{code, AV_H8SX, 0, name, {{imm, RDIND, E}}, {{op10, op11, B30 | RDIND, 0, op00, op01, imm, op4, E}}}, \

9
ld/testsuite/ChangeLog
View File

@ -1,3 +1,12 @@
2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
* ld-h8300/h8300-exp: Run the relax-4 test.
* ld-h8300/relax-4.s: New file: Source for relax-4 test.
* ld-h8300/relax-4.d: New file: Expected output and commands for
assembling and linking the relax-4 test.
* ld-h8300/relax-4-coff.d: New file: Variant for the COFF based
toolchain.
2004-01-09 H.J. Lu <hongjiu.lu@intel.com>
* ld-selective/selective.exp: Skip ia64-*-*.

4
ld/testsuite/ld-h8300/h8300.exp
View File

@ -1,5 +1,5 @@
# Expect script for ld-h8300 tests
# Copyright 2002, 2003 Free Software Foundation, Inc.
# Copyright 2002, 2003, 2004 Free Software Foundation, Inc.
#
# This file is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
@ -29,6 +29,8 @@ run_dump_test relax
if {[istarget *-elf]} {
run_dump_test relax-2
run_dump_test relax-3
run_dump_test relax-4
} else {
run_dump_test relax-3-coff
run_dump_test relax-4-coff
}

52
ld/testsuite/ld-h8300/relax-4-coff.d
View File

@ -0,0 +1,52 @@
# name: H8300 Relaxation Test 4
# source: relax-4.s
# ld: --relax -m h8300s
# objdump: -d --no-show-raw-insn
.*: file format .*-h8300
Disassembly of section .text:
00000100 <_start>:
100: f8 03 mov.b #0x3,r0l
102: fa 05 mov.b #0x5,r2l
104: 7f ff 60 80 bset r0l,@0xff:8
108: 7f 00 60 a0 bset r2l,@0x0:8
10c: 7e ff 63 a0 btst r2l,@0xff:8
110: 7e 00 63 80 btst r0l,@0x0:8
114: 6a 18 00 00 70 50 bset #0x5,@0x0:16
11a: 6a 18 7f ff 70 50 bset #0x5,@0x7fff:16
120: 6a 18 80 00 70 50 bset #0x5,@0x8000:16
126: 6a 18 fe ff 70 50 bset #0x5,@0xfeff:16
12c: 7f 00 70 50 bset #0x5,@0x0:8
130: 7f ff 70 50 bset #0x5,@0xff:8
134: 6a 10 00 00 76 50 band #0x5,@0x0:16
13a: 6a 10 7f ff 76 50 band #0x5,@0x7fff:16
140: 6a 10 80 00 76 50 band #0x5,@0x8000:16
146: 6a 10 fe ff 76 50 band #0x5,@0xfeff:16
14c: 7e 00 76 50 band #0x5,@0x0:8
150: 7e ff 76 50 band #0x5,@0xff:8
154: 7f ff 60 a0 bset r2l,@0xff:8
158: 7f 00 60 80 bset r0l,@0x0:8
15c: 7e ff 63 80 btst r0l,@0xff:8
160: 7e 00 63 a0 btst r2l,@0x0:8
164: 6a 18 00 00 70 60 bset #0x6,@0x0:16
16a: 6a 18 7f ff 70 60 bset #0x6,@0x7fff:16
170: 6a 38 00 00 80 00 70 60 bset #0x6,@0x8000:32
178: 6a 38 00 00 ff 00 70 60 bset #0x6,@0xff00:32
180: 6a 38 00 ff ff 00 70 60 bset #0x6,@0xffff00:32
188: 6a 38 ff ff 7f ff 70 60 bset #0x6,@0xffff7fff:32
190: 6a 18 80 00 70 60 bset #0x6,@0x8000:16
196: 6a 18 fe ff 70 60 bset #0x6,@0xfeff:16
19c: 7f 00 70 60 bset #0x6,@0x0:8
1a0: 7f ff 70 60 bset #0x6,@0xff:8
1a4: 6a 10 00 00 76 60 band #0x6,@0x0:16
1aa: 6a 10 7f ff 76 60 band #0x6,@0x7fff:16
1b0: 6a 30 00 00 80 00 76 60 band #0x6,@0x8000:32
1b8: 6a 30 00 00 ff 00 76 60 band #0x6,@0xff00:32
1c0: 6a 30 00 ff ff 00 76 60 band #0x6,@0xffff00:32
1c8: 6a 30 ff ff 7f ff 76 60 band #0x6,@0xffff7fff:32
1d0: 6a 10 80 00 76 60 band #0x6,@0x8000:16
1d6: 6a 10 fe ff 76 60 band #0x6,@0xfeff:16
1dc: 7e 00 76 60 band #0x6,@0x0:8
1e0: 7e ff 76 60 band #0x6,@0xff:8

51
ld/testsuite/ld-h8300/relax-4.d
View File

@ -0,0 +1,51 @@
# name: H8300 Relaxation Test 4
# ld: --relax -m h8300self
# objdump: -d --no-show-raw-insn
.*: file format .*-h8300
Disassembly of section .text:
00000100 <_start>:
100: f8 03 mov.b #0x3,r0l
102: fa 05 mov.b #0x5,r2l
104: 7f ff 60 80 bset r0l,@0xff:8
108: 7f 00 60 a0 bset r2l,@0x0:8
10c: 7e ff 63 a0 btst r2l,@0xff:8
110: 7e 00 63 80 btst r0l,@0x0:8
114: 6a 18 00 00 70 50 bset #0x5,@0x0:16
11a: 6a 18 7f ff 70 50 bset #0x5,@0x7fff:16
120: 6a 18 80 00 70 50 bset #0x5,@0x8000:16
126: 6a 18 fe ff 70 50 bset #0x5,@0xfeff:16
12c: 7f 00 70 50 bset #0x5,@0x0:8
130: 7f ff 70 50 bset #0x5,@0xff:8
134: 6a 10 00 00 76 50 band #0x5,@0x0:16
13a: 6a 10 7f ff 76 50 band #0x5,@0x7fff:16
140: 6a 10 80 00 76 50 band #0x5,@0x8000:16
146: 6a 10 fe ff 76 50 band #0x5,@0xfeff:16
14c: 7e 00 76 50 band #0x5,@0x0:8
150: 7e ff 76 50 band #0x5,@0xff:8
154: 7f ff 60 a0 bset r2l,@0xff:8
158: 7f 00 60 80 bset r0l,@0x0:8
15c: 7e ff 63 80 btst r0l,@0xff:8
160: 7e 00 63 a0 btst r2l,@0x0:8
164: 6a 18 00 00 70 60 bset #0x6,@0x0:16
16a: 6a 18 7f ff 70 60 bset #0x6,@0x7fff:16
170: 6a 38 00 00 80 00 70 60 bset #0x6,@0x8000:32
178: 6a 38 00 00 ff 00 70 60 bset #0x6,@0xff00:32
180: 6a 38 00 ff ff 00 70 60 bset #0x6,@0xffff00:32
188: 6a 38 ff ff 7f ff 70 60 bset #0x6,@0xffff7fff:32
190: 6a 18 80 00 70 60 bset #0x6,@0x8000:16
196: 6a 18 fe ff 70 60 bset #0x6,@0xfeff:16
19c: 7f 00 70 60 bset #0x6,@0x0:8
1a0: 7f ff 70 60 bset #0x6,@0xff:8
1a4: 6a 10 00 00 76 60 band #0x6,@0x0:16
1aa: 6a 10 7f ff 76 60 band #0x6,@0x7fff:16
1b0: 6a 30 00 00 80 00 76 60 band #0x6,@0x8000:32
1b8: 6a 30 00 00 ff 00 76 60 band #0x6,@0xff00:32
1c0: 6a 30 00 ff ff 00 76 60 band #0x6,@0xffff00:32
1c8: 6a 30 ff ff 7f ff 76 60 band #0x6,@0xffff7fff:32
1d0: 6a 10 80 00 76 60 band #0x6,@0x8000:16
1d6: 6a 10 fe ff 76 60 band #0x6,@0xfeff:16
1dc: 7e 00 76 60 band #0x6,@0x0:8
1e0: 7e ff 76 60 band #0x6,@0xff:8

72
ld/testsuite/ld-h8300/relax-4.s
View File

@ -0,0 +1,72 @@
; Relaxation is possible for following bit manipulation instructions
; BAND, BCLR, BIAND, BILD, BIOR, BIST, BIXOR, BLD, BNOT, BOR, BSET, BST, BTST, BXOR
.h8300s
.globl _start
_start:
# s3-s6 aren't valid 16-bit addresses.
mov.b #0x3,r0l
mov.b #0x5,r2l
;
; Relaxation of aa:16
;
bset r0l,@s10:16
bset r2l,@s9:16
btst r2l,@s10:16
btst r0l,@s9:16
bset #5,@s1:16
bset #5,@s2:16
bset #5,@s7:16
bset #5,@s8:16
bset #5,@s9:16
bset #5,@s10:16
band #5,@s1:16
band #5,@s2:16
band #5,@s7:16
band #5,@s8:16
band #5,@s9:16
band #5,@s10:16
;
; Relaxation of aa:32
;
bset r2l,@s10:32
bset r0l,@s9:32
btst r0l,@s10:32
btst r2l,@s9:32
bset #6,@s1:32
bset #6,@s2:32
bset #6,@s3:32
bset #6,@s4:32
bset #6,@s5:32
bset #6,@s6:32
bset #6,@s7:32
bset #6,@s8:32
bset #6,@s9:32
bset #6,@s10:32
band #6,@s1:32
band #6,@s2:32
band #6,@s3:32
band #6,@s4:32
band #6,@s5:32
band #6,@s6:32
band #6,@s7:32
band #6,@s8:32
band #6,@s9:32
band #6,@s10:32
.equ s1,0
.equ s2,0x7fff
.equ s3,0x8000
.equ s4,0xff00
.equ s5,0xffff00
.equ s6,0xffff7fff
.equ s7,0xffff8000
.equ s8,0xfffffeff
.equ s9,0xffffff00
.equ s10,0xffffffff
.end
Write Preview
Loading…
Cancel
Save