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Enhance the AARCH64 assembler to support LDFF1xx instructions which use REG+REG addressing with an assumed offset register. 

PR 22988
opcode	* opcode/aarch64.h (enum aarch64_opnd): Add
	AARCH64_OPND_SVE_ADDR_R.

opcodes	* aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
	instructions with only a base address register.
	* aarch64-opc.c (operand_general_constraint_met_p): Add code to
	handle AARHC64_OPND_SVE_ADDR_R.
	(aarch64_print_operand): Likewise.
	* aarch64-asm-2.c: Regenerate.
	* aarch64_dis-2.c: Regenerate.
	* aarch64-opc-2.c: Regenerate.

gas	* config/tc-aarch64.c (parse_operands): Add code to handle
	AARCH64_OPN_SVE_ADDR_R.
	* testsuite/gas/aarch64/sve.s: Add tests for LDFF1xx instructions
	with an assumed XZR offset address register.
	* testsuite/gas/aarch64/sve.d: Update expected disassembly.
binutils-2_31-branch
Nick Clifton 9 years ago
parent
9c75b45645
commit
c8d59609b1
12 changed files with 720 additions and 571 deletions
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  1. 9
      gas/ChangeLog
  2. 20
      gas/config/tc-aarch64.c
  3. 15
      gas/testsuite/gas/aarch64/sve.d
  4. 23
      gas/testsuite/gas/aarch64/sve.s
  5. 6
      include/ChangeLog
  6. 1
      include/opcode/aarch64.h
  7. 12
      opcodes/ChangeLog
  8. 113
      opcodes/aarch64-asm-2.c
  9. 1063
      opcodes/aarch64-dis-2.c
  10. 1
      opcodes/aarch64-opc-2.c
  11. 2
      opcodes/aarch64-opc.c
  12. 26
      opcodes/aarch64-tbl.h

9
gas/ChangeLog
View File

@ -1,3 +1,12 @@
2018-03-28 Nick Clifton <nickc@redhat.com>
PR 22988
* config/tc-aarch64.c (parse_operands): Add code to handle
AARCH64_OPN_SVE_ADDR_R.
* testsuite/gas/aarch64/sve.s: Add tests for LDFF1xx instructions
with an assumed XZR offset address register.
* testsuite/gas/aarch64/sve.d: Update expected disassembly.
2018-03-22 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (check_VecOperands): Latch

20
gas/config/tc-aarch64.c
View File

@ -3695,6 +3695,7 @@ parse_address_main (char **str, aarch64_opnd_info *operand,
set_syntax_error (_("missing offset in the pre-indexed address"));
return FALSE;
}
operand->addr.preind = 1;
inst.reloc.exp.X_op = O_constant;
inst.reloc.exp.X_add_number = 0;
@ -6233,6 +6234,25 @@ parse_operands (char *str, const aarch64_opcode *opcode)
info->addr.offset.imm = inst.reloc.exp.X_add_number;
break;
case AARCH64_OPND_SVE_ADDR_R:
/* [<Xn|SP>{, <R><m>}]
but recognizing SVE registers. */
po_misc_or_fail (parse_sve_address (&str, info, &base_qualifier,
&offset_qualifier));
if (offset_qualifier == AARCH64_OPND_QLF_NIL)
{
offset_qualifier = AARCH64_OPND_QLF_X;
info->addr.offset.is_reg = 1;
info->addr.offset.regno = 31;
}
else if (base_qualifier != AARCH64_OPND_QLF_X
|| offset_qualifier != AARCH64_OPND_QLF_X)
{
set_syntax_error (_("invalid addressing mode"));
goto failure;
}
goto regoff_addr;
case AARCH64_OPND_SVE_ADDR_RR:
case AARCH64_OPND_SVE_ADDR_RR_LSL1:
case AARCH64_OPND_SVE_ADDR_RR_LSL2:

15
gas/testsuite/gas/aarch64/sve.d
View File

@ -40562,3 +40562,18 @@ Disassembly of section .*:
.*: 0e431441 fadd v1\.4h, v2\.4h, v3\.4h
.*: 4e401400 fadd v0\.8h, v0\.8h, v0\.8h
.*: 4e431441 fadd v1\.8h, v2\.8h, v3\.8h
.*: a41f6400 ldff1b \{z0\.b\}, p1/z, \[x0, xzr\]
.*: a43f6420 ldff1b \{z0\.h\}, p1/z, \[x1, xzr\]
.*: a45f6440 ldff1b \{z0\.s\}, p1/z, \[x2, xzr\]
.*: a47f6460 ldff1b \{z0\.d\}, p1/z, \[x3, xzr\]
.*: a5ff6000 ldff1d \{z0\.d\}, p0/z, \[x0, xzr, lsl #3\]
.*: a4bf6520 ldff1h \{z0\.h\}, p1/z, \[x9, xzr, lsl #1\]
.*: a4df6540 ldff1h \{z0\.s\}, p1/z, \[x10, xzr, lsl #1\]
.*: a4ff6560 ldff1h \{z0\.d\}, p1/z, \[x11, xzr, lsl #1\]
.*: a5bf65c0 ldff1sb \{z0\.s\}, p1/z, \[x14, xzr\]
.*: a59f65e0 ldff1sb \{z0\.d\}, p1/z, \[x15, xzr\]
.*: a53f6640 ldff1sh \{z0\.s\}, p1/z, \[x18, xzr, lsl #1\]
.*: a51f6660 ldff1sh \{z0\.d\}, p1/z, \[x19, xzr, lsl #1\]
.*: a49f66e0 ldff1sw \{z0\.d\}, p1/z, \[x23, xzr, lsl #2\]
.*: a57f6760 ldff1w \{z0\.d\}, p1/z, \[x27, xzr, lsl #2\]

23
gas/testsuite/gas/aarch64/sve.s
View File

@ -40540,3 +40540,26 @@
ORN Z0.D, Z0.D, #0X1
.include "advsimd-compnum.s"
# PR 22988 - check that [Rn] is equivalent to [Rn,xzr]
ldff1b z0.b, p1/z, [x0]
ldff1b z0.h, p1/z, [x1]
ldff1b z0.s, p1/z, [x2]
ldff1b z0.d, p1/z, [x3]
ldff1d z0.d, p0/z, [x0]
ldff1h z0.h, p1/z, [x9]
ldff1h z0.s, p1/z, [x10]
ldff1h z0.d, p1/z, [x11]
ldff1sb z0.s, p1/z, [x14]
ldff1sb z0.d, p1/z, [x15]
ldff1sh z0.s, p1/z, [x18]
ldff1sh z0.d, p1/z, [x19]
ldff1sw z0.d, p1/z, [x23]
ldff1w z0.d, p1/z, [x27]

6
include/ChangeLog
View File

@ -1,3 +1,9 @@
2018-03-28 Nick Clifton <nickc@redhat.com>
PR 22988
* opcode/aarch64.h (enum aarch64_opnd): Add
AARCH64_OPND_SVE_ADDR_R.
2018-03-21 H.J. Lu <hongjiu.lu@intel.com>
* elf/common.h (DF_1_KMOD): New.

1
include/opcode/aarch64.h
View File

@ -272,6 +272,7 @@ enum aarch64_opnd
AARCH64_OPND_SVE_ADDR_RI_U6x2, /* SVE [<Xn|SP>, #<uimm6>*2]. */
AARCH64_OPND_SVE_ADDR_RI_U6x4, /* SVE [<Xn|SP>, #<uimm6>*4]. */
AARCH64_OPND_SVE_ADDR_RI_U6x8, /* SVE [<Xn|SP>, #<uimm6>*8]. */
AARCH64_OPND_SVE_ADDR_R, /* SVE [<Xn|SP>]. */
AARCH64_OPND_SVE_ADDR_RR, /* SVE [<Xn|SP>, <Xm|XZR>]. */
AARCH64_OPND_SVE_ADDR_RR_LSL1, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #1]. */
AARCH64_OPND_SVE_ADDR_RR_LSL2, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #2]. */

12
opcodes/ChangeLog
View File

@ -1,3 +1,15 @@
2018-03-28 Nick Clifton <nickc@redhat.com>
PR 22988
* aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
instructions with only a base address register.
* aarch64-opc.c (operand_general_constraint_met_p): Add code to
handle AARHC64_OPND_SVE_ADDR_R.
(aarch64_print_operand): Likewise.
* aarch64-asm-2.c: Regenerate.
* aarch64_dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
2018-03-22 Jan Beulich <jbeulich@suse.com>
* i386-opc.tbl: Drop VecESize from register only insn forms and

113
opcodes/aarch64-asm-2.c
View File

@ -454,7 +454,7 @@ aarch64_find_real_opcode (const aarch64_opcode *opcode)
case 1177: /* sys */
value = 1177; /* --> sys. */
break;
case 1974: /* bic */
case 1990: /* bic */
case 1240: /* and */
value = 1240; /* --> and. */
break;
@ -466,19 +466,19 @@ aarch64_find_real_opcode (const aarch64_opcode *opcode)
case 1243: /* ands */
value = 1243; /* --> ands. */
break;
case 1975: /* cmple */
case 1991: /* cmple */
case 1278: /* cmpge */
value = 1278; /* --> cmpge. */
break;
case 1978: /* cmplt */
case 1994: /* cmplt */
case 1281: /* cmpgt */
value = 1281; /* --> cmpgt. */
break;
case 1976: /* cmplo */
case 1992: /* cmplo */
case 1283: /* cmphi */
value = 1283; /* --> cmphi. */
break;
case 1977: /* cmpls */
case 1993: /* cmpls */
case 1286: /* cmphs */
value = 1286; /* --> cmphs. */
break;
@ -490,7 +490,7 @@ aarch64_find_real_opcode (const aarch64_opcode *opcode)
case 1309: /* cpy */
value = 1309; /* --> cpy. */
break;
case 1985: /* fmov */
case 2001: /* fmov */
case 1225: /* mov */
case 1310: /* cpy */
value = 1310; /* --> cpy. */
@ -504,7 +504,7 @@ aarch64_find_real_opcode (const aarch64_opcode *opcode)
case 1323: /* dup */
value = 1323; /* --> dup. */
break;
case 1984: /* fmov */
case 2000: /* fmov */
case 1219: /* mov */
case 1324: /* dup */
value = 1324; /* --> dup. */
@ -513,7 +513,7 @@ aarch64_find_real_opcode (const aarch64_opcode *opcode)
case 1325: /* dupm */
value = 1325; /* --> dupm. */
break;
case 1979: /* eon */
case 1995: /* eon */
case 1327: /* eor */
value = 1327; /* --> eor. */
break;
@ -525,19 +525,19 @@ aarch64_find_real_opcode (const aarch64_opcode *opcode)
case 1330: /* eors */
value = 1330; /* --> eors. */
break;
case 1980: /* facle */
case 1996: /* facle */
case 1335: /* facge */
value = 1335; /* --> facge. */
break;
case 1981: /* faclt */
case 1997: /* faclt */
case 1336: /* facgt */
value = 1336; /* --> facgt. */
break;
case 1982: /* fcmle */
case 1998: /* fcmle */
case 1349: /* fcmge */
value = 1349; /* --> fcmge. */
break;
case 1983: /* fcmlt */
case 1999: /* fcmlt */
case 1351: /* fcmgt */
value = 1351; /* --> fcmgt. */
break;
@ -550,28 +550,28 @@ aarch64_find_real_opcode (const aarch64_opcode *opcode)
value = 1380; /* --> fdup. */
break;
case 1213: /* mov */
case 1695: /* orr */
value = 1695; /* --> orr. */
case 1711: /* orr */
value = 1711; /* --> orr. */
break;
case 1986: /* orn */
case 1696: /* orr */
value = 1696; /* --> orr. */
case 2002: /* orn */
case 1712: /* orr */
value = 1712; /* --> orr. */
break;
case 1216: /* mov */
case 1698: /* orr */
value = 1698; /* --> orr. */
case 1714: /* orr */
value = 1714; /* --> orr. */
break;
case 1226: /* movs */
case 1699: /* orrs */
value = 1699; /* --> orrs. */
case 1715: /* orrs */
value = 1715; /* --> orrs. */
break;
case 1221: /* mov */
case 1761: /* sel */
value = 1761; /* --> sel. */
case 1777: /* sel */
value = 1777; /* --> sel. */
break;
case 1224: /* mov */
case 1762: /* sel */
value = 1762; /* --> sel. */
case 1778: /* sel */
value = 1778; /* --> sel. */
break;
default: return NULL;
}
@ -613,7 +613,6 @@ aarch64_insert_operand (const aarch64_operand *self,
case 27:
case 28:
case 29:
case 151:
case 152:
case 153:
case 154:
@ -623,7 +622,7 @@ aarch64_insert_operand (const aarch64_operand *self,
case 158:
case 159:
case 160:
case 173:
case 161:
case 174:
case 175:
case 176:
@ -632,8 +631,9 @@ aarch64_insert_operand (const aarch64_operand *self,
case 179:
case 180:
case 181:
case 185:
case 188:
case 182:
case 186:
case 189:
return aarch64_ins_regno (self, info, code, inst);
case 13:
return aarch64_ins_reg_extended (self, info, code, inst);
@ -644,7 +644,7 @@ aarch64_insert_operand (const aarch64_operand *self,
case 30:
case 31:
case 32:
case 190:
case 191:
return aarch64_ins_reglane (self, info, code, inst);
case 33:
return aarch64_ins_reglist (self, info, code, inst);
@ -676,9 +676,8 @@ aarch64_insert_operand (const aarch64_operand *self,
case 76:
case 77:
case 78:
case 148:
case 150:
case 165:
case 149:
case 151:
case 166:
case 167:
case 168:
@ -686,6 +685,7 @@ aarch64_insert_operand (const aarch64_operand *self,
case 170:
case 171:
case 172:
case 173:
return aarch64_ins_imm (self, info, code, inst);
case 41:
case 42:
@ -695,10 +695,10 @@ aarch64_insert_operand (const aarch64_operand *self,
case 45:
return aarch64_ins_advsimd_imm_modified (self, info, code, inst);
case 49:
case 139:
case 140:
return aarch64_ins_fpimm (self, info, code, inst);
case 64:
case 146:
case 147:
return aarch64_ins_limm (self, info, code, inst);
case 65:
return aarch64_ins_aimm (self, info, code, inst);
@ -708,10 +708,10 @@ aarch64_insert_operand (const aarch64_operand *self,
return aarch64_ins_fbits (self, info, code, inst);
case 69:
case 70:
case 144:
case 145:
return aarch64_ins_imm_rotate2 (self, info, code, inst);
case 71:
case 143:
case 144:
return aarch64_ins_imm_rotate1 (self, info, code, inst);
case 72:
case 73:
@ -777,8 +777,8 @@ aarch64_insert_operand (const aarch64_operand *self,
case 119:
case 120:
case 121:
return aarch64_ins_sve_addr_rr_lsl (self, info, code, inst);
case 122:
return aarch64_ins_sve_addr_rr_lsl (self, info, code, inst);
case 123:
case 124:
case 125:
@ -786,48 +786,49 @@ aarch64_insert_operand (const aarch64_operand *self,
case 127:
case 128:
case 129:
return aarch64_ins_sve_addr_rz_xtw (self, info, code, inst);
case 130:
return aarch64_ins_sve_addr_rz_xtw (self, info, code, inst);
case 131:
case 132:
case 133:
return aarch64_ins_sve_addr_zi_u5 (self, info, code, inst);
case 134:
return aarch64_ins_sve_addr_zz_lsl (self, info, code, inst);
return aarch64_ins_sve_addr_zi_u5 (self, info, code, inst);
case 135:
return aarch64_ins_sve_addr_zz_sxtw (self, info, code, inst);
return aarch64_ins_sve_addr_zz_lsl (self, info, code, inst);
case 136:
return aarch64_ins_sve_addr_zz_uxtw (self, info, code, inst);
return aarch64_ins_sve_addr_zz_sxtw (self, info, code, inst);
case 137:
return aarch64_ins_sve_aimm (self, info, code, inst);
return aarch64_ins_sve_addr_zz_uxtw (self, info, code, inst);
case 138:
return aarch64_ins_sve_aimm (self, info, code, inst);
case 139:
return aarch64_ins_sve_asimm (self, info, code, inst);
case 140:
return aarch64_ins_sve_float_half_one (self, info, code, inst);
case 141:
return aarch64_ins_sve_float_half_two (self, info, code, inst);
return aarch64_ins_sve_float_half_one (self, info, code, inst);
case 142:
return aarch64_ins_sve_float_half_two (self, info, code, inst);
case 143:
return aarch64_ins_sve_float_zero_one (self, info, code, inst);
case 145:
case 146:
return aarch64_ins_inv_limm (self, info, code, inst);
case 147:
case 148:
return aarch64_ins_sve_limm_mov (self, info, code, inst);
case 149:
case 150:
return aarch64_ins_sve_scale (self, info, code, inst);
case 161:
case 162:
return aarch64_ins_sve_shlimm (self, info, code, inst);
case 163:
return aarch64_ins_sve_shlimm (self, info, code, inst);
case 164:
case 165:
return aarch64_ins_sve_shrimm (self, info, code, inst);
case 182:
case 183:
case 184:
case 185:
return aarch64_ins_sve_quad_index (self, info, code, inst);
case 186:
return aarch64_ins_sve_index (self, info, code, inst);
case 187:
case 189:
return aarch64_ins_sve_index (self, info, code, inst);
case 188:
case 190:
return aarch64_ins_sve_reglist (self, info, code, inst);
default: assert (0); abort ();
}

1063
opcodes/aarch64-dis-2.c
View File

File diff suppressed because it is too large

1
opcodes/aarch64-opc-2.c
View File

@ -134,6 +134,7 @@ const struct aarch64_operand aarch64_operands[] =
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_U6x2", 1 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an address with a 6-bit unsigned offset, multiplied by 2"},
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_U6x4", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an address with a 6-bit unsigned offset, multiplied by 4"},
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_U6x8", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an address with a 6-bit unsigned offset, multiplied by 8"},
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_R", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_Rm}, "an address with an optional scalar register offset"},
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RR", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_Rm}, "an address with a scalar register offset"},
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RR_LSL1", 1 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_Rm}, "an address with a scalar register offset"},
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RR_LSL2", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_Rm}, "an address with a scalar register offset"},

2
opcodes/aarch64-opc.c
View File

@ -1835,6 +1835,7 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
max_value = 7;
goto sve_imm_offset;
case AARCH64_OPND_SVE_ADDR_R:
case AARCH64_OPND_SVE_ADDR_RR:
case AARCH64_OPND_SVE_ADDR_RR_LSL1:
case AARCH64_OPND_SVE_ADDR_RR_LSL2:
@ -3476,6 +3477,7 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
break;
case AARCH64_OPND_ADDR_REGOFF:
case AARCH64_OPND_SVE_ADDR_R:
case AARCH64_OPND_SVE_ADDR_RR:
case AARCH64_OPND_SVE_ADDR_RR_LSL1:
case AARCH64_OPND_SVE_ADDR_RR_LSL2:

26
opcodes/aarch64-tbl.h
View File

@ -3879,66 +3879,90 @@ struct aarch64_opcode aarch64_opcode_table[] =
_SVE_INSN ("ld4h", 0xa4e0e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_HZU, F_OD(4), 0),
_SVE_INSN ("ld4w", 0xa560c000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL2), OP_SVE_SZU, F_OD(4), 0),
_SVE_INSN ("ld4w", 0xa560e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_SZU, F_OD(4), 0),
_SVE_INSN ("ldff1b", 0x84006000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW_22), OP_SVE_SZS, F_OD(1), 0),
_SVE_INSN ("ldff1b", 0xa4006000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RR), OP_SVE_BZU, F_OD(1), 0),
_SVE_INSN ("ldff1b", 0xa4006000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_R), OP_SVE_BZU, F_OD(1), 0),
_SVE_INSN ("ldff1b", 0xa4206000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RR), OP_SVE_HZU, F_OD(1), 0),
_SVE_INSN ("ldff1b", 0xa4206000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_R), OP_SVE_HZU, F_OD(1), 0),
_SVE_INSN ("ldff1b", 0xa4406000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RR), OP_SVE_SZU, F_OD(1), 0),
_SVE_INSN ("ldff1b", 0xa4406000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_R), OP_SVE_SZU, F_OD(1), 0),
_SVE_INSN ("ldff1b", 0xa4606000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RR), OP_SVE_DZU, F_OD(1), 0),
_SVE_INSN ("ldff1b", 0xa4606000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_R), OP_SVE_DZU, F_OD(1), 0),
_SVE_INSN ("ldff1b", 0xc4006000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW_22), OP_SVE_DZD, F_OD(1), 0),
_SVE_INSN ("ldff1b", 0xc440e000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ), OP_SVE_DZD, F_OD(1), 0),
_SVE_INSN ("ldff1b", 0x8420e000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZI_U5), OP_SVE_SZS, F_OD(1), 0),
_SVE_INSN ("ldff1b", 0xc420e000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZI_U5), OP_SVE_DZD, F_OD(1), 0),
_SVE_INSN ("ldff1d", 0xa5e06000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RR_LSL3), OP_SVE_DZU, F_OD(1), 0),
_SVE_INSN ("ldff1d", 0xa5e06000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_R), OP_SVE_DZU, F_OD(1), 0),
_SVE_INSN ("ldff1d", 0xc5806000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW_22), OP_SVE_DZD, F_OD(1), 0),
_SVE_INSN ("ldff1d", 0xc5a06000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW3_22), OP_SVE_DZD, F_OD(1), 0),
_SVE_INSN ("ldff1d", 0xc5c0e000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ), OP_SVE_DZD, F_OD(1), 0),
_SVE_INSN ("ldff1d", 0xc5e0e000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_LSL3), OP_SVE_DZD, F_OD(1), 0),
_SVE_INSN ("ldff1d", 0xc5a0e000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZI_U5x8), OP_SVE_DZD, F_OD(1), 0),
_SVE_INSN ("ldff1h", 0x84806000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW_22), OP_SVE_SZS, F_OD(1), 0),
_SVE_INSN ("ldff1h", 0x84a06000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW1_22), OP_SVE_SZS, F_OD(1), 0),
_SVE_INSN ("ldff1h", 0xa4a06000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RR_LSL1), OP_SVE_HZU, F_OD(1), 0),
_SVE_INSN ("ldff1h", 0xa4a06000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_R), OP_SVE_HZU, F_OD(1), 0),
_SVE_INSN ("ldff1h", 0xa4c06000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RR_LSL1), OP_SVE_SZU, F_OD(1), 0),
_SVE_INSN ("ldff1h", 0xa4c06000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_R), OP_SVE_SZU, F_OD(1), 0),
_SVE_INSN ("ldff1h", 0xa4e06000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RR_LSL1), OP_SVE_DZU, F_OD(1), 0),
_SVE_INSN ("ldff1h", 0xa4e06000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_R), OP_SVE_DZU, F_OD(1), 0),
_SVE_INSN ("ldff1h", 0xc4806000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW_22), OP_SVE_DZD, F_OD(1), 0),
_SVE_INSN ("ldff1h", 0xc4a06000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW1_22), OP_SVE_DZD, F_OD(1), 0),
_SVE_INSN ("ldff1h", 0xc4c0e000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ), OP_SVE_DZD, F_OD(1), 0),
_SVE_INSN ("ldff1h", 0xc4e0e000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_LSL1), OP_SVE_DZD, F_OD(1), 0),
_SVE_INSN ("ldff1h", 0x84a0e000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZI_U5x2), OP_SVE_SZS, F_OD(1), 0),
_SVE_INSN ("ldff1h", 0xc4a0e000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZI_U5x2), OP_SVE_DZD, F_OD(1), 0),
_SVE_INSN ("ldff1sb", 0x84002000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW_22), OP_SVE_SZS, F_OD(1), 0),
_SVE_INSN ("ldff1sb", 0xa5806000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RR), OP_SVE_DZU, F_OD(1), 0),
_SVE_INSN ("ldff1sb", 0xa5806000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_R), OP_SVE_DZU, F_OD(1), 0),
_SVE_INSN ("ldff1sb", 0xa5a06000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RR), OP_SVE_SZU, F_OD(1), 0),
_SVE_INSN ("ldff1sb", 0xa5a06000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_R), OP_SVE_SZU, F_OD(1), 0),
_SVE_INSN ("ldff1sb", 0xa5c06000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RR), OP_SVE_HZU, F_OD(1), 0),
_SVE_INSN ("ldff1sb", 0xa5c06000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_R), OP_SVE_HZU, F_OD(1), 0),
_SVE_INSN ("ldff1sb", 0xc4002000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW_22), OP_SVE_DZD, F_OD(1), 0),
_SVE_INSN ("ldff1sb", 0xc440a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ), OP_SVE_DZD, F_OD(1), 0),
_SVE_INSN ("ldff1sb", 0x8420a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZI_U5), OP_SVE_SZS, F_OD(1), 0),
_SVE_INSN ("ldff1sb", 0xc420a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZI_U5), OP_SVE_DZD, F_OD(1), 0),
_SVE_INSN ("ldff1sh", 0x84802000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW_22), OP_SVE_SZS, F_OD(1), 0),
_SVE_INSN ("ldff1sh", 0x84a02000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW1_22), OP_SVE_SZS, F_OD(1), 0),
_SVE_INSN ("ldff1sh", 0xa5006000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RR_LSL1), OP_SVE_DZU, F_OD(1), 0),
_SVE_INSN ("ldff1sh", 0xa5006000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_R), OP_SVE_DZU, F_OD(1), 0),
_SVE_INSN ("ldff1sh", 0xa5206000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RR_LSL1), OP_SVE_SZU, F_OD(1), 0),
_SVE_INSN ("ldff1sh", 0xa5206000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_R), OP_SVE_SZU, F_OD(1), 0),
_SVE_INSN ("ldff1sh", 0xc4802000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW_22), OP_SVE_DZD, F_OD(1), 0),
_SVE_INSN ("ldff1sh", 0xc4a02000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW1_22), OP_SVE_DZD, F_OD(1), 0),
_SVE_INSN ("ldff1sh", 0xc4c0a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ), OP_SVE_DZD, F_OD(1), 0),
_SVE_INSN ("ldff1sh", 0xc4e0a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_LSL1), OP_SVE_DZD, F_OD(1), 0),
_SVE_INSN ("ldff1sh", 0x84a0a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZI_U5x2), OP_SVE_SZS, F_OD(1), 0),
_SVE_INSN ("ldff1sh", 0xc4a0a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZI_U5x2), OP_SVE_DZD, F_OD(1), 0),
_SVE_INSN ("ldff1sw", 0xa4806000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RR_LSL2), OP_SVE_DZU, F_OD(1), 0),
_SVE_INSN ("ldff1sw", 0xa4806000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_R), OP_SVE_DZU, F_OD(1), 0),
_SVE_INSN ("ldff1sw", 0xc5002000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW_22), OP_SVE_DZD, F_OD(1), 0),
_SVE_INSN ("ldff1sw", 0xc5202000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW2_22), OP_SVE_DZD, F_OD(1), 0),
_SVE_INSN ("ldff1sw", 0xc540a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ), OP_SVE_DZD, F_OD(1), 0),
_SVE_INSN ("ldff1sw", 0xc560a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_LSL2), OP_SVE_DZD, F_OD(1), 0),
_SVE_INSN ("ldff1sw", 0xc520a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZI_U5x4), OP_SVE_DZD, F_OD(1), 0),
_SVE_INSN ("ldff1w", 0x85006000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW_22), OP_SVE_SZS, F_OD(1), 0),
_SVE_INSN ("ldff1w", 0x85206000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW2_22), OP_SVE_SZS, F_OD(1), 0),
_SVE_INSN ("ldff1w", 0xa5406000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RR_LSL2), OP_SVE_SZU, F_OD(1), 0),
_SVE_INSN ("ldff1w", 0xa5406000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_R), OP_SVE_SZU, F_OD(1), 0),
_SVE_INSN ("ldff1w", 0xa5606000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RR_LSL2), OP_SVE_DZU, F_OD(1), 0),
_SVE_INSN ("ldff1w", 0xa5606000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_R), OP_SVE_DZU, F_OD(1), 0),
_SVE_INSN ("ldff1w", 0xc5006000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW_22), OP_SVE_DZD, F_OD(1), 0),
_SVE_INSN ("ldff1w", 0xc5206000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW2_22), OP_SVE_DZD, F_OD(1), 0),
_SVE_INSN ("ldff1w", 0xc540e000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ), OP_SVE_DZD, F_OD(1), 0),
_SVE_INSN ("ldff1w", 0xc560e000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_LSL2), OP_SVE_DZD, F_OD(1), 0),
_SVE_INSN ("ldff1w", 0x8520e000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZI_U5x4), OP_SVE_SZS, F_OD(1), 0),
_SVE_INSN ("ldff1w", 0xc520e000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZI_U5x4), OP_SVE_DZD, F_OD(1), 0),
_SVE_INSN ("ldnf1b", 0xa410a000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_BZU, F_OD(1), 0),
_SVE_INSN ("ldnf1b", 0xa430a000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_HZU, F_OD(1), 0),
_SVE_INSN ("ldnf1b", 0xa450a000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_SZU, F_OD(1), 0),
@ -4573,6 +4597,8 @@ struct aarch64_opcode aarch64_opcode_table[] =
Y(ADDRESS, sve_addr_ri_u6, "SVE_ADDR_RI_U6x8", 3 << OPD_F_OD_LSB, \
F(FLD_Rn), \
"an address with a 6-bit unsigned offset, multiplied by 8") \
Y(ADDRESS, sve_addr_rr_lsl, "SVE_ADDR_R", 0 << OPD_F_OD_LSB, \
F(FLD_Rn,FLD_Rm), "an address with an optional scalar register offset") \
Y(ADDRESS, sve_addr_rr_lsl, "SVE_ADDR_RR", 0 << OPD_F_OD_LSB, \
F(FLD_Rn,FLD_Rm), "an address with a scalar register offset") \
Y(ADDRESS, sve_addr_rr_lsl, "SVE_ADDR_RR_LSL1", 1 << OPD_F_OD_LSB, \

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