Browse Source
Hi,
This is based on a patch originally written by Alan Modra.
Powerpc / Power10 ISA 3.1 adds prefixed instructions, which
are 8 bytes in length. This is in contrast to powerpc previously
always having 4 byte instruction length. This patch implements
changes to allow GDB to better detect prefixed instructions, and
handle single stepping across the 8 byte instructions.
Added #defines to help test for PNOP and prefix instructions.
Update ppc_displaced_step_copy_insn() to handle pnop and prefixed
instructions whem R=0 (non-pc-relative).
Updated ppc_displaced_step_fixup() to properly handle the offset
value matching the current instruction size
Updated the for-loop within ppc_deal_with_atomic_sequence() to
count instructions properly in case we have a mix of 4-byte and
8-byte instructions within the atomic_sequence_length.
Added testcase and harness to exercise pc-relative load/store
instructions with R=0.
2021-04-12 Will Schmidt <will_schmidt@vnet.ibm.com>
gdb/ChangeLog:
* rs6000-tdep.c: Add support for single-stepping of
prefixed instructions.
gdb/testsuite/ChangeLog:
* gdb.arch/powerpc-plxv-nonrel.s: Testcase using
non-relative plxv instructions.
* gdb.arch/powerpc-plxv-nonrel.exp: Testcase harness.
binutils-2_37-branch
Will Schmidt
5 years ago
5 changed files with 236 additions and 9 deletions
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# Copyright 2021 Free Software Foundation, Inc. |
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# This program is free software; you can redistribute it and/or modify |
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# it under the terms of the GNU General Public License as published by |
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# the Free Software Foundation; either version 3 of the License, or |
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# (at your option) any later version. |
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# |
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# This program is distributed in the hope that it will be useful, |
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# but WITHOUT ANY WARRANTY; without even the implied warranty of |
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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# GNU General Public License for more details. |
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# |
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# You should have received a copy of the GNU General Public License |
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# along with this program. If not, see <http://www.gnu.org/licenses/>. |
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# Test to see if gdb is properly single stepping over the |
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# displaced plxv instruction. |
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if { ![istarget powerpc*-*] } { |
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verbose "Skipping powerpc plxv test." |
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return |
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} |
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set retval 0 |
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standard_testfile .s |
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if { [prepare_for_testing "failed to prepare" $testfile "$srcfile" \ |
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{debug quiet}] } { |
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return -1 |
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} |
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gdb_test "set radix 0b10000" |
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gdb_test "set debug displaced" |
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if ![runto_main] then { |
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return |
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} |
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gdb_test "set debug displaced on" |
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# Proc to extract the uint128 hex value from the output of |
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# a print vector statement. |
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proc get_vector_hexadecimal_valueof { exp default {test ""} } { |
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set val "0x0000" |
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global gdb_prompt |
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if {$test == ""} { |
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set test "get vector_hexadecimal valueof \"${exp}\"" |
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} |
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gdb_test_multiple "print $${exp}.uint128" $test { |
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-re -wrap "\\$\[0-9\]* = (0x\[0-9a-zA-Z\]+).*" { |
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set val $expect_out(1,string) |
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pass "$test" |
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} |
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-re -wrap ".*Illegal instruction.* $" { |
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fail "Illegal instruction on print." |
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set val 0xffff |
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} |
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} |
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return ${val} |
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} |
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# Proc to do a single-step, and ensure we gently handle |
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# an illegal instruction situation. |
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proc stepi_over_instruction { xyz } { |
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global gdb_prompt |
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gdb_test_multiple "stepi" "${xyz} " { |
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-re -wrap ".*Illegal instruction.*" { |
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fail "Illegal instruction on single step." |
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return |
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} |
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-re -wrap ".*" { |
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pass "stepi ${xyz}" |
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} |
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} |
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} |
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set check_pc [get_hexadecimal_valueof "\$pc" "default0"] |
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# set some breakpoints on the instructions below main(). |
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gdb_test "disas /r main" |
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set bp1 *$check_pc+4 |
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set bp2 *$check_pc+0d12 |
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set bp3 *$check_pc+0d20 |
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set bp4 *$check_pc+0d28 |
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gdb_breakpoint $bp1 |
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gdb_breakpoint $bp2 |
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gdb_breakpoint $bp3 |
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gdb_breakpoint $bp4 |
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# single-step through the plxv instructions, and retrieve the |
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# register values as we proceed. |
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stepi_over_instruction "stepi over NOP" |
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stepi_over_instruction "stepi over lnia" |
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stepi_over_instruction "stepi over addi" |
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stepi_over_instruction "stepi over vs4 assignment" |
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set check_vs4 [get_vector_hexadecimal_valueof "vs4" "default0"] |
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stepi_over_instruction "stepi over vs5 assignment" |
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set check_vs5 [get_vector_hexadecimal_valueof "vs5" "default0"] |
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stepi_over_instruction "stepi over vs6 assignment" |
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set check_vs6 [get_vector_hexadecimal_valueof "vs6" "default0"] |
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stepi_over_instruction "stepi over vs7 assignment" |
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set check_vs7 [get_vector_hexadecimal_valueof "vs7" "default0"] |
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set vs4_expected 0xa5b5c5d5a4b4c4d4a3b3c3d3a2b2c2d2 |
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set vs5_expected 0xa7b7c7d7a6b6c6d6a5b5c5d5a4b4c4d4 |
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set vs6_expected 0xa9b9c9d9a8b8c8d8a7b7c7d7a6b6c6d6 |
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set vs7_expected 0xabbbcbdbaabacadaa9b9c9d9a8b8c8d8 |
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if [expr $check_vs4 != $vs4_expected] { |
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fail "unexpected value vs4; actual:$check_vs4 expected:$vs4_expected" |
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} |
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if [expr $check_vs5 != $vs5_expected ] { |
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fail "unexpected value vs5; actual:$check_vs5 expected:$vs5_expected" |
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} |
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if [expr $check_vs6 != $vs6_expected ] { |
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fail "unexpected value vs6; actual:$check_vs6 expected:$vs6_expected" |
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} |
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if [expr $check_vs7 != $vs7_expected ] { |
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fail "unexpected value vs7; actual:$check_vs7 expected:$vs7_expected" |
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} |
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gdb_test "info break" |
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gdb_test "info register vs4 vs5 vs6 vs7 " |
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gdb_test "disas main #2" |
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@ -0,0 +1,45 @@ |
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# Copyright 2021 Free Software Foundation, Inc. |
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# This program is free software; you can redistribute it and/or modify |
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# it under the terms of the GNU General Public License as published by |
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# the Free Software Foundation; either version 3 of the License, or |
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# (at your option) any later version. |
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# |
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# This program is distributed in the hope that it will be useful, |
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# but WITHOUT ANY WARRANTY; without even the implied warranty of |
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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# GNU General Public License for more details. |
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# |
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# You should have received a copy of the GNU General Public License |
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# along with this program. If not, see <http://www.gnu.org/licenses/>. |
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# test to verify that the prefixed instructions that |
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# load/store non-relative values work OK. |
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.global main |
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.type main,function |
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main: |
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nop |
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lnia 4 |
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addi 4,4,40 |
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plxv 4,4(4),0 |
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plxv 5,12(4),0 |
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plxv 6,20(4),0 |
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plxv 7,28(4),0 |
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check_here: |
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blr |
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mydata: |
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.long 0xa1b1c1d1 # <<- |
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.long 0xa2b2c2d2 # <<- loaded into vs4 |
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.long 0xa3b3c3d3 # <<- loaded into vs4 |
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.long 0xa4b4c4d4 # <<- loaded into vs4, vs5 |
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.long 0xa5b5c5d5 # <<- loaded into vs4, vs5 |
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.long 0xa6b6c6d6 # <<- loaded into vs5, vs6 |
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.long 0xa7b7c7d7 # <<- loaded into vs5, vs6 |
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.long 0xa8b8c8d8 # <<- loaded into vs6, vs7 |
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.long 0xa9b9c9d9 # <<- loaded into vs6, vs7 |
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.long 0xaabacada # <<- loaded into vs7 |
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.long 0xabbbcbdb # <<- loaded into vs7 |
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.long 0xacbcccdc # <<- |
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