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include/opcode/ 

2013-05-22  Jürgen Urban  <JuergenUrban@gmx.de>

	* mips.h (M_LQC2_AB, M_SQC2_AB): New macros.

opcodes/
2013-05-22  Jürgen Urban  <JuergenUrban@gmx.de>

	* mips-opc.c (mips_builtin_opcodes): Add R5900 VU0 instructions.

gas/
2013-05-22  Jürgen Urban  <JuergenUrban@gmx.de>

	* config/tc-mips.c (macro): Handle M_LQC2_AB and M_SQC2_AB.

gas/testsuite/
2013-05-22  Jürgen Urban  <JuergenUrban@gmx.de>

	* gas/mips/r5900-full.s, gas/mips/r5900-full.d: Add tests for LQ
	and SQ macros.
	* gas/mips/r5900-vu0.s, gas/mips/r5900-vu0.d: New test.
	* gas/mips/mips.exp: Run it.
binutils-2_24-branch
Richard Sandiford 13 years ago
parent
45901633da
commit
c77c0862b2
12 changed files with 226 additions and 9 deletions
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  1. 4
      gas/ChangeLog
  2. 14
      gas/config/tc-mips.c
  3. 7
      gas/testsuite/ChangeLog
  4. 1
      gas/testsuite/gas/mips/mips.exp
  5. 18
      gas/testsuite/gas/mips/r5900-full.d
  6. 12
      gas/testsuite/gas/mips/r5900-full.s
  7. 66
      gas/testsuite/gas/mips/r5900-vu0.d
  8. 76
      gas/testsuite/gas/mips/r5900-vu0.s
  9. 4
      include/opcode/ChangeLog
  10. 2
      include/opcode/mips.h
  11. 4
      opcodes/ChangeLog
  12. 27
      opcodes/mips-opc.c

4
gas/ChangeLog
View File

@ -1,3 +1,7 @@
2013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
* config/tc-mips.c (macro): Handle M_LQC2_AB and M_SQC2_AB.
2013-05-20 Peter Bergner <bergner@vnet.ibm.com>
* config/tc-ppc.c (ppc_setup_opcodes): Use new_seg to fix error

14
gas/config/tc-mips.c
View File

@ -8201,6 +8201,13 @@ macro (struct mips_cl_insn *ip)
/* Itbl support may require additional care here. */
coproc = 1;
goto ld_st;
case M_LQC2_AB:
ab = 1;
s = "lqc2";
fmt = "E,o(b)";
/* Itbl support may require additional care here. */
coproc = 1;
goto ld_st;
case M_LDC3_AB:
ab = 1;
s = "ldc3";
@ -8390,6 +8397,13 @@ macro (struct mips_cl_insn *ip)
/* Itbl support may require additional care here. */
coproc = 1;
goto ld_st;
case M_SQC2_AB:
ab = 1;
s = "sqc2";
fmt = "E,o(b)";
/* Itbl support may require additional care here. */
coproc = 1;
goto ld_st;
case M_SDC3_AB:
ab = 1;
gas_assert (!mips_opts.micromips);

7
gas/testsuite/ChangeLog
View File

@ -1,3 +1,10 @@
2013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
* gas/mips/r5900-full.s, gas/mips/r5900-full.d: Add tests for LQ
and SQ macros.
* gas/mips/r5900-vu0.s, gas/mips/r5900-vu0.d: New test.
* gas/mips/mips.exp: Run it.
2013-05-21 Alan Modra <amodra@gmail.com>
* gas/ppc/vsx2.d: Ignore trailing padding.

1
gas/testsuite/gas/mips/mips.exp
View File

@ -1173,6 +1173,7 @@ if { [istarget mips*-*-vxworks*] } {
run_dump_test "r5900"
run_dump_test "r5900-full"
if $elf { run_list_test "r5900-nollsc" "-mabi=o64 -march=r5900" }
run_dump_test "r5900-vu0"
run_list_test_arches "ext-ill" [mips_arch_list_matching mips64r2]
}

18
gas/testsuite/gas/mips/r5900-full.d
View File

@ -43,10 +43,28 @@ Disassembly of section \.text:
[0-9a-f]+ <[^>]*> 7c217fff sq \$1,32767\(\$1\)
[0-9a-f]+ <[^>]*> 7d088000 sq \$8,-32768\(\$8\)
[0-9a-f]+ <[^>]*> 7fffffff sq \$31,-1\(\$31\)
[0-9a-f]+ <[^>]*> 3c010001 lui \$1,0x1
[0-9a-f]+ <[^>]*> 00220821 addu \$1,\$1,\$2
[0-9a-f]+ <[^>]*> 7c208000 sq \$0,-32768\(\$1\)
[0-9a-f]+ <[^>]*> 3c01ffff lui \$1,0xffff
[0-9a-f]+ <[^>]*> 003f0821 addu \$1,\$1,\$31
[0-9a-f]+ <[^>]*> 7c287fff sq \$8,32767\(\$1\)
[0-9a-f]+ <[^>]*> 3c01f123 lui \$1,0xf123
[0-9a-f]+ <[^>]*> 00240821 addu \$1,\$1,\$4
[0-9a-f]+ <[^>]*> 7c3f4567 sq \$31,17767\(\$1\)
[0-9a-f]+ <[^>]*> 78000000 lq \$0,0\(\$0\)
[0-9a-f]+ <[^>]*> 78217fff lq \$1,32767\(\$1\)
[0-9a-f]+ <[^>]*> 79088000 lq \$8,-32768\(\$8\)
[0-9a-f]+ <[^>]*> 7bffffff lq \$31,-1\(\$31\)
[0-9a-f]+ <[^>]*> 3c030001 lui \$3,0x1
[0-9a-f]+ <[^>]*> 00621821 addu \$3,\$3,\$2
[0-9a-f]+ <[^>]*> 78638000 lq \$3,-32768\(\$3\)
[0-9a-f]+ <[^>]*> 3c08ffff lui \$8,0xffff
[0-9a-f]+ <[^>]*> 011f4021 addu \$8,\$8,\$31
[0-9a-f]+ <[^>]*> 79087fff lq \$8,32767\(\$8\)
[0-9a-f]+ <[^>]*> 3c1ff123 lui \$31,0xf123
[0-9a-f]+ <[^>]*> 03e4f821 addu \$31,\$31,\$4
[0-9a-f]+ <[^>]*> 7bff4567 lq \$31,17767\(\$31\)
[0-9a-f]+ <[^>]*> cc000000 pref 0x0,0\(\$0\)
[0-9a-f]+ <[^>]*> cc217fff pref 0x1,32767\(\$1\)
[0-9a-f]+ <[^>]*> cd088000 pref 0x8,-32768\(\$8\)

12
gas/testsuite/gas/mips/r5900-full.s
View File

@ -53,7 +53,7 @@ stuff:
trunc.w.s $f0, $f31
trunc.w.s $f31, $f0
# Test ei/di, but not the R5900 has a bug. ei/di should not be used.
# Test ei/di, but the R5900 has a bug. ei/di should not be used.
di
ei
@ -68,12 +68,20 @@ stuff:
sq $1, 0x7fff($1)
sq $8, -0x8000($8)
sq $31, -1($31)
.set at
sq $0, 0x8000($2)
sq $8, -0x8001($31)
sq $31, 0xF1234567($4)
.set noat
# 128 bit load instruction.
lq $0, 0($0)
lq $1, 0x7fff($1)
lq $8, -0x8000($8)
lq $31, -1($31)
lq $3, 0x8000($2)
lq $8, -0x8001($31)
lq $31, 0xF1234567($4)
# Prefetch cache
pref 0, 0($0)
@ -210,7 +218,7 @@ stuff:
rsqrt.s $f0, $f31, $f0
rsqrt.s $f31, $f0, $f31
# FLoating point subtract to accumulator
# Floating point subtract to accumulator
suba.s $f0, $f31
suba.s $f31, $f0

66
gas/testsuite/gas/mips/r5900-vu0.d
View File

@ -0,0 +1,66 @@
#objdump: -dr --prefix-addresses --show-raw-insn -M gpr-names=numeric -mmips:5900
#name: MIPS R5900 VU0
#as: -march=r5900
.*: +file format .*mips.*
Disassembly of section \.text:
[0-9a-f]+ <[^>]*> d8000000 lqc2 \$0,0\(\$0\)
[0-9a-f]+ <[^>]*> d8217fff lqc2 \$1,32767\(\$1\)
[0-9a-f]+ <[^>]*> d9088000 lqc2 \$8,-32768\(\$8\)
[0-9a-f]+ <[^>]*> dbffffff lqc2 \$31,-1\(\$31\)
[0-9a-f]+ <[^>]*> 3c010001 lui \$1,0x1
[0-9a-f]+ <[^>]*> 00220821 addu \$1,\$1,\$2
[0-9a-f]+ <[^>]*> d8208000 lqc2 \$0,-32768\(\$1\)
[0-9a-f]+ <[^>]*> 3c01ffff lui \$1,0xffff
[0-9a-f]+ <[^>]*> 003f0821 addu \$1,\$1,\$31
[0-9a-f]+ <[^>]*> d8287fff lqc2 \$8,32767\(\$1\)
[0-9a-f]+ <[^>]*> 3c01f123 lui \$1,0xf123
[0-9a-f]+ <[^>]*> 00240821 addu \$1,\$1,\$4
[0-9a-f]+ <[^>]*> d83f4567 lqc2 \$31,17767\(\$1\)
[0-9a-f]+ <[^>]*> f8000000 sqc2 \$0,0\(\$0\)
[0-9a-f]+ <[^>]*> f8217fff sqc2 \$1,32767\(\$1\)
[0-9a-f]+ <[^>]*> f9088000 sqc2 \$8,-32768\(\$8\)
[0-9a-f]+ <[^>]*> fbffffff sqc2 \$31,-1\(\$31\)
[0-9a-f]+ <[^>]*> 3c010001 lui \$1,0x1
[0-9a-f]+ <[^>]*> 00220821 addu \$1,\$1,\$2
[0-9a-f]+ <[^>]*> f8208000 sqc2 \$0,-32768\(\$1\)
[0-9a-f]+ <[^>]*> 3c01ffff lui \$1,0xffff
[0-9a-f]+ <[^>]*> 003f0821 addu \$1,\$1,\$31
[0-9a-f]+ <[^>]*> f8287fff sqc2 \$8,32767\(\$1\)
[0-9a-f]+ <[^>]*> 3c01f123 lui \$1,0xf123
[0-9a-f]+ <[^>]*> 00240821 addu \$1,\$1,\$4
[0-9a-f]+ <[^>]*> f83f4567 sqc2 \$31,17767\(\$1\)
[0-9a-f]+ <[^>]*> 48400000 cfc2 \$0,\$0
[0-9a-f]+ <[^>]*> 4840f800 cfc2 \$0,\$31
[0-9a-f]+ <[^>]*> 48400001 cfc2.i \$0,\$0
[0-9a-f]+ <[^>]*> 4840f801 cfc2.i \$0,\$31
[0-9a-f]+ <[^>]*> 48400000 cfc2 \$0,\$0
[0-9a-f]+ <[^>]*> 4840f800 cfc2 \$0,\$31
[0-9a-f]+ <[^>]*> 48c00000 ctc2 \$0,\$0
[0-9a-f]+ <[^>]*> 48c0f800 ctc2 \$0,\$31
[0-9a-f]+ <[^>]*> 48c00001 ctc2.i \$0,\$0
[0-9a-f]+ <[^>]*> 48c0f801 ctc2.i \$0,\$31
[0-9a-f]+ <[^>]*> 48c00000 ctc2 \$0,\$0
[0-9a-f]+ <[^>]*> 48c0f800 ctc2 \$0,\$31
[0-9a-f]+ <[^>]*> 48200000 qmfc2 \$0,\$0
[0-9a-f]+ <[^>]*> 4820f800 qmfc2 \$0,\$31
[0-9a-f]+ <[^>]*> 48200001 qmfc2.i \$0,\$0
[0-9a-f]+ <[^>]*> 4820f801 qmfc2.i \$0,\$31
[0-9a-f]+ <[^>]*> 48200000 qmfc2 \$0,\$0
[0-9a-f]+ <[^>]*> 4820f800 qmfc2 \$0,\$31
[0-9a-f]+ <[^>]*> 48a00000 qmtc2 \$0,\$0
[0-9a-f]+ <[^>]*> 48a0f800 qmtc2 \$0,\$31
[0-9a-f]+ <[^>]*> 48a00001 qmtc2.i \$0,\$0
[0-9a-f]+ <[^>]*> 48a0f801 qmtc2.i \$0,\$31
[0-9a-f]+ <[^>]*> 48a00000 qmtc2 \$0,\$0
[0-9a-f]+ <[^>]*> 48a0f800 qmtc2 \$0,\$31
[0-9a-f]+ <[^>]*> 4900ffff bc2f [0-9a-f]+ <branch_label>
[0-9a-f]+ <[^>]*> 00000000 nop
[0-9a-f]+ <[^>]*> 4902fffd bc2fl [0-9a-f]+ <branch_label>
[0-9a-f]+ <[^>]*> 00000000 nop
[0-9a-f]+ <[^>]*> 4901fffb bc2t [0-9a-f]+ <branch_label>
[0-9a-f]+ <[^>]*> 00000000 nop
[0-9a-f]+ <[^>]*> 4903fff9 bc2tl [0-9a-f]+ <branch_label>
[0-9a-f]+ <[^>]*> 00000000 nop
\.\.\.

76
gas/testsuite/gas/mips/r5900-vu0.s
View File

@ -0,0 +1,76 @@
.text
.set noreorder
.set noat
.ent text_label
.global text_label
text_label:
# Floating point transfer to VU
lqc2 $0,0($0)
lqc2 $1, 0x7fff($1)
lqc2 $8, -0x8000($8)
lqc2 $31, -1($31)
.set at
lqc2 $0, 0x8000($2)
lqc2 $8, -0x8001($31)
lqc2 $31, 0xF1234567($4)
.set noat
# Floating point transfer from VU
sqc2 $0,0($0)
sqc2 $1, 0x7fff($1)
sqc2 $8, -0x8000($8)
sqc2 $31, -1($31)
.set at
sqc2 $0, 0x8000($2)
sqc2 $8, -0x8001($31)
sqc2 $31, 0xF1234567($4)
.set noat
# Integer transfer from VU
cfc2 $0,$0
cfc2 $0,$31
cfc2.i $0,$0
cfc2.i $0,$31
cfc2.ni $0,$0
cfc2.ni $0,$31
# Integer transfer to VU
ctc2 $0,$0
ctc2 $0,$31
ctc2.i $0,$0
ctc2.i $0,$31
ctc2.ni $0,$0
ctc2.ni $0,$31
# Floating point transfer from VU
qmfc2 $0,$0
qmfc2 $0,$31
qmfc2.i $0,$0
qmfc2.i $0,$31
qmfc2.ni $0,$0
qmfc2.ni $0,$31
# Floating point transfer to VU
qmtc2 $0,$0
qmtc2 $0,$31
qmtc2.i $0,$0
qmtc2.i $0,$31
qmtc2.ni $0,$0
qmtc2.ni $0,$31
# COP2 conditional branch instructions
branch_label:
bc2f branch_label
nop
bc2fl branch_label
nop
bc2t branch_label
nop
bc2tl branch_label
nop
# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
.space 8
.end text_label

4
include/opcode/ChangeLog
View File

@ -1,3 +1,7 @@
2013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
* mips.h (M_LQC2_AB, M_SQC2_AB): New macros.
2013-05-09 Andrew Pinski <apinski@cavium.com>
* mips.h (OP_MASK_CODE10): Correct definition.

2
include/opcode/mips.h
View File

@ -1070,6 +1070,7 @@ enum
M_LDC1_AB,
M_LDC2_AB,
M_LDC2_OB,
M_LQC2_AB,
M_LDC3_AB,
M_LDL_AB,
M_LDL_OB,
@ -1163,6 +1164,7 @@ enum
M_SDC1_AB,
M_SDC2_AB,
M_SDC2_OB,
M_SQC2_AB,
M_SDC3_AB,
M_SDL_AB,
M_SDL_OB,

4
opcodes/ChangeLog
View File

@ -1,3 +1,7 @@
2013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
* mips-opc.c (mips_builtin_opcodes): Add R5900 VU0 instructions.
2013-05-20 Peter Bergner <bergner@vnet.ibm.com>
* ppc-dis.c (powerpc_init_dialect): Set default dialect to power8.

27
opcodes/mips-opc.c
View File

@ -914,6 +914,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"lld", "t,A(b)", 0, (int) M_LLD_AB, INSN_MACRO, 0, I3, EE },
{"lq", "t,o(b)", 0x78000000, 0xfc000000, WR_t|RD_b, 0, MMI },
{"lq", "t,A(b)", 0, (int) M_LQ_AB, INSN_MACRO, 0, MMI },
{"lqc2", "E,o(b)", 0xd8000000, 0xfc000000, RD_b|WR_C2, 0, EE },
{"lqc2", "E,A(b)", 0, (int) M_LQC2_AB, INSN_MACRO, 0, EE },
{"lui", "t,u", 0x3c000000, 0xffe00000, WR_t, 0, I1 },
{"luxc1", "D,t(b)", 0x4c000005, 0xfc00f83f, LDD|WR_D|RD_t|RD_b|FP_D, 0, I5_33|N55},
{"lw", "t,o(b)", 0x8c000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 },
@ -1535,6 +1537,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"snei", "t,r,+Q", 0x7000002f, 0xfc00003f, WR_t|RD_s, 0, IOCT },
{"sq", "t,o(b)", 0x7c000000, 0xfc000000, SM|RD_t|RD_b, 0, MMI },
{"sq", "t,A(b)", 0, (int) M_SQ_AB, INSN_MACRO, 0, MMI },
{"sqc2", "E,o(b)", 0xf8000000, 0xfc000000, SM|RD_C2|RD_b, 0, EE },
{"sqc2", "E,A(b)", 0, (int) M_SQC2_AB, INSN_MACRO, 0, EE },
{"sqrt.d", "D,S", 0x46200004, 0xffff003f, WR_D|RD_S|FP_D, 0, I2, SF },
{"sqrt.s", "D,S", 0x46000004, 0xffff003f, WR_D|RD_S|FP_S, 0, I2 },
{"sqrt.ps", "D,S", 0x46c00004, 0xffff003f, WR_D|RD_S|FP_D, 0, SB1 },
@ -1781,16 +1785,20 @@ const struct mips_opcode mips_builtin_opcodes[] =
/* Coprocessor 2 move/branch operations overlap with VR5400 .ob format
instructions so they are here for the latters to take precedence. */
{"bc2f", "p", 0x49000000, 0xffff0000, CBD|RD_CC, 0, I1, IOCT|IOCTP|IOCT2|EE },
{"bc2f", "p", 0x49000000, 0xffff0000, CBD|RD_CC, 0, I1, IOCT|IOCTP|IOCT2 },
{"bc2f", "N,p", 0x49000000, 0xffe30000, CBD|RD_CC, 0, I32, IOCT|IOCTP|IOCT2 },
{"bc2fl", "p", 0x49020000, 0xffff0000, CBL|RD_CC, 0, I2|T3, IOCT|IOCTP|IOCT2|EE },
{"bc2fl", "p", 0x49020000, 0xffff0000, CBL|RD_CC, 0, I2|T3, IOCT|IOCTP|IOCT2 },
{"bc2fl", "N,p", 0x49020000, 0xffe30000, CBL|RD_CC, 0, I32, IOCT|IOCTP|IOCT2 },
{"bc2t", "p", 0x49010000, 0xffff0000, CBD|RD_CC, 0, I1, IOCT|IOCTP|IOCT2|EE },
{"bc2t", "p", 0x49010000, 0xffff0000, CBD|RD_CC, 0, I1, IOCT|IOCTP|IOCT2 },
{"bc2t", "N,p", 0x49010000, 0xffe30000, CBD|RD_CC, 0, I32, IOCT|IOCTP|IOCT2 },
{"bc2tl", "p", 0x49030000, 0xffff0000, CBL|RD_CC, 0, I2|T3, IOCT|IOCTP|IOCT2|EE },
{"bc2tl", "p", 0x49030000, 0xffff0000, CBL|RD_CC, 0, I2|T3, IOCT|IOCTP|IOCT2 },
{"bc2tl", "N,p", 0x49030000, 0xffe30000, CBL|RD_CC, 0, I32, IOCT|IOCTP|IOCT2 },
{"cfc2", "t,G", 0x48400000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I1, IOCT|IOCTP|IOCT2|EE },
{"ctc2", "t,G", 0x48c00000, 0xffe007ff, COD|RD_t|WR_CC, 0, I1, IOCT|IOCTP|IOCT2|EE },
{"cfc2", "t,G", 0x48400000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I1, IOCT|IOCTP|IOCT2 },
{"cfc2.i", "t,G", 0x48400001, 0xffe007ff, LCD|WR_t|RD_C2, 0, EE },
{"cfc2.ni", "t,G", 0x48400000, 0xffe007ff, LCD|WR_t|RD_C2, 0, EE },
{"ctc2", "t,G", 0x48c00000, 0xffe007ff, COD|RD_t|WR_CC, 0, I1, IOCT|IOCTP|IOCT2 },
{"ctc2.i", "t,G", 0x48c00001, 0xffe007ff, COD|RD_t|WR_CC, 0, EE },
{"ctc2.ni", "t,G", 0x48c00000, 0xffe007ff, COD|RD_t|WR_CC, 0, EE },
{"dmfc2", "t,i", 0x48200000, 0xffe00000, LCD|WR_t|RD_C2, 0, IOCT },
{"dmfc2", "t,G", 0x48200000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I3, IOCT|IOCTP|IOCT2|EE },
{"dmfc2", "t,G,H", 0x48200000, 0xffe007f8, LCD|WR_t|RD_C2, 0, I64, IOCT|IOCTP|IOCT2 },
@ -1807,7 +1815,12 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"mthc2", "t,G", 0x48e00000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, 0, I33, IOCT|IOCTP|IOCT2 },
{"mthc2", "t,G,H", 0x48e00000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, 0, I33, IOCT|IOCTP|IOCT2 },
{"mthc2", "t,i", 0x48e00000, 0xffe00000, COD|RD_t|WR_C2|WR_CC, 0, I33, IOCT|IOCTP|IOCT2 },
{"qmfc2", "t,G", 0x48200000, 0xffe007ff, WR_t|RD_C2, 0, EE },
{"qmfc2.i", "t,G", 0x48200001, 0xffe007ff, WR_t|RD_C2, 0, EE },
{"qmfc2.ni","t,G", 0x48200000, 0xffe007ff, WR_t|RD_C2, 0, EE },
{"qmtc2", "t,G", 0x48a00000, 0xffe007ff, RD_t|WR_C2, 0, EE },
{"qmtc2.i", "t,G", 0x48a00001, 0xffe007ff, RD_t|WR_C2, 0, EE },
{"qmtc2.ni","t,G", 0x48a00000, 0xffe007ff, RD_t|WR_C2, 0, EE },
/* Coprocessor 3 move/branch operations overlap with MIPS IV COP1X
instructions, so they are here for the latters to take precedence. */
{"bc3f", "p", 0x4d000000, 0xffff0000, CBD|RD_CC, 0, I1, IOCT|IOCTP|IOCT2|EE },

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