PowerPC disassembly of pcrel references

This adds some annotation to Power10 pcrel instructions, displaying the target address (ie. pc + D34 field) plus a symbol if there is one at exactly that target address. pld from the .got or .plt will also look up the entry and display it, symbolically if there is a dynamic relocation on the entry. include/ * dis-asm.h (struct disassemble_info): Add dynrelbuf and dynrelcount. binutils/ * objdump.c (struct objdump_disasm_info): Delete dynrelbuf and dynrelcount. (find_symbol_for_address): Adjust for dynrelbuf and dynrelcount move. (disassemble_section, disassemble_data): Likewise. opcodes/ * ppc-dis.c (struct dis_private): Add "special". (POWERPC_DIALECT): Delete. Replace uses with.. (private_data): ..this. New inline function. (disassemble_init_powerpc): Init "special" names. (skip_optional_operands): Add is_pcrel arg, set when detecting R field of prefix instructions. (bsearch_reloc, print_got_plt): New functions. (print_insn_powerpc): For pcrel instructions, print target address and symbol if known, and decode plt and got loads too. gas/ * testsuite/gas/ppc/prefix-pcrel.d: Update expected output. * testsuite/gas/ppc/prefix-reloc.d: Likewise. * gas/testsuite/gas/ppc/vsx_32byte.d: Likewise. ld/ * testsuite/ld-powerpc/inlinepcrel-1.d: Update expected output. * testsuite/ld-powerpc/inlinepcrel-2.d: Likewise. * testsuite/ld-powerpc/notoc2.d: Likewise. * testsuite/ld-powerpc/notoc3.d: Likewise. * testsuite/ld-powerpc/pcrelopt.d: Likewise. * testsuite/ld-powerpc/startstop.d: Likewise. * testsuite/ld-powerpc/tlsget.d: Likewise. * testsuite/ld-powerpc/tlsget2.d: Likewise. * testsuite/ld-powerpc/tlsld.d: Likewise. * testsuite/ld-powerpc/weak1.d: Likewise. * testsuite/ld-powerpc/weak1so.d: Likewise.
5 years ago · c3f72de4f5
22 changed files with 311 additions and 147 deletions
--- a/binutils/ChangeLog
+++ b/binutils/ChangeLog
@ -1,3 +1,10 @@
+2021-04-09  Alan Modra  <amodra@gmail.com>
+
+	* objdump.c (struct objdump_disasm_info): Delete dynrelbuf and
+	dynrelcount.
+	(find_symbol_for_address): Adjust for dynrelbuf and dynrelcount move.
+	(disassemble_section, disassemble_data): Likewise.
+
 2021-04-06  Alan Modra  <amodra@gmail.com>

 	* objdump.c (objdump_symbol_at_address): Return asymbol*.
--- a/binutils/objdump.c
+++ b/binutils/objdump.c
@ -153,8 +153,6 @@ struct objdump_disasm_info
 {
  bfd *abfd;
  bool require_sec;
-  arelent **dynrelbuf;
-  long dynrelcount;
  disassembler_ftype disassemble_fn;
  arelent *reloc;
  const char *symbol;
@ -1270,20 +1268,20 @@ find_symbol_for_address (bfd_vma vma,
     and we have dynamic relocations available, then we can produce
     a better result by matching a relocation to the address and
     using the symbol associated with that relocation.  */
-  rel_count = aux->dynrelcount;
+  rel_count = inf->dynrelcount;
  if (!want_section
      && sorted_syms[thisplace]->value != vma
      && rel_count > 0
-      && aux->dynrelbuf != NULL
-      && aux->dynrelbuf[0]->address <= vma
-      && aux->dynrelbuf[rel_count - 1]->address >= vma
+      && inf->dynrelbuf != NULL
+      && inf->dynrelbuf[0]->address <= vma
+      && inf->dynrelbuf[rel_count - 1]->address >= vma
      /* If we have matched a synthetic symbol, then stick with that.  */
      && (sorted_syms[thisplace]->flags & BSF_SYNTHETIC) == 0)
    {
      arelent **  rel_low;
      arelent **  rel_high;

-      rel_low = aux->dynrelbuf;
+      rel_low = inf->dynrelbuf;
      rel_high = rel_low + rel_count - 1;
      while (rel_low <= rel_high)
 	{
@ -3116,10 +3114,10 @@ disassemble_section (bfd *abfd, asection *section, void *inf)

  /* Decide which set of relocs to use.  Load them if necessary.  */
  paux = (struct objdump_disasm_info *) pinfo->application_data;
-  if (paux->dynrelbuf && dump_dynamic_reloc_info)
+  if (pinfo->dynrelbuf && dump_dynamic_reloc_info)
    {
-      rel_pp = paux->dynrelbuf;
-      rel_count = paux->dynrelcount;
+      rel_pp = pinfo->dynrelbuf;
+      rel_count = pinfo->dynrelcount;
      /* Dynamic reloc addresses are absolute, non-dynamic are section
 	 relative.  REL_OFFSET specifies the reloc address corresponding
 	 to the start of this section.  */
@ -3455,8 +3453,8 @@ disassemble_data (bfd *abfd)
  disasm_info.application_data = (void *) &aux;
  aux.abfd = abfd;
  aux.require_sec = false;
-  aux.dynrelbuf = NULL;
-  aux.dynrelcount = 0;
+  disasm_info.dynrelbuf = NULL;
+  disasm_info.dynrelcount = 0;
  aux.reloc = NULL;
  aux.symbol = disasm_sym;

@ -3519,33 +3517,31 @@ disassemble_data (bfd *abfd)
  disassemble_init_for_target (& disasm_info);

  /* Pre-load the dynamic relocs as we may need them during the disassembly.  */
-    {
-      long relsize = bfd_get_dynamic_reloc_upper_bound (abfd);
+  long relsize = bfd_get_dynamic_reloc_upper_bound (abfd);

-      if (relsize < 0 && dump_dynamic_reloc_info)
-	bfd_fatal (bfd_get_filename (abfd));
+  if (relsize < 0 && dump_dynamic_reloc_info)
+    bfd_fatal (bfd_get_filename (abfd));

-      if (relsize > 0)
-	{
-	  aux.dynrelbuf = (arelent **) xmalloc (relsize);
-	  aux.dynrelcount = bfd_canonicalize_dynamic_reloc (abfd,
-							    aux.dynrelbuf,
-							    dynsyms);
-	  if (aux.dynrelcount < 0)
-	    bfd_fatal (bfd_get_filename (abfd));
+  if (relsize > 0)
+    {
+      disasm_info.dynrelbuf = (arelent **) xmalloc (relsize);
+      disasm_info.dynrelcount
+	= bfd_canonicalize_dynamic_reloc (abfd, disasm_info.dynrelbuf, dynsyms);
+      if (disasm_info.dynrelcount < 0)
+	bfd_fatal (bfd_get_filename (abfd));

-	  /* Sort the relocs by address.  */
-	  qsort (aux.dynrelbuf, aux.dynrelcount, sizeof (arelent *),
-		 compare_relocs);
-	}
+      /* Sort the relocs by address.  */
+      qsort (disasm_info.dynrelbuf, disasm_info.dynrelcount, sizeof (arelent *),
+	     compare_relocs);
    }
+
  disasm_info.symtab = sorted_syms;
  disasm_info.symtab_size = sorted_symcount;

  bfd_map_over_sections (abfd, disassemble_section, & disasm_info);

-  if (aux.dynrelbuf != NULL)
-    free (aux.dynrelbuf);
+  free (disasm_info.dynrelbuf);
+  disasm_info.dynrelbuf = NULL;
  free (sorted_syms);
  disassemble_free_target (&disasm_info);
 }
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@ -1,3 +1,9 @@
+2021-04-09  Alan Modra  <amodra@gmail.com>
+
+	* testsuite/gas/ppc/prefix-pcrel.d: Update expected output.
+	* testsuite/gas/ppc/prefix-reloc.d: Likewise.
+	* gas/testsuite/gas/ppc/vsx_32byte.d: Likewise.
+
 2021-04-08  Alan Modra  <amodra@gmail.com>

 	* testsuite/gas/ppc/pr27676.d,
--- a/gas/testsuite/gas/ppc/prefix-pcrel.d
+++ b/gas/testsuite/gas/ppc/prefix-pcrel.d
@ -40,27 +40,27 @@ Disassembly of section \.text:
 .*:	(39 a9 00 00|00 00 a9 39) 
 .*:	(06 02 00 00|00 00 02 06) 	paddi   r13,r9,-8589934592
 .*:	(39 a9 00 00|00 00 a9 39) 
-.*:	(06 10 00 00|00 00 10 06) 	pla     r14,0
+.*:	(06 10 00 00|00 00 10 06) 	pla     r14,0	# 80
 .*:	(39 c0 00 00|00 00 c0 39) 
-.*:	(06 10 00 00|00 00 10 06) 	pla     r14,0
+.*:	(06 10 00 00|00 00 10 06) 	pla     r14,0	# 88
 .*:	(39 c0 00 00|00 00 c0 39) 
-.*:	(06 13 ff ff|ff ff 13 06) 	pla     r15,-32769
+.*:	(06 13 ff ff|ff ff 13 06) 	pla     r15,-32769	# f+808f
 .*:	(39 e0 7f ff|ff 7f e0 39) 
-.*:	(06 13 ff ff|ff ff 13 06) 	pla     r15,-32769
+.*:	(06 13 ff ff|ff ff 13 06) 	pla     r15,-32769	# f+8097
 .*:	(39 e0 7f ff|ff 7f e0 39) 
-.*:	(06 13 ff ff|ff ff 13 06) 	pla     r15,-32769
+.*:	(06 13 ff ff|ff ff 13 06) 	pla     r15,-32769	# f+809f
 .*:	(39 e0 7f ff|ff 7f e0 39) 
-.*:	(06 11 ff ff|ff ff 11 06) 	pla     r16,8589934591
+.*:	(06 11 ff ff|ff ff 11 06) 	pla     r16,8589934591	# 2000000a7
 .*:	(3a 00 ff ff|ff ff 00 3a) 
-.*:	(06 11 ff ff|ff ff 11 06) 	pla     r16,8589934591
+.*:	(06 11 ff ff|ff ff 11 06) 	pla     r16,8589934591	# 2000000af
 .*:	(3a 00 ff ff|ff ff 00 3a) 
-.*:	(06 11 ff ff|ff ff 11 06) 	pla     r16,8589934591
+.*:	(06 11 ff ff|ff ff 11 06) 	pla     r16,8589934591	# 2000000b7
 .*:	(3a 00 ff ff|ff ff 00 3a) 
-.*:	(06 12 00 00|00 00 12 06) 	pla     r17,-8589934592
+.*:	(06 12 00 00|00 00 12 06) 	pla     r17,-8589934592	# f+e000000c0
 .*:	(3a 20 00 00|00 00 20 3a) 
-.*:	(06 12 00 00|00 00 12 06) 	pla     r17,-8589934592
+.*:	(06 12 00 00|00 00 12 06) 	pla     r17,-8589934592	# f+e000000c8
 .*:	(3a 20 00 00|00 00 20 3a) 
-.*:	(06 12 00 00|00 00 12 06) 	pla     r17,-8589934592
+.*:	(06 12 00 00|00 00 12 06) 	pla     r17,-8589934592	# f+e000000d0
 .*:	(3a 20 00 00|00 00 20 3a) 
 .*:	(06 00 00 00|00 00 00 06) 	pli     r20,13
 .*:	(3a 80 00 0d|0d 00 80 3a) 
@ -118,118 +118,118 @@ Disassembly of section \.text:
 .*:	(88 61 00 00|00 00 61 88) 
 .*:	(06 00 00 00|00 00 00 06) 	plbz    r3,0\(0\)
 .*:	(88 60 00 00|00 00 60 88) 
-.*:	(06 10 00 00|00 00 10 06) 	plbz    r4,0
+.*:	(06 10 00 00|00 00 10 06) 	plbz    r4,0	# 1b8
 .*:	(88 80 00 00|00 00 80 88) 
-.*:	(06 10 00 00|00 00 10 06) 	plbz    r4,0
+.*:	(06 10 00 00|00 00 10 06) 	plbz    r4,0	# 1c0
 .*:	(88 80 00 00|00 00 80 88) 
 .*:	(06 03 ff ff|ff ff 03 06) 	plbz    r3,-32769\(0\)
 .*:	(88 60 7f ff|ff 7f 60 88) 
-.*:	(06 13 ff ff|ff ff 13 06) 	plbz    r4,-32769
+.*:	(06 13 ff ff|ff ff 13 06) 	plbz    r4,-32769	# f+81cf
 .*:	(88 80 7f ff|ff 7f 80 88) 
-.*:	(06 13 ff ff|ff ff 13 06) 	plbz    r4,-32769
+.*:	(06 13 ff ff|ff ff 13 06) 	plbz    r4,-32769	# f+81d7
 .*:	(88 80 7f ff|ff 7f 80 88) 
 .*:	(06 01 ff ff|ff ff 01 06) 	plbz    r3,8589934591\(0\)
 .*:	(88 60 ff ff|ff ff 60 88) 
-.*:	(06 11 ff ff|ff ff 11 06) 	plbz    r4,8589934591
+.*:	(06 11 ff ff|ff ff 11 06) 	plbz    r4,8589934591	# 2000001e7
 .*:	(88 80 ff ff|ff ff 80 88) 
-.*:	(06 11 ff ff|ff ff 11 06) 	plbz    r4,8589934591
+.*:	(06 11 ff ff|ff ff 11 06) 	plbz    r4,8589934591	# 2000001ef
 .*:	(88 80 ff ff|ff ff 80 88) 
 .*:	(06 02 00 00|00 00 02 06) 	plbz    r3,-8589934592\(0\)
 .*:	(88 60 00 00|00 00 60 88) 
-.*:	(06 12 00 00|00 00 12 06) 	plbz    r4,-8589934592
+.*:	(06 12 00 00|00 00 12 06) 	plbz    r4,-8589934592	# f+e00000200
 .*:	(88 80 00 00|00 00 80 88) 
-.*:	(06 12 00 00|00 00 12 06) 	plbz    r4,-8589934592
+.*:	(06 12 00 00|00 00 12 06) 	plbz    r4,-8589934592	# f+e00000208
 .*:	(88 80 00 00|00 00 80 88) 
 .*:	(06 00 00 00|00 00 00 06) 	plhz    r5,4\(r10\)
 .*:	(a0 aa 00 04|04 00 aa a0) 
-.*:	(06 10 00 00|00 00 10 06) 	plhz    r5,4
+.*:	(06 10 00 00|00 00 10 06) 	plhz    r5,4	# 21c
 .*:	(a0 a0 00 04|04 00 a0 a0) 
 .*:	(06 00 00 00|00 00 00 06) 	plha    r6,8\(r10\)
 .*:	(a8 ca 00 08|08 00 ca a8) 
-.*:	(06 10 00 00|00 00 10 06) 	plha    r6,8
+.*:	(06 10 00 00|00 00 10 06) 	plha    r6,8	# 230
 .*:	(a8 c0 00 08|08 00 c0 a8) 
 .*:	(06 00 00 00|00 00 00 06) 	plwz    r7,12\(r10\)
 .*:	(80 ea 00 0c|0c 00 ea 80) 
-.*:	(06 10 00 00|00 00 10 06) 	plwz    r7,12
+.*:	(06 10 00 00|00 00 10 06) 	plwz    r7,12	# 244
 .*:	(80 e0 00 0c|0c 00 e0 80) 
 .*:	(04 00 00 00|00 00 00 04) 	plwa    r8,16\(r10\)
 .*:	(a5 0a 00 10|10 00 0a a5) 
-.*:	(04 10 00 00|00 00 10 04) 	plwa    r8,16
+.*:	(04 10 00 00|00 00 10 04) 	plwa    r8,16	# 258
 .*:	(a5 00 00 10|10 00 00 a5) 
 .*:	(04 00 00 00|00 00 00 04) 	pld     r9,20\(r10\)
 .*:	(e5 2a 00 14|14 00 2a e5) 
-.*:	(04 10 00 00|00 00 10 04) 	pld     r9,20
+.*:	(04 10 00 00|00 00 10 04) 	pld     r9,20	# 26c
 .*:	(e5 20 00 14|14 00 20 e5) 
 .*:	(06 00 00 00|00 00 00 06) 	plfs    f10,24\(r10\)
 .*:	(c1 4a 00 18|18 00 4a c1) 
-.*:	(06 10 00 00|00 00 10 06) 	plfs    f10,24
+.*:	(06 10 00 00|00 00 10 06) 	plfs    f10,24	# 280
 .*:	(c1 40 00 18|18 00 40 c1) 
 .*:	(06 00 00 00|00 00 00 06) 	plfd    f11,28\(r10\)
 .*:	(c9 6a 00 1c|1c 00 6a c9) 
-.*:	(06 10 00 00|00 00 10 06) 	plfd    f11,28
+.*:	(06 10 00 00|00 00 10 06) 	plfd    f11,28	# 294
 .*:	(c9 60 00 1c|1c 00 60 c9) 
 .*:	(04 00 00 00|00 00 00 04) 	plxsd   v13,36\(r10\)
 .*:	(a9 aa 00 24|24 00 aa a9) 
-.*:	(04 10 00 00|00 00 10 04) 	plxsd   v13,36
+.*:	(04 10 00 00|00 00 10 04) 	plxsd   v13,36	# 2ac
 .*:	(a9 a0 00 24|24 00 a0 a9) 
 .*:	(04 00 00 00|00 00 00 04) 	plxssp  v14,40\(r10\)
 .*:	(ad ca 00 28|28 00 ca ad) 
-.*:	(04 10 00 00|00 00 10 04) 	plxssp  v14,40
+.*:	(04 10 00 00|00 00 10 04) 	plxssp  v14,40	# 2c0
 .*:	(ad c0 00 28|28 00 c0 ad) 
 .*:	(04 00 00 00|00 00 00 04) 	plq     r16,48\(r10\)
 .*:	(e2 0a 00 30|30 00 0a e2) 
-.*:	(04 10 00 00|00 00 10 04) 	plq     r16,48
+.*:	(04 10 00 00|00 00 10 04) 	plq     r16,48	# 2d8
 .*:	(e2 00 00 30|30 00 00 e2) 
 .*:	(04 00 00 00|00 00 00 04) 	plxv    vs17,64\(r10\)
 .*:	(ca 2a 00 40|40 00 2a ca) 
-.*:	(04 10 00 00|00 00 10 04) 	plxv    vs17,64
+.*:	(04 10 00 00|00 00 10 04) 	plxv    vs17,64	# 2f8
 .*:	(ca 20 00 40|40 00 20 ca) 
 .*:	(04 00 00 00|00 00 00 04) 	plxv    vs34,64\(r10\)
 .*:	(cc 4a 00 40|40 00 4a cc) 
-.*:	(04 10 00 00|00 00 10 04) 	plxv    vs34,64
+.*:	(04 10 00 00|00 00 10 04) 	plxv    vs34,64	# 308
 .*:	(cc 40 00 40|40 00 40 cc) 
 .*:	(06 00 00 00|00 00 00 06) 	pstb    r3,52\(r11\)
 .*:	(98 6b 00 34|34 00 6b 98) 
-.*:	(06 10 00 00|00 00 10 06) 	pstb    r3,52
+.*:	(06 10 00 00|00 00 10 06) 	pstb    r3,52	# 30c
 .*:	(98 60 00 34|34 00 60 98) 
 .*:	(06 00 00 00|00 00 00 06) 	psth    r4,56\(r11\)
 .*:	(b0 8b 00 38|38 00 8b b0) 
-.*:	(06 10 00 00|00 00 10 06) 	psth    r4,56
+.*:	(06 10 00 00|00 00 10 06) 	psth    r4,56	# 320
 .*:	(b0 80 00 38|38 00 80 b0) 
 .*:	(06 00 00 00|00 00 00 06) 	pstw    r5,60\(r11\)
 .*:	(90 ab 00 3c|3c 00 ab 90) 
-.*:	(06 10 00 00|00 00 10 06) 	pstw    r5,60
+.*:	(06 10 00 00|00 00 10 06) 	pstw    r5,60	# 334
 .*:	(90 a0 00 3c|3c 00 a0 90) 
 .*:	(06 00 00 00|00 00 00 06) 	pstfs   f6,64\(r11\)
 .*:	(d0 cb 00 40|40 00 cb d0) 
-.*:	(06 10 00 00|00 00 10 06) 	pstfs   f6,64
+.*:	(06 10 00 00|00 00 10 06) 	pstfs   f6,64	# 348
 .*:	(d0 c0 00 40|40 00 c0 d0) 
 .*:	(06 00 00 00|00 00 00 06) 	pstfd   f7,68\(r11\)
 .*:	(d8 eb 00 44|44 00 eb d8) 
-.*:	(06 10 00 00|00 00 10 06) 	pstfd   f7,68
+.*:	(06 10 00 00|00 00 10 06) 	pstfd   f7,68	# 35c
 .*:	(d8 e0 00 44|44 00 e0 d8) 
 .*:	(04 00 00 00|00 00 00 04) 	pstxsd  v9,76\(r11\)
 .*:	(b9 2b 00 4c|4c 00 2b b9) 
-.*:	(04 10 00 00|00 00 10 04) 	pstxsd  v9,76
+.*:	(04 10 00 00|00 00 10 04) 	pstxsd  v9,76	# 374
 .*:	(b9 20 00 4c|4c 00 20 b9) 
 .*:	(04 00 00 00|00 00 00 04) 	pstxssp v10,80\(r11\)
 .*:	(bd 4b 00 50|50 00 4b bd) 
-.*:	(04 10 00 00|00 00 10 04) 	pstxssp v10,80
+.*:	(04 10 00 00|00 00 10 04) 	pstxssp v10,80	# 388
 .*:	(bd 40 00 50|50 00 40 bd) 
 .*:	(04 00 00 00|00 00 00 04) 	pstd    r11,84\(r11\)
 .*:	(f5 6b 00 54|54 00 6b f5) 
-.*:	(04 10 00 00|00 00 10 04) 	pstd    r11,84
+.*:	(04 10 00 00|00 00 10 04) 	pstd    r11,84	# 39c
 .*:	(f5 60 00 54|54 00 60 f5) 
 .*:	(04 00 00 00|00 00 00 04) 	pstq    r12,88\(r11\)
 .*:	(f1 8b 00 58|58 00 8b f1) 
-.*:	(04 10 00 00|00 00 10 04) 	pstq    r12,88
+.*:	(04 10 00 00|00 00 10 04) 	pstq    r12,88	# 3b0
 .*:	(f1 80 00 58|58 00 80 f1) 
 .*:	(04 00 00 00|00 00 00 04) 	pstxv   vs13,96\(r11\)
 .*:	(d9 ab 00 60|60 00 ab d9) 
-.*:	(04 10 00 00|00 00 10 04) 	pstxv   vs13,96
+.*:	(04 10 00 00|00 00 10 04) 	pstxv   vs13,96	# 3c8
 .*:	(d9 a0 00 60|60 00 a0 d9) 
 .*:	(04 00 00 00|00 00 00 04) 	pstxv   vs63,96\(r11\)
 .*:	(df eb 00 60|60 00 eb df) 
-.*:	(04 10 00 00|00 00 10 04) 	pstxv   vs63,96
+.*:	(04 10 00 00|00 00 10 04) 	pstxv   vs63,96	# 3d8
 .*:	(df e0 00 60|60 00 e0 df) 
 #pass
--- a/gas/testsuite/gas/ppc/prefix-reloc.d
+++ b/gas/testsuite/gas/ppc/prefix-reloc.d
@ -14,22 +14,22 @@ Disassembly of section \.text:
   c:	(00 00 00 06|06 00 00 00) 	paddi   r9,r9,0
  10:	(00 00 29 39|39 29 00 00) 
 			c: R_PPC64_D34_LO	ext
-  14:	(00 00 10 04|04 10 00 00) 	pld     r3,0
+  14:	(00 00 10 04|04 10 00 00) 	pld     r3,0	# 14
  18:	(00 00 60 e4|e4 60 00 00) 
 			14: R_PPC64_PCREL34	ext
-  1c:	(00 00 10 04|04 10 00 00) 	pld     r4,0
+  1c:	(00 00 10 04|04 10 00 00) 	pld     r4,0	# 1c
  20:	(00 00 80 e4|e4 80 00 00) 
 			1c: R_PPC64_GOT_PCREL34	ext
-  24:	(00 00 10 04|04 10 00 00) 	pld     r5,0
+  24:	(00 00 10 04|04 10 00 00) 	pld     r5,0	# 24
  28:	(00 00 a0 e4|e4 a0 00 00) 
 			24: R_PPC64_PLT_PCREL34	ext
-  2c:	(00 00 10 04|04 10 00 00) 	pld     r6,0
+  2c:	(00 00 10 04|04 10 00 00) 	pld     r6,0	# 2c
  30:	(00 00 c0 e4|e4 c0 00 00) 
 			2c: R_PPC64_PCREL34	ext
  34:	(00 00 00 04|04 00 00 00) 	pld     r7,0\(0\)
  38:	(00 00 e0 e4|e4 e0 00 00) 
 			34: R_PPC64_D34	ext
  3c:	(00 00 00 60|60 00 00 00) 	nop
-  40:	(00 00 10 04|04 10 00 00) 	pld     r8,0
+  40:	(00 00 10 04|04 10 00 00) 	pld     r8,0	# 40
  44:	(00 00 00 e5|e5 00 00 00) 
 			40: R_PPC64_PCREL34	ext
--- a/gas/testsuite/gas/ppc/vsx_32byte.d
+++ b/gas/testsuite/gas/ppc/vsx_32byte.d
@ -14,9 +14,9 @@ Disassembly of section \.text:
 .*:	(e8 9e 00 01|01 00 9e e8) 
 .*:	(04 03 ff ff|ff ff 03 04) 	plxvp   vs60,-1\(r9\)
 .*:	(eb a9 ff ff|ff ff a9 eb) 
-.*:	(04 10 12 34|34 12 10 04) 	plxvp   vs6,305419896
+.*:	(04 10 12 34|34 12 10 04) 	plxvp   vs6,305419896	# 12345690
 .*:	(e8 c0 56 78|78 56 c0 e8) 
-.*:	(04 13 ff ff|ff ff 13 04) 	plxvp   vs58,-32
+.*:	(04 13 ff ff|ff ff 13 04) 	plxvp   vs58,-32	# 0 <_start>
 .*:	(eb 60 ff e0|e0 ff 60 eb) 
 .*:	(7f 20 0a 9a|9a 0a 20 7f) 	lxvpx   vs56,0,r1
 .*:	(19 1d 00 01|01 00 1d 19) 	stxvp   vs8,0\(r29\)
@ -26,8 +26,8 @@ Disassembly of section \.text:
 .*:	(60 00 00 00|00 00 00 60) 	nop
 .*:	(04 03 ff ff|ff ff 03 04) 	pstxvp  vs52,-1\(r8\)
 .*:	(fa a8 ff ff|ff ff a8 fa) 
-.*:	(04 10 12 34|34 12 10 04) 	pstxvp  vs12,305419896
+.*:	(04 10 12 34|34 12 10 04) 	pstxvp  vs12,305419896	# 123456c0
 .*:	(f9 80 56 78|78 56 80 f9) 
-.*:	(04 13 ff ff|ff ff 13 04) 	pstxvp  vs50,-80
+.*:	(04 13 ff ff|ff ff 13 04) 	pstxvp  vs50,-80	# 0 <_start>
 .*:	(fa 60 ff b0|b0 ff 60 fa) 
 .*:	(7e 20 0b 9a|9a 0b 20 7e) 	stxvpx  vs48,0,r1
--- a/include/ChangeLog
+++ b/include/ChangeLog
@ -1,3 +1,7 @@
+2021-04-09  Alan Modra  <amodra@gmail.com>
+
+	* dis-asm.h (struct disassemble_info): Add dynrelbuf and dynrelcount.
+
 2021-04-06  Alan Modra  <amodra@gmail.com>

 	* dis-asm.h (struct disassemble_info <symbol_at_address_func>):
--- a/include/dis-asm.h
+++ b/include/dis-asm.h
@ -114,6 +114,10 @@ typedef struct disassemble_info
  /* Set if the user has requested wide output.  */
 #define WIDE_OUTPUT (1u << 28)

+  /* Dynamic relocations, if they have been loaded.  */
+  arelent **dynrelbuf;
+  long dynrelcount;
+
  /* Use internally by the target specific disassembly code.  */
  void *private_data;

--- a/ld/ChangeLog
+++ b/ld/ChangeLog
@ -1,3 +1,17 @@
+2021-04-09  Alan Modra  <amodra@gmail.com>
+
+	* testsuite/ld-powerpc/inlinepcrel-1.d: Update expected output.
+	* testsuite/ld-powerpc/inlinepcrel-2.d: Likewise.
+	* testsuite/ld-powerpc/notoc2.d: Likewise.
+	* testsuite/ld-powerpc/notoc3.d: Likewise.
+	* testsuite/ld-powerpc/pcrelopt.d: Likewise.
+	* testsuite/ld-powerpc/startstop.d: Likewise.
+	* testsuite/ld-powerpc/tlsget.d: Likewise.
+	* testsuite/ld-powerpc/tlsget2.d: Likewise.
+	* testsuite/ld-powerpc/tlsld.d: Likewise.
+	* testsuite/ld-powerpc/weak1.d: Likewise.
+	* testsuite/ld-powerpc/weak1so.d: Likewise.
+
 2021-04-06  Jan Beulich  <jbeulich@suse.com>

 	* pe-dll.c (generate_reloc): Bail immediately when .reloc is
--- a/ld/testsuite/ld-powerpc/inlinepcrel-1.d
+++ b/ld/testsuite/ld-powerpc/inlinepcrel-1.d
@ -8,7 +8,7 @@
 Disassembly of section \.text:

 .*:
-.*:	(04 10 00 01|01 00 10 04) 	pld     r12,65944
+.*:	(04 10 00 01|01 00 10 04) 	pld     r12,65944	# 10318 \[my_func@plt\]
 .*:	(e5 80 01 98|98 01 80 e5) 
 .*:	(7d 89 03 a6|a6 03 89 7d) 	mtctr   r12
 .*:	(4e 80 04 21|21 04 80 4e) 	bctrl
--- a/ld/testsuite/ld-powerpc/inlinepcrel-2.d
+++ b/ld/testsuite/ld-powerpc/inlinepcrel-2.d
@ -9,7 +9,7 @@
 Disassembly of section \.text:

 .*:
-.*:	(04 10 00 01|01 00 10 04) 	pld     r12,66072
+.*:	(04 10 00 01|01 00 10 04) 	pld     r12,66072	# 10010418 \[my_func@plt\]
 .*:	(e5 80 02 18|18 02 80 e5) 
 .*:	(7d 89 03 a6|a6 03 89 7d) 	mtctr   r12
 .*:	(4e 80 04 21|21 04 80 4e) 	bctrl
--- a/ld/testsuite/ld-powerpc/notoc2.d
+++ b/ld/testsuite/ld-powerpc/notoc2.d
@ -9,20 +9,20 @@
 Disassembly of section \.text:

 .* <.*\.plt_call\.puts>:
-.*:	(04 10 00 01|01 00 10 04) 	pld     r12,66200
+.*:	(04 10 00 01|01 00 10 04) 	pld     r12,66200	# 10418 \[puts@plt\]
 .*:	(e5 80 02 98|98 02 80 e5) 
 .*:	(7d 89 03 a6|a6 03 89 7d) 	mtctr   r12
 .*:	(4e 80 04 20|20 04 80 4e) 	bctr
 #...
-.*:	(04 13 ff ff|ff ff 13 04) 	pld     r12,-1
+.*:	(04 13 ff ff|ff ff 13 04) 	pld     r12,-1	# 1bf
 .*:	(e5 80 ff ff|ff ff 80 e5) 
-.*:	(04 10 00 00|00 00 10 04) 	pld     r12,0
+.*:	(04 10 00 00|00 00 10 04) 	pld     r12,0	# 1c8
 .*:	(e5 80 00 00|00 00 80 e5) 
-.*:	(06 13 ff ff|ff ff 13 06) 	pla     r12,-1
+.*:	(06 13 ff ff|ff ff 13 06) 	pla     r12,-1	# 1cf
 .*:	(39 80 ff ff|ff ff 80 39) 
-.*:	(06 10 00 00|00 00 10 06) 	pla     r12,0
+.*:	(06 10 00 00|00 00 10 06) 	pla     r12,0	# 1d8
 .*:	(39 80 00 00|00 00 80 39) 
-.*:	(06 10 00 00|00 00 10 06) 	pla     r3,88
+.*:	(06 10 00 00|00 00 10 06) 	pla     r3,88	# 238 <hello>
 .*:	(38 60 00 58|58 00 60 38) 
 .*:	(4b ff ff 99|99 ff ff 4b) 	bl      .* <.*\.plt_call\.puts>
 .*:	(60 00 00 00|00 00 00 60) 	nop
--- a/ld/testsuite/ld-powerpc/notoc3.d
+++ b/ld/testsuite/ld-powerpc/notoc3.d
@ -18,7 +18,7 @@ Disassembly of section \.text:
 .* <.*\.plt_branch\.ext>:
 .*:	(00 20 60 3d|3d 60 20 00) 	lis     r11,8192
 .*:	(00 00 6b 61|61 6b 00 00) 	ori     r11,r11,0
-.*:	(ff ef 13 06|06 13 ef ff) 	pla     r12,-268435736
+.*:	(ff ef 13 06|06 13 ef ff) 	pla     r12,-268435736	# 0
 .*:	(e8 fe 80 39|39 80 fe e8) 
 .*:	(46 17 6b 79|79 6b 17 46) 	rldicr  r11,r11,34,29
 .*:	(14 62 8b 7d|7d 8b 62 14) 	add     r12,r11,r12
@ -30,13 +30,13 @@ Disassembly of section \.text:

 .* <.*\.long_branch\.f2>:
 .*:	(00 00 00 60|60 00 00 00) 	nop
-.*:	(00 00 10 06|06 10 00 00) 	pla     r12,108
+.*:	(00 00 10 06|06 10 00 00) 	pla     r12,108	# .* <f2>
 .*:	(6c 00 80 39|39 80 00 6c) 
 .*:	(.. .. 00 48|48 00 .. ..) 	b       .* <f2>

 .* <.*\.long_branch\.g2>:
 .*:	(00 00 00 60|60 00 00 00) 	nop
-.*:	(00 00 10 06|06 10 00 00) 	pla     r12,144
+.*:	(00 00 10 06|06 10 00 00) 	pla     r12,144	# .* <g2>
 .*:	(90 00 80 39|39 80 00 90) 
 .*:	(.. .. 00 48|48 00 .. ..) 	b       .* <g2>
 #...
--- a/ld/testsuite/ld-powerpc/pcrelopt.d
+++ b/ld/testsuite/ld-powerpc/pcrelopt.d
@ -4,105 +4,105 @@
 Disassembly of section \.text:

 0+10000200 <_start>:
-.*:	(06 10 00 01|01 00 10 06) 	plbz    r3,66320
+.*:	(06 10 00 01|01 00 10 06) 	plbz    r3,66320	# .* <sym>
 .*:	(88 60 03 10|10 03 60 88) 
 .*:	(60 00 00 00|00 00 00 60) 	nop
-.*:	(06 10 00 01|01 00 10 06) 	plhz    r4,66308
+.*:	(06 10 00 01|01 00 10 06) 	plhz    r4,66308	# .* <sym>
 .*:	(a0 80 03 04|04 03 80 a0) 
 .*:	(60 00 00 00|00 00 00 60) 	nop
 .*:	(60 00 00 00|00 00 00 60) 	nop
 .*:	(60 00 00 00|00 00 00 60) 	nop
-.*:	(06 10 00 01|01 00 10 06) 	plha    r3,66288
+.*:	(06 10 00 01|01 00 10 06) 	plha    r3,66288	# .* <sym>
 .*:	(a8 60 02 f0|f0 02 60 a8) 
 .*:	(40 82 ff f4|f4 ff 82 40) 	bne     .*
-.*:	(06 10 00 01|01 00 10 06) 	plwz    r3,66276
+.*:	(06 10 00 01|01 00 10 06) 	plwz    r3,66276	# .* <sym>
 .*:	(80 60 02 e4|e4 02 60 80) 
 .*:	(60 00 00 00|00 00 00 60) 	nop
-.*:	(04 10 00 01|01 00 10 04) 	plwa    r3,66264
+.*:	(04 10 00 01|01 00 10 04) 	plwa    r3,66264	# .* <sym>
 .*:	(a4 60 02 d8|d8 02 60 a4) 
 .*:	(60 00 00 00|00 00 00 60) 	nop
-.*:	(04 10 00 01|01 00 10 04) 	pld     r3,66252
+.*:	(04 10 00 01|01 00 10 04) 	pld     r3,66252	# .* <sym>
 .*:	(e4 60 02 cc|cc 02 60 e4) 
 .*:	(60 00 00 00|00 00 00 60) 	nop
-.*:	(04 10 00 01|01 00 10 04) 	plq     r14,66240
+.*:	(04 10 00 01|01 00 10 04) 	plq     r14,66240	# .* <sym>
 .*:	(e1 c0 02 c0|c0 02 c0 e1) 
 .*:	(60 00 00 00|00 00 00 60) 	nop
-.*:	(06 10 00 01|01 00 10 06) 	plfs    f1,66228
+.*:	(06 10 00 01|01 00 10 06) 	plfs    f1,66228	# .* <sym>
 .*:	(c0 20 02 b4|b4 02 20 c0) 
 .*:	(60 00 00 00|00 00 00 60) 	nop
-.*:	(06 10 00 01|01 00 10 06) 	plfd    f1,66216
+.*:	(06 10 00 01|01 00 10 06) 	plfd    f1,66216	# .* <sym>
 .*:	(c8 20 02 a8|a8 02 20 c8) 
 .*:	(60 00 00 00|00 00 00 60) 	nop
-.*:	(04 10 00 01|01 00 10 04) 	plxsd   v30,66204
+.*:	(04 10 00 01|01 00 10 04) 	plxsd   v30,66204	# .* <sym>
 .*:	(ab c0 02 9c|9c 02 c0 ab) 
 .*:	(60 00 00 00|00 00 00 60) 	nop
-.*:	(04 10 00 01|01 00 10 04) 	plxssp  v31,66192
+.*:	(04 10 00 01|01 00 10 04) 	plxssp  v31,66192	# .* <sym>
 .*:	(af e0 02 90|90 02 e0 af) 
 .*:	(60 00 00 00|00 00 00 60) 	nop
-.*:	(04 10 00 01|01 00 10 04) 	plxv    vs63,66180
+.*:	(04 10 00 01|01 00 10 04) 	plxv    vs63,66180	# .* <sym>
 .*:	(cf e0 02 84|84 02 e0 cf) 
 .*:	(60 00 00 00|00 00 00 60) 	nop
-.*:	(04 10 00 01|01 00 10 04) 	plxv    vs0,66168
+.*:	(04 10 00 01|01 00 10 04) 	plxv    vs0,66168	# .* <sym>
 .*:	(c8 00 02 78|78 02 00 c8) 
 .*:	(60 00 00 00|00 00 00 60) 	nop
-.*:	(06 10 00 01|01 00 10 06) 	pstb    r3,66156
+.*:	(06 10 00 01|01 00 10 06) 	pstb    r3,66156	# .* <sym>
 .*:	(98 60 02 6c|6c 02 60 98) 
 .*:	(60 00 00 00|00 00 00 60) 	nop
-.*:	(06 10 00 01|01 00 10 06) 	psth    r3,66144
+.*:	(06 10 00 01|01 00 10 06) 	psth    r3,66144	# .* <sym>
 .*:	(b0 60 02 60|60 02 60 b0) 
 .*:	(60 00 00 00|00 00 00 60) 	nop
 .*:	(60 00 00 00|00 00 00 60) 	nop
-.*:	(06 10 00 01|01 00 10 06) 	pstw    r3,66128
+.*:	(06 10 00 01|01 00 10 06) 	pstw    r3,66128	# .* <sym>
 .*:	(90 60 02 50|50 02 60 90) 
 .*:	(60 00 00 00|00 00 00 60) 	nop
-.*:	(04 10 00 01|01 00 10 04) 	pstd    r3,66116
+.*:	(04 10 00 01|01 00 10 04) 	pstd    r3,66116	# .* <sym>
 .*:	(f4 60 02 44|44 02 60 f4) 
 .*:	(60 00 00 00|00 00 00 60) 	nop
-.*:	(04 10 00 01|01 00 10 04) 	pstq    r14,66104
+.*:	(04 10 00 01|01 00 10 04) 	pstq    r14,66104	# .* <sym>
 .*:	(f1 c0 02 38|38 02 c0 f1) 
 .*:	(60 00 00 00|00 00 00 60) 	nop
-.*:	(06 10 00 01|01 00 10 06) 	pstfd   f1,66092
+.*:	(06 10 00 01|01 00 10 06) 	pstfd   f1,66092	# .* <sym>
 .*:	(d8 20 02 2c|2c 02 20 d8) 
 .*:	(60 00 00 00|00 00 00 60) 	nop
-.*:	(06 10 00 01|01 00 10 06) 	pstfs   f2,66080
+.*:	(06 10 00 01|01 00 10 06) 	pstfs   f2,66080	# .* <sym>
 .*:	(d0 40 02 20|20 02 40 d0) 
 .*:	(60 00 00 00|00 00 00 60) 	nop
 .*:	(60 00 00 00|00 00 00 60) 	nop
-.*:	(04 10 00 01|01 00 10 04) 	pstxsd  v30,66064
+.*:	(04 10 00 01|01 00 10 04) 	pstxsd  v30,66064	# .* <sym>
 .*:	(bb c0 02 10|10 02 c0 bb) 
 .*:	(60 00 00 00|00 00 00 60) 	nop
-.*:	(04 10 00 01|01 00 10 04) 	pstxssp v31,66052
+.*:	(04 10 00 01|01 00 10 04) 	pstxssp v31,66052	# .* <sym>
 .*:	(bf e0 02 04|04 02 e0 bf) 
 .*:	(60 00 00 00|00 00 00 60) 	nop
-.*:	(04 10 00 01|01 00 10 04) 	pstxv   vs63,66040
+.*:	(04 10 00 01|01 00 10 04) 	pstxv   vs63,66040	# .* <sym>
 .*:	(df e0 01 f8|f8 01 e0 df) 
 .*:	(60 00 00 00|00 00 00 60) 	nop
-.*:	(04 10 00 01|01 00 10 04) 	pstxv   vs0,66028
+.*:	(04 10 00 01|01 00 10 04) 	pstxv   vs0,66028	# .* <sym>
 .*:	(d8 00 01 ec|ec 01 00 d8) 
 .*:	(60 00 00 00|00 00 00 60) 	nop
-.*:	(06 10 00 01|01 00 10 06) 	plbz    r3,70676
+.*:	(06 10 00 01|01 00 10 06) 	plbz    r3,70676	# 10011744
 .*:	(88 60 14 14|14 14 60 88) 
 .*:	(60 00 00 00|00 00 00 60) 	nop
 .*:	(60 00 00 00|00 00 00 60) 	nop
-.*:	(04 10 12 35|35 12 10 04) 	plq     r4,305485896
+.*:	(04 10 12 35|35 12 10 04) 	plq     r4,305485896	# 22355b88
 .*:	(e0 80 58 48|48 58 80 e0) 
 .*:	(07 00 00 00|00 00 00 07) 	pnop
 .*:	(00 00 00 00|00 00 00 00) 
-.*:	(04 10 00 01|01 00 10 04) 	pld     r9,65976
+.*:	(04 10 00 01|01 00 10 04) 	pld     r9,65976	# 10010508 \[i@got\]
 .*:	(e5 20 01 b8|b8 01 20 e5) 
 .*:	(e8 09 00 00|00 00 09 e8) 	ld      r0,0\(r9\)
-.*:	(06 10 00 01|01 00 10 06) 	pla     r7,65972
+.*:	(06 10 00 01|01 00 10 06) 	pla     r7,65972	# .* <sym>
 .*:	(38 e0 01 b4|b4 01 e0 38) 
 .*:	(88 c7 00 00|00 00 c7 88) 	lbz     r6,0\(r7\)
-.*:	(04 10 00 01|01 00 10 04) 	plxvp   vs62,65960
+.*:	(04 10 00 01|01 00 10 04) 	plxvp   vs62,65960	# .* <sym>
 .*:	(eb e0 01 a8|a8 01 e0 eb) 
 .*:	(60 00 00 00|00 00 00 60) 	nop
-.*:	(04 10 00 01|01 00 10 04) 	plxvp   vs0,65948
+.*:	(04 10 00 01|01 00 10 04) 	plxvp   vs0,65948	# .* <sym>
 .*:	(e8 00 01 9c|9c 01 00 e8) 
 .*:	(60 00 00 00|00 00 00 60) 	nop
-.*:	(04 10 00 01|01 00 10 04) 	pstxvp  vs62,65936
+.*:	(04 10 00 01|01 00 10 04) 	pstxvp  vs62,65936	# .* <sym>
 .*:	(fb e0 01 90|90 01 e0 fb) 
 .*:	(60 00 00 00|00 00 00 60) 	nop
-.*:	(04 10 00 01|01 00 10 04) 	pstxvp  vs0,65924
+.*:	(04 10 00 01|01 00 10 04) 	pstxvp  vs0,65924	# .* <sym>
 .*:	(f8 00 01 84|84 01 00 f8) 
 .*:	(60 00 00 00|00 00 00 60) 	nop
--- a/ld/testsuite/ld-powerpc/startstop.d
+++ b/ld/testsuite/ld-powerpc/startstop.d
@ -4,7 +4,7 @@
 Disassembly of section \.text:

 0+140 <_start>:
- 140:	(04 10 00 01|01 00 10 04) 	pld     r3,66000
+ 140:	(04 10 00 01|01 00 10 04) 	pld     r3,66000	# 10310 \[0@got\]
 144:	(e4 60 01 d0|d0 01 60 e4) 
- 148:	(04 10 00 01|01 00 10 04) 	pld     r4,65984
+ 148:	(04 10 00 01|01 00 10 04) 	pld     r4,65984	# 10308 \[0@got\]
 14c:	(e4 80 01 c0|c0 01 80 e4) 
--- a/ld/testsuite/ld-powerpc/tlsget.d
+++ b/ld/testsuite/ld-powerpc/tlsget.d
@ -64,7 +64,7 @@ Disassembly of section \.text:
 .*:	(e8 41 00 18|18 00 41 e8) 	ld      r2,24\(r1\)

 .* <fun>:
-.*:	(06 10 00 00|00 00 10 06) 	pla     r3,8
+.*:	(06 10 00 00|00 00 10 06) 	pla     r3,8.*
 .*:	(38 60 00 08|08 00 60 38) 
 .*:	(4e 80 00 20|20 00 80 4e) 	blr
 .*:	(60 00 00 00|00 00 00 60) 	nop
--- a/ld/testsuite/ld-powerpc/tlsget2.d
+++ b/ld/testsuite/ld-powerpc/tlsget2.d
@ -50,7 +50,7 @@ Disassembly of section \.text:
 .*:	(e8 41 00 18|18 00 41 e8) 	ld      r2,24\(r1\)

 .* <fun>:
-.*:	(06 10 00 00|00 00 10 06) 	pla     r3,8
+.*:	(06 10 00 00|00 00 10 06) 	pla     r3,8.*
 .*:	(38 60 00 08|08 00 60 38) 
 .*:	(4e 80 00 20|20 00 80 4e) 	blr
 .*:	(60 00 00 00|00 00 00 60) 	nop
--- a/ld/testsuite/ld-powerpc/tlsld.d
+++ b/ld/testsuite/ld-powerpc/tlsld.d
@ -20,7 +20,7 @@ Disassembly of section \.text:
 .*:	(60 00 00 00|00 00 00 60) 	nop
 .*:	(06 03 ff ff|ff ff 03 06) 	paddi   r9,r3,-32728
 .*:	(39 23 80 28|28 80 23 39) 
-.*:	(04 10 00 01|01 00 10 04) 	pld     r10,65784
+.*:	(04 10 00 01|01 00 10 04) 	pld     r10,65784	# 10010228 \[f+8030@got\]
 .*:	(e5 40 00 f8|f8 00 40 e5) 
 .*:	(7d 4a 1a 14|14 1a 4a 7d) 	add     r10,r10,r3
 .*:	(60 00 00 00|00 00 00 60) 	nop
--- a/ld/testsuite/ld-powerpc/weak1.d
+++ b/ld/testsuite/ld-powerpc/weak1.d
@ -4,13 +4,13 @@
 Disassembly of section \.text:

 .*0c0 <_start>:
-.*0c0:	(04 10 00 01|01 00 10 04) 	pld     r3,65888
+.*0c0:	(04 10 00 01|01 00 10 04) 	pld     r3,65888	# 10010220 \[0@got\]
 .*0c4:	(e4 60 01 60|60 01 60 e4) 
-.*0c8:	(04 10 00 01|01 00 10 04) 	pld     r3,65856
+.*0c8:	(04 10 00 01|01 00 10 04) 	pld     r3,65856	# 10010208 \[0@got\]
 .*0cc:	(e4 60 01 40|40 01 60 e4) 
-.*0d0:	(04 10 00 01|01 00 10 04) 	pld     r3,65864
+.*0d0:	(04 10 00 01|01 00 10 04) 	pld     r3,65864	# 10010218 \[0@got\]
 .*0d4:	(e4 60 01 48|48 01 60 e4) 
-.*0d8:	(04 10 00 01|01 00 10 04) 	pld     r3,65848
+.*0d8:	(04 10 00 01|01 00 10 04) 	pld     r3,65848	# 10010210 \[0@got\]
 .*0dc:	(e4 60 01 38|38 01 60 e4) 
 .*0e0:	(e8 62 80 20|20 80 62 e8) 	ld      r3,-32736\(r2\)
 .*0e4:	(e8 62 80 08|08 80 62 e8) 	ld      r3,-32760\(r2\)
--- a/ld/testsuite/ld-powerpc/weak1so.d
+++ b/ld/testsuite/ld-powerpc/weak1so.d
@ -4,13 +4,13 @@
 Disassembly of section \.text:

 0+1c0 <_start>:
- 1c0:	(04 10 00 01|01 00 10 04) 	pld     r3,66144
+ 1c0:	(04 10 00 01|01 00 10 04) 	pld     r3,66144	# 10420 \[x1@got\]
 1c4:	(e4 60 02 60|60 02 60 e4) 
- 1c8:	(04 10 00 01|01 00 10 04) 	pld     r3,66112
+ 1c8:	(04 10 00 01|01 00 10 04) 	pld     r3,66112	# 10408 \[0@got\]
 1cc:	(e4 60 02 40|40 02 60 e4) 
- 1d0:	(04 10 00 01|01 00 10 04) 	pld     r3,66120
+ 1d0:	(04 10 00 01|01 00 10 04) 	pld     r3,66120	# 10418 \[0@got\]
 1d4:	(e4 60 02 48|48 02 60 e4) 
- 1d8:	(04 10 00 01|01 00 10 04) 	pld     r3,66104
+ 1d8:	(04 10 00 01|01 00 10 04) 	pld     r3,66104	# 10410 \[0@got\]
 1dc:	(e4 60 02 38|38 02 60 e4) 
 1e0:	(e8 62 80 20|20 80 62 e8) 	ld      r3,-32736\(r2\)
 1e4:	(e8 62 80 08|08 80 62 e8) 	ld      r3,-32760\(r2\)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@ -1,3 +1,15 @@
+2021-04-09  Alan Modra  <amodra@gmail.com>
+
+	* ppc-dis.c (struct dis_private): Add "special".
+	(POWERPC_DIALECT): Delete.  Replace uses with..
+	(private_data): ..this.  New inline function.
+	(disassemble_init_powerpc): Init "special" names.
+	(skip_optional_operands): Add is_pcrel arg, set when detecting R
+	field of prefix instructions.
+	(bsearch_reloc, print_got_plt): New functions.
+	(print_insn_powerpc): For pcrel instructions, print target address
+	and symbol if known, and decode plt and got loads too.
+
 2021-04-08  Alan Modra  <amodra@gmail.com>

 	PR 27684
--- a/opcodes/ppc-dis.c
+++ b/opcodes/ppc-dis.c
@ -40,10 +40,20 @@ struct dis_private
 {
  /* Stash the result of parsing disassembler_options here.  */
  ppc_cpu_t dialect;
+
+  /* .got and .plt sections.  NAME is set to NULL if not present.  */
+  struct sec_buf {
+    asection *sec;
+    bfd_byte *buf;
+    const char *name;
+  } special[2];
 };

-#define POWERPC_DIALECT(INFO) \
-  (((struct dis_private *) ((INFO)->private_data))->dialect)
+static inline struct dis_private *
+private_data (struct disassemble_info *info)
+{
+  return (struct dis_private *) info->private_data;
+}

 struct ppc_mopt {
  /* Option string, without -m or -M prefix.  */
@ -270,7 +280,7 @@ get_powerpc_dialect (struct disassemble_info *info)
  ppc_cpu_t dialect = 0;

  if (info->private_data)
-    dialect = POWERPC_DIALECT (info);
+    dialect = private_data (info)->dialect;

  /* Disassemble according to the section headers flags for VLE-mode.  */
  if (dialect & PPC_OPCODE_VLE
@ -387,7 +397,7 @@ powerpc_init_dialect (struct disassemble_info *info)
    }

  info->private_data = priv;
-  POWERPC_DIALECT(info) = dialect;
+  private_data (info)->dialect = dialect;
 }

 #define PPC_OPCD_SEGS (1 + PPC_OP (-1))
@ -409,7 +419,7 @@ ppc_symbol_is_valid (asymbol *sym,
    return false;

  est = elf_symbol_from (sym);
-  
+
  /* Ignore ELF hidden, local, no-type symbols.
     These are generated by annobin.  */
  if (est != NULL
@ -477,6 +487,11 @@ disassemble_init_powerpc (struct disassemble_info *info)
    }

  powerpc_init_dialect (info);
+  if (info->private_data != NULL)
+    {
+      private_data (info)->special[0].name = ".got";
+      private_data (info)->special[1].name = ".plt";
+    }
 }

 /* Print a big endian PowerPC instruction.  */
@ -532,7 +547,7 @@ operand_value_powerpc (const struct powerpc_operand *operand,

 static bool
 skip_optional_operands (const unsigned char *opindex,
-			uint64_t insn, ppc_cpu_t dialect)
+			uint64_t insn, ppc_cpu_t dialect, bool *is_pcrel)
 {
  const struct powerpc_operand *operand;
  int num_optional;
@ -544,11 +559,15 @@ skip_optional_operands (const unsigned char *opindex,
 	return false;
      if ((operand->flags & PPC_OPERAND_OPTIONAL) != 0)
 	{
+	  int64_t value = operand_value_powerpc (operand, insn, dialect);
+
+	  if (operand->shift == 52)
+	    *is_pcrel = value != 0;
+
 	  /* Negative count is used as a flag to extract function.  */
 	  --num_optional;
-	  if (operand_value_powerpc (operand, insn, dialect)
-	      != ppc_optional_operand_value (operand, insn, dialect,
-					     num_optional))
+	  if (value != ppc_optional_operand_value (operand, insn, dialect,
+						   num_optional))
 	    return false;
 	}
    }
@ -764,6 +783,75 @@ lookup_spe2 (uint64_t insn)
  return NULL;
 }

+static arelent *
+bsearch_reloc (arelent **lo, arelent **hi, bfd_vma vma)
+{
+  while (lo < hi)
+    {
+      arelent **mid = lo + (hi - lo) / 2;
+      arelent *rel = *mid;
+
+      if (vma < rel->address)
+	hi = mid;
+      else if (vma > rel->address)
+	lo = mid + 1;
+      else
+	return rel;
+    }
+  return NULL;
+}
+
+static bool
+print_got_plt (struct sec_buf *sb, uint64_t vma, struct disassemble_info *info)
+{
+  if (sb->name != NULL)
+    {
+      asection *s = sb->sec;
+      if (s == NULL)
+	{
+	  s = bfd_get_section_by_name (info->section->owner, sb->name);
+	  sb->sec = s;
+	  if (s == NULL)
+	    sb->name = NULL;
+	}
+      if (s != NULL
+	  && vma >= s->vma
+	  && vma < s->vma + s->size)
+	{
+	  asymbol *sym = NULL;
+	  uint64_t ent = 0;
+	  if (info->dynrelcount > 0)
+	    {
+	      arelent **lo = info->dynrelbuf;
+	      arelent **hi = lo + info->dynrelcount;
+	      arelent *rel = bsearch_reloc (lo, hi, vma);
+	      if (rel != NULL && rel->sym_ptr_ptr != NULL)
+		sym = *rel->sym_ptr_ptr;
+	    }
+	  if (sym == NULL && (s->flags & SEC_HAS_CONTENTS) != 0)
+	    {
+	      if (sb->buf == NULL
+		  && !bfd_malloc_and_get_section (s->owner, s, &sb->buf))
+		sb->name = NULL;
+	      if (sb->buf != NULL)
+		{
+		  ent = bfd_get_64 (s->owner, sb->buf + (vma - s->vma));
+		  if (ent != 0)
+		    sym = (*info->symbol_at_address_func) (ent, info);
+		}
+	    }
+	  if (sym != NULL)
+	    (*info->fprintf_func) (info->stream, " [%s@%s]",
+				   bfd_asymbol_name (sym), sb->name + 1);
+	  else
+	    (*info->fprintf_func) (info->stream, " [%" PRIx64 "@%s]",
+				   ent, sb->name + 1);
+	  return true;
+	}
+    }
+  return false;
+}
+
 /* Print a PowerPC or POWER instruction.  */

 static int
@ -862,6 +950,8 @@ print_insn_powerpc (bfd_vma memaddr,
 	need_paren
      } op_separator;
      bool skip_optional;
+      bool is_pcrel;
+      uint64_t d34;
      int blanks;

      (*info->fprintf_func) (info->stream, "%s", opcode->name);
@ -873,6 +963,8 @@ print_insn_powerpc (bfd_vma memaddr,
      /* Now extract and print the operands.  */
      op_separator = blanks;
      skip_optional = false;
+      is_pcrel = false;
+      d34 = 0;
      for (opindex = opcode->operands; *opindex != 0; opindex++)
 	{
 	  int64_t value;
@ -886,7 +978,8 @@ print_insn_powerpc (bfd_vma memaddr,
 	      && (dialect & PPC_OPCODE_RAW) == 0)
 	    {
 	      if (!skip_optional)
-		skip_optional = skip_optional_operands (opindex, insn, dialect);
+		skip_optional = skip_optional_operands (opindex, insn,
+							dialect, &is_pcrel);
 	      if (skip_optional)
 		continue;
 	    }
@ -945,6 +1038,11 @@ print_insn_powerpc (bfd_vma memaddr,
 	  else
 	    (*info->fprintf_func) (info->stream, "%" PRId64, value);

+	  if (operand->shift == 52)
+	    is_pcrel = value != 0;
+	  else if (operand->bitm == UINT64_C (0x3ffffffff))
+	    d34 = value;
+
 	  if (op_separator == need_paren)
 	    (*info->fprintf_func) (info->stream, ")");

@ -953,6 +1051,29 @@ print_insn_powerpc (bfd_vma memaddr,
 	    op_separator = need_paren;
 	}

+      if (is_pcrel)
+	{
+	  d34 += memaddr;
+	  (*info->fprintf_func) (info->stream, "\t# %" PRIx64, d34);
+	  asymbol *sym = (*info->symbol_at_address_func) (d34, info);
+	  if (sym)
+	    (*info->fprintf_func) (info->stream, " <%s>",
+				   bfd_asymbol_name (sym));
+
+	  if (info->private_data != NULL
+	      && info->section != NULL
+	      && info->section->owner != NULL
+	      && (bfd_get_file_flags (info->section->owner)
+		  & (EXEC_P | DYNAMIC)) != 0
+	      && ((insn & ((-1ULL << 50) | (0x3fULL << 26)))
+		  == ((1ULL << 58) | (1ULL << 52) | (57ULL << 26)) /* pld */))
+	    {
+	      for (int i = 0; i < 2; i++)
+		if (print_got_plt (private_data (info)->special + i, d34, info))
+		  break;
+	    }
+	}
+
      /* We have found and printed an instruction.  */
      return insn_length;
    }