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* elf32-mep.c (config_names): Regenerate configuration. 

* mep-asm.c: Regenerate.
* mep-desc.c: Regenerate.
* mep-desc.h: Regenerate.
* mep-dis.c: Regenerate.
* mep-ibld.c: Regenerate.
* mep-opc.c: Regenerate.
* mep-opc.h: Regenerate.
cgen-1_1-branch
DJ Delorie 18 years ago
parent
bfa149ac1e
commit
c1a0a41faa
10 changed files with 426 additions and 1341 deletions
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  1. 4
      bfd/ChangeLog
  2. 3
      bfd/elf32-mep.c
  3. 10
      opcodes/ChangeLog
  4. 37
      opcodes/mep-asm.c
  5. 1136
      opcodes/mep-desc.c
  6. 33
      opcodes/mep-desc.h
  7. 39
      opcodes/mep-dis.c
  8. 211
      opcodes/mep-ibld.c
  9. 268
      opcodes/mep-opc.c
  10. 26
      opcodes/mep-opc.h

4
bfd/ChangeLog
View File

@ -1,3 +1,7 @@
2009-02-02 DJ Delorie <dj@redhat.com>
* elf32-mep.c (config_names): Regenerate configuration.
2009-02-02 Alan Modra <amodra@bigpond.net.au>
* elf-bfd.h (bfd_elf_get_str_section): Don't declare.

3
bfd/elf32-mep.c
View File

@ -684,8 +684,7 @@ static const char * config_names[] =
{
"basic"
/* start-mepcfgtool */
,"simple"
,"fmax"
,"default"
/* end-mepcfgtool */
};

10
opcodes/ChangeLog
View File

@ -1,3 +1,13 @@
2009-02-02 DJ Delorie <dj@redhat.com>
* mep-asm.c: Regenerate.
* mep-desc.c: Regenerate.
* mep-desc.h: Regenerate.
* mep-dis.c: Regenerate.
* mep-ibld.c: Regenerate.
* mep-opc.c: Regenerate.
* mep-opc.h: Regenerate.
2009-01-29 Mark Mitchell <mark@codesourcery.com>
* arm-dis.c (thumb32_opcodes): Correct decoding for qadd, qdadd,

37
opcodes/mep-asm.c
View File

@ -83,22 +83,6 @@ parse_csrn (CGEN_CPU_DESC cd, const char **strp,
}
/* begin-cop-ip-parse-handlers */
static const char *
parse_fmax_cr (CGEN_CPU_DESC cd,
const char **strp,
CGEN_KEYWORD *keyword_table ATTRIBUTE_UNUSED,
long *field)
{
return cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_cr_fmax, field);
}
static const char *
parse_fmax_ccr (CGEN_CPU_DESC cd,
const char **strp,
CGEN_KEYWORD *keyword_table ATTRIBUTE_UNUSED,
long *field)
{
return cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_ccr_fmax, field);
}
/* end-cop-ip-parse-handlers */
const char *
@ -809,27 +793,6 @@ mep_cgen_parse_operand (CGEN_CPU_DESC cd,
case MEP_OPERAND_EXC :
errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_csr, & junk);
break;
case MEP_OPERAND_FMAX_CCRN :
errmsg = parse_fmax_ccr (cd, strp, & mep_cgen_opval_h_ccr, & fields->f_fmax_4_4);
break;
case MEP_OPERAND_FMAX_FRD :
errmsg = parse_fmax_cr (cd, strp, & mep_cgen_opval_h_cr, & fields->f_fmax_frd);
break;
case MEP_OPERAND_FMAX_FRD_INT :
errmsg = parse_fmax_cr (cd, strp, & mep_cgen_opval_h_cr, & fields->f_fmax_frd);
break;
case MEP_OPERAND_FMAX_FRM :
errmsg = parse_fmax_cr (cd, strp, & mep_cgen_opval_h_cr, & fields->f_fmax_frm);
break;
case MEP_OPERAND_FMAX_FRN :
errmsg = parse_fmax_cr (cd, strp, & mep_cgen_opval_h_cr, & fields->f_fmax_frn);
break;
case MEP_OPERAND_FMAX_FRN_INT :
errmsg = parse_fmax_cr (cd, strp, & mep_cgen_opval_h_cr, & fields->f_fmax_frn);
break;
case MEP_OPERAND_FMAX_RM :
errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_gpr, & fields->f_fmax_rm);
break;
case MEP_OPERAND_HI :
errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_csr, & junk);
break;

1136
opcodes/mep-desc.c
View File

File diff suppressed because it is too large

33
opcodes/mep-desc.h
View File

@ -59,7 +59,7 @@ This file is part of the GNU Binutils and/or GDB, the GNU debugger.
#define CGEN_MNEMONIC_OPERANDS
/* Maximum number of fields in an instruction. */
#define CGEN_ACTUAL_MAX_IFMT_OPERANDS 11
#define CGEN_ACTUAL_MAX_IFMT_OPERANDS 9
/* Enums. */
@ -71,14 +71,6 @@ typedef enum major {
, MAJ_12, MAJ_13, MAJ_14, MAJ_15
} MAJOR;
/* Enum declaration for condition opcode enum. */
typedef enum fmax_cond {
FMAX_F, FMAX_U, FMAX_E, FMAX_UE
, FMAX_L, FMAX_UL, FMAX_LE, FMAX_ULE
, FMAX_FI, FMAX_UI, FMAX_EI, FMAX_UEI
, FMAX_LI, FMAX_ULI, FMAX_LEI, FMAX_ULEI
} FMAX_COND;
/* Attributes. */
/* Enum declaration for machine type selection. */
@ -88,8 +80,7 @@ typedef enum mach_attr {
/* Enum declaration for instruction set selection. */
typedef enum isa_attr {
ISA_MEP, ISA_EXT_CORE1, ISA_EXT_CORE2, ISA_EXT_COP2_16
, ISA_EXT_COP2_32, ISA_EXT_COP2_48, ISA_EXT_COP2_64, ISA_MAX
ISA_MEP, ISA_EXT_CORE1, ISA_MAX
} ISA_ATTR;
/* Enum declaration for datatype to use for C intrinsics mapping. */
@ -101,7 +92,7 @@ typedef enum cdata_attr {
/* Enum declaration for . */
typedef enum config_attr {
CONFIG_NONE, CONFIG_SIMPLE, CONFIG_FMAX
CONFIG_NONE, CONFIG_DEFAULT
} CONFIG_ATTR;
/* Number of architecture variants. */
@ -156,11 +147,7 @@ typedef enum ifield_type {
, MEP_F_8S24A4, MEP_F_8S24A8, MEP_F_24U8A4N_HI, MEP_F_24U8A4N_LO
, MEP_F_24U8A4N, MEP_F_24U8N_HI, MEP_F_24U8N_LO, MEP_F_24U8N
, MEP_F_24U4N_HI, MEP_F_24U4N_LO, MEP_F_24U4N, MEP_F_CALLNUM
, MEP_F_CCRN_HI, MEP_F_CCRN_LO, MEP_F_CCRN, MEP_F_FMAX_0_4
, MEP_F_FMAX_4_4, MEP_F_FMAX_8_4, MEP_F_FMAX_12_4, MEP_F_FMAX_16_4
, MEP_F_FMAX_20_4, MEP_F_FMAX_24_4, MEP_F_FMAX_28_1, MEP_F_FMAX_29_1
, MEP_F_FMAX_30_1, MEP_F_FMAX_31_1, MEP_F_FMAX_FRD, MEP_F_FMAX_FRN
, MEP_F_FMAX_FRM, MEP_F_FMAX_RM, MEP_F_MAX
, MEP_F_CCRN_HI, MEP_F_CCRN_LO, MEP_F_CCRN, MEP_F_MAX
} IFIELD_TYPE;
#define MAX_IFLD ((int) MEP_F_MAX)
@ -190,8 +177,7 @@ typedef enum cgen_hw_attr {
typedef enum cgen_hw_type {
HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR
, HW_H_IADDR, HW_H_PC, HW_H_GPR, HW_H_CSR
, HW_H_CR64, HW_H_CR, HW_H_CCR, HW_H_CR_FMAX
, HW_H_CCR_FMAX, HW_H_FMAX_COMPARE_I_P, HW_MAX
, HW_H_CR64, HW_H_CR, HW_H_CCR, HW_MAX
} CGEN_HW_TYPE;
#define MAX_HW ((int) HW_MAX)
@ -245,14 +231,11 @@ typedef enum cgen_operand_type {
, MEP_OPERAND_UIMM4, MEP_OPERAND_UIMM5, MEP_OPERAND_UDISP7, MEP_OPERAND_UDISP7A2
, MEP_OPERAND_UDISP7A4, MEP_OPERAND_UIMM7A4, MEP_OPERAND_UIMM24, MEP_OPERAND_CIMM4
, MEP_OPERAND_CIMM5, MEP_OPERAND_CDISP8, MEP_OPERAND_CDISP8A2, MEP_OPERAND_CDISP8A4
, MEP_OPERAND_CDISP8A8, MEP_OPERAND_ZERO, MEP_OPERAND_CP_FLAG, MEP_OPERAND_FMAX_FRD
, MEP_OPERAND_FMAX_FRN, MEP_OPERAND_FMAX_FRM, MEP_OPERAND_FMAX_FRD_INT, MEP_OPERAND_FMAX_FRN_INT
, MEP_OPERAND_FMAX_CCRN, MEP_OPERAND_FMAX_CIRR, MEP_OPERAND_FMAX_CBCR, MEP_OPERAND_FMAX_CERR
, MEP_OPERAND_FMAX_RM, MEP_OPERAND_FMAX_COMPARE_I_P, MEP_OPERAND_MAX
, MEP_OPERAND_CDISP8A8, MEP_OPERAND_ZERO, MEP_OPERAND_CP_FLAG, MEP_OPERAND_MAX
} CGEN_OPERAND_TYPE;
/* Number of operands types. */
#define MAX_OPERANDS 90
#define MAX_OPERANDS 79
/* Maximum number of operands referenced by any insn. */
#define MAX_OPERAND_INSTANCES 8
@ -332,8 +315,6 @@ extern CGEN_KEYWORD mep_cgen_opval_h_csr;
extern CGEN_KEYWORD mep_cgen_opval_h_cr64;
extern CGEN_KEYWORD mep_cgen_opval_h_cr;
extern CGEN_KEYWORD mep_cgen_opval_h_ccr;
extern CGEN_KEYWORD mep_cgen_opval_h_cr_fmax;
extern CGEN_KEYWORD mep_cgen_opval_h_ccr_fmax;
extern const CGEN_HW_ENTRY mep_cgen_hw_table[];

39
opcodes/mep-dis.c
View File

@ -89,24 +89,6 @@ print_spreg (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, PTR dis_info,
}
/* begin-cop-ip-print-handlers */
static void
print_fmax_cr (CGEN_CPU_DESC cd,
void *dis_info,
CGEN_KEYWORD *keyword_table ATTRIBUTE_UNUSED,
long value,
unsigned int attrs)
{
print_keyword (cd, dis_info, & mep_cgen_opval_h_cr_fmax, value, attrs);
}
static void
print_fmax_ccr (CGEN_CPU_DESC cd,
void *dis_info,
CGEN_KEYWORD *keyword_table ATTRIBUTE_UNUSED,
long value,
unsigned int attrs)
{
print_keyword (cd, dis_info, & mep_cgen_opval_h_ccr_fmax, value, attrs);
}
/* end-cop-ip-print-handlers */
/************************************************************\
@ -584,27 +566,6 @@ mep_cgen_print_operand (CGEN_CPU_DESC cd,
case MEP_OPERAND_EXC :
print_keyword (cd, info, & mep_cgen_opval_h_csr, 0, 0);
break;
case MEP_OPERAND_FMAX_CCRN :
print_fmax_ccr (cd, info, & mep_cgen_opval_h_ccr, fields->f_fmax_4_4, 0);
break;
case MEP_OPERAND_FMAX_FRD :
print_fmax_cr (cd, info, & mep_cgen_opval_h_cr, fields->f_fmax_frd, 0|(1<<CGEN_OPERAND_VIRTUAL));
break;
case MEP_OPERAND_FMAX_FRD_INT :
print_fmax_cr (cd, info, & mep_cgen_opval_h_cr, fields->f_fmax_frd, 0|(1<<CGEN_OPERAND_VIRTUAL));
break;
case MEP_OPERAND_FMAX_FRM :
print_fmax_cr (cd, info, & mep_cgen_opval_h_cr, fields->f_fmax_frm, 0|(1<<CGEN_OPERAND_VIRTUAL));
break;
case MEP_OPERAND_FMAX_FRN :
print_fmax_cr (cd, info, & mep_cgen_opval_h_cr, fields->f_fmax_frn, 0|(1<<CGEN_OPERAND_VIRTUAL));
break;
case MEP_OPERAND_FMAX_FRN_INT :
print_fmax_cr (cd, info, & mep_cgen_opval_h_cr, fields->f_fmax_frn, 0|(1<<CGEN_OPERAND_VIRTUAL));
break;
case MEP_OPERAND_FMAX_RM :
print_keyword (cd, info, & mep_cgen_opval_h_gpr, fields->f_fmax_rm, 0);
break;
case MEP_OPERAND_HI :
print_keyword (cd, info, & mep_cgen_opval_h_csr, 0, 0);
break;

211
opcodes/mep-ibld.c
View File

@ -737,82 +737,6 @@ mep_cgen_insert_operand (CGEN_CPU_DESC cd,
break;
case MEP_OPERAND_EXC :
break;
case MEP_OPERAND_FMAX_CCRN :
errmsg = insert_normal (cd, fields->f_fmax_4_4, 0, 0, 4, 4, 32, total_length, buffer);
break;
case MEP_OPERAND_FMAX_FRD :
{
{
FLD (f_fmax_4_4) = ((FLD (f_fmax_frd)) & (15));
FLD (f_fmax_28_1) = ((unsigned int) (FLD (f_fmax_frd)) >> (4));
}
errmsg = insert_normal (cd, fields->f_fmax_28_1, 0, 0, 28, 1, 32, total_length, buffer);
if (errmsg)
break;
errmsg = insert_normal (cd, fields->f_fmax_4_4, 0, 0, 4, 4, 32, total_length, buffer);
if (errmsg)
break;
}
break;
case MEP_OPERAND_FMAX_FRD_INT :
{
{
FLD (f_fmax_4_4) = ((FLD (f_fmax_frd)) & (15));
FLD (f_fmax_28_1) = ((unsigned int) (FLD (f_fmax_frd)) >> (4));
}
errmsg = insert_normal (cd, fields->f_fmax_28_1, 0, 0, 28, 1, 32, total_length, buffer);
if (errmsg)
break;
errmsg = insert_normal (cd, fields->f_fmax_4_4, 0, 0, 4, 4, 32, total_length, buffer);
if (errmsg)
break;
}
break;
case MEP_OPERAND_FMAX_FRM :
{
{
FLD (f_fmax_24_4) = ((FLD (f_fmax_frm)) & (15));
FLD (f_fmax_30_1) = ((unsigned int) (FLD (f_fmax_frm)) >> (4));
}
errmsg = insert_normal (cd, fields->f_fmax_30_1, 0, 0, 30, 1, 32, total_length, buffer);
if (errmsg)
break;
errmsg = insert_normal (cd, fields->f_fmax_24_4, 0, 0, 24, 4, 32, total_length, buffer);
if (errmsg)
break;
}
break;
case MEP_OPERAND_FMAX_FRN :
{
{
FLD (f_fmax_20_4) = ((FLD (f_fmax_frn)) & (15));
FLD (f_fmax_29_1) = ((unsigned int) (FLD (f_fmax_frn)) >> (4));
}
errmsg = insert_normal (cd, fields->f_fmax_29_1, 0, 0, 29, 1, 32, total_length, buffer);
if (errmsg)
break;
errmsg = insert_normal (cd, fields->f_fmax_20_4, 0, 0, 20, 4, 32, total_length, buffer);
if (errmsg)
break;
}
break;
case MEP_OPERAND_FMAX_FRN_INT :
{
{
FLD (f_fmax_20_4) = ((FLD (f_fmax_frn)) & (15));
FLD (f_fmax_29_1) = ((unsigned int) (FLD (f_fmax_frn)) >> (4));
}
errmsg = insert_normal (cd, fields->f_fmax_29_1, 0, 0, 29, 1, 32, total_length, buffer);
if (errmsg)
break;
errmsg = insert_normal (cd, fields->f_fmax_20_4, 0, 0, 20, 4, 32, total_length, buffer);
if (errmsg)
break;
}
break;
case MEP_OPERAND_FMAX_RM :
errmsg = insert_normal (cd, fields->f_fmax_rm, 0, 0, 8, 4, 32, total_length, buffer);
break;
case MEP_OPERAND_HI :
break;
case MEP_OPERAND_LO :
@ -1192,57 +1116,6 @@ mep_cgen_extract_operand (CGEN_CPU_DESC cd,
break;
case MEP_OPERAND_EXC :
break;
case MEP_OPERAND_FMAX_CCRN :
length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 4, 32, total_length, pc, & fields->f_fmax_4_4);
break;
case MEP_OPERAND_FMAX_FRD :
{
length = extract_normal (cd, ex_info, insn_value, 0, 0, 28, 1, 32, total_length, pc, & fields->f_fmax_28_1);
if (length <= 0) break;
length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 4, 32, total_length, pc, & fields->f_fmax_4_4);
if (length <= 0) break;
FLD (f_fmax_frd) = ((((FLD (f_fmax_28_1)) << (4))) | (FLD (f_fmax_4_4)));
}
break;
case MEP_OPERAND_FMAX_FRD_INT :
{
length = extract_normal (cd, ex_info, insn_value, 0, 0, 28, 1, 32, total_length, pc, & fields->f_fmax_28_1);
if (length <= 0) break;
length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 4, 32, total_length, pc, & fields->f_fmax_4_4);
if (length <= 0) break;
FLD (f_fmax_frd) = ((((FLD (f_fmax_28_1)) << (4))) | (FLD (f_fmax_4_4)));
}
break;
case MEP_OPERAND_FMAX_FRM :
{
length = extract_normal (cd, ex_info, insn_value, 0, 0, 30, 1, 32, total_length, pc, & fields->f_fmax_30_1);
if (length <= 0) break;
length = extract_normal (cd, ex_info, insn_value, 0, 0, 24, 4, 32, total_length, pc, & fields->f_fmax_24_4);
if (length <= 0) break;
FLD (f_fmax_frm) = ((((FLD (f_fmax_30_1)) << (4))) | (FLD (f_fmax_24_4)));
}
break;
case MEP_OPERAND_FMAX_FRN :
{
length = extract_normal (cd, ex_info, insn_value, 0, 0, 29, 1, 32, total_length, pc, & fields->f_fmax_29_1);
if (length <= 0) break;
length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 4, 32, total_length, pc, & fields->f_fmax_20_4);
if (length <= 0) break;
FLD (f_fmax_frn) = ((((FLD (f_fmax_29_1)) << (4))) | (FLD (f_fmax_20_4)));
}
break;
case MEP_OPERAND_FMAX_FRN_INT :
{
length = extract_normal (cd, ex_info, insn_value, 0, 0, 29, 1, 32, total_length, pc, & fields->f_fmax_29_1);
if (length <= 0) break;
length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 4, 32, total_length, pc, & fields->f_fmax_20_4);
if (length <= 0) break;
FLD (f_fmax_frn) = ((((FLD (f_fmax_29_1)) << (4))) | (FLD (f_fmax_20_4)));
}
break;
case MEP_OPERAND_FMAX_RM :
length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 4, 32, total_length, pc, & fields->f_fmax_rm);
break;
case MEP_OPERAND_HI :
break;
case MEP_OPERAND_LO :
@ -1545,27 +1418,6 @@ mep_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
case MEP_OPERAND_EXC :
value = 0;
break;
case MEP_OPERAND_FMAX_CCRN :
value = fields->f_fmax_4_4;
break;
case MEP_OPERAND_FMAX_FRD :
value = fields->f_fmax_frd;
break;
case MEP_OPERAND_FMAX_FRD_INT :
value = fields->f_fmax_frd;
break;
case MEP_OPERAND_FMAX_FRM :
value = fields->f_fmax_frm;
break;
case MEP_OPERAND_FMAX_FRN :
value = fields->f_fmax_frn;
break;
case MEP_OPERAND_FMAX_FRN_INT :
value = fields->f_fmax_frn;
break;
case MEP_OPERAND_FMAX_RM :
value = fields->f_fmax_rm;
break;
case MEP_OPERAND_HI :
value = 0;
break;
@ -1820,27 +1672,6 @@ mep_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
case MEP_OPERAND_EXC :
value = 0;
break;
case MEP_OPERAND_FMAX_CCRN :
value = fields->f_fmax_4_4;
break;
case MEP_OPERAND_FMAX_FRD :
value = fields->f_fmax_frd;
break;
case MEP_OPERAND_FMAX_FRD_INT :
value = fields->f_fmax_frd;
break;
case MEP_OPERAND_FMAX_FRM :
value = fields->f_fmax_frm;
break;
case MEP_OPERAND_FMAX_FRN :
value = fields->f_fmax_frn;
break;
case MEP_OPERAND_FMAX_FRN_INT :
value = fields->f_fmax_frn;
break;
case MEP_OPERAND_FMAX_RM :
value = fields->f_fmax_rm;
break;
case MEP_OPERAND_HI :
value = 0;
break;
@ -2097,27 +1928,6 @@ mep_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
break;
case MEP_OPERAND_EXC :
break;
case MEP_OPERAND_FMAX_CCRN :
fields->f_fmax_4_4 = value;
break;
case MEP_OPERAND_FMAX_FRD :
fields->f_fmax_frd = value;
break;
case MEP_OPERAND_FMAX_FRD_INT :
fields->f_fmax_frd = value;
break;
case MEP_OPERAND_FMAX_FRM :
fields->f_fmax_frm = value;
break;
case MEP_OPERAND_FMAX_FRN :
fields->f_fmax_frn = value;
break;
case MEP_OPERAND_FMAX_FRN_INT :
fields->f_fmax_frn = value;
break;
case MEP_OPERAND_FMAX_RM :
fields->f_fmax_rm = value;
break;
case MEP_OPERAND_HI :
break;
case MEP_OPERAND_LO :
@ -2346,27 +2156,6 @@ mep_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
break;
case MEP_OPERAND_EXC :
break;
case MEP_OPERAND_FMAX_CCRN :
fields->f_fmax_4_4 = value;
break;
case MEP_OPERAND_FMAX_FRD :
fields->f_fmax_frd = value;
break;
case MEP_OPERAND_FMAX_FRD_INT :
fields->f_fmax_frd = value;
break;
case MEP_OPERAND_FMAX_FRM :
fields->f_fmax_frm = value;
break;
case MEP_OPERAND_FMAX_FRN :
fields->f_fmax_frn = value;
break;
case MEP_OPERAND_FMAX_FRN_INT :
fields->f_fmax_frn = value;
break;
case MEP_OPERAND_FMAX_RM :
fields->f_fmax_rm = value;
break;
case MEP_OPERAND_HI :
break;
case MEP_OPERAND_LO :

268
opcodes/mep-opc.c
View File

@ -45,7 +45,6 @@ init_mep_all_core_isas_mask (void)
cgen_bitset_set (& mep_all_core_isas_mask, ISA_MEP);
/* begin-all-core-isas */
cgen_bitset_add (& mep_all_core_isas_mask, ISA_EXT_CORE1);
cgen_bitset_add (& mep_all_core_isas_mask, ISA_EXT_CORE2);
/* end-all-core-isas */
}
@ -58,10 +57,6 @@ init_mep_all_cop_isas_mask (void)
return;
cgen_bitset_init (& mep_all_cop_isas_mask, ISA_MAX);
/* begin-all-cop-isas */
cgen_bitset_add (& mep_all_cop_isas_mask, ISA_EXT_COP2_16);
cgen_bitset_add (& mep_all_cop_isas_mask, ISA_EXT_COP2_32);
cgen_bitset_add (& mep_all_cop_isas_mask, ISA_EXT_COP2_48);
cgen_bitset_add (& mep_all_cop_isas_mask, ISA_EXT_COP2_64);
/* end-all-cop-isas */
}
@ -93,12 +88,9 @@ mep_config_map_struct mep_config_map[] =
{
/* config-map-start */
/* Default entry: mep core only, all options enabled. */
{ "", 0, EF_MEP_CPU_C2, 1, 0, {1,"\x0"}, {1,"\x0"}, {1,"\x0"}, {1,"\x0"}, {1,"\x0"}, {1,"\x80"}, OPTION_MASK },
{ "simple", CONFIG_SIMPLE, EF_MEP_CPU_C2, 1, 0, { 1, "\x0" }, { 1, "\x0" }, { 1, "\x0" }, { 1, "\x0" }, { 1, "\x0" }, { 1, "\xc0" },
0 },
{ "fmax", CONFIG_FMAX, EF_MEP_CPU_C2, 1, 0, { 1, "\x10" }, { 1, "\x8" }, { 1, "\x4" }, { 1, "\x2" }, { 1, "\x1e" }, { 1, "\xa0" },
{ "", 0, EF_MEP_CPU_C4, 1, 0, {1,"\x0"}, {1,"\x0"}, {1,"\x0"}, {1,"\x0"}, {1,"\x0"}, {1,"\x80"}, OPTION_MASK },
{ "default", CONFIG_DEFAULT, EF_MEP_CPU_C4, 0, 0, { 1, "\x0" }, { 1, "\x0" }, { 1, "\x0" }, { 1, "\x0" }, { 1, "\x0" }, { 1, "\xc0" },
0
| (1 << CGEN_INSN_OPTIONAL_CP_INSN)
| (1 << CGEN_INSN_OPTIONAL_MUL_INSN)
| (1 << CGEN_INSN_OPTIONAL_DIV_INSN)
| (1 << CGEN_INSN_OPTIONAL_BIT_INSN)
@ -412,34 +404,6 @@ static const CGEN_IFMT ifmt_sim_syscall ATTRIBUTE_UNUSED = {
16, 16, 0xf8ef, { { F (F_MAJOR) }, { F (F_4) }, { F (F_CALLNUM) }, { F (F_8) }, { F (F_9) }, { F (F_10) }, { F (F_SUB4) }, { 0 } }
};
static const CGEN_IFMT ifmt_fadds ATTRIBUTE_UNUSED = {
32, 32, 0xf0fff001, { { F (F_FMAX_0_4) }, { F (F_FMAX_FRD) }, { F (F_FMAX_8_4) }, { F (F_FMAX_12_4) }, { F (F_FMAX_16_4) }, { F (F_FMAX_FRN) }, { F (F_FMAX_FRM) }, { F (F_FMAX_31_1) }, { 0 } }
};
static const CGEN_IFMT ifmt_fsqrts ATTRIBUTE_UNUSED = {
32, 32, 0xf0fff0f3, { { F (F_FMAX_0_4) }, { F (F_FMAX_FRD) }, { F (F_FMAX_8_4) }, { F (F_FMAX_12_4) }, { F (F_FMAX_16_4) }, { F (F_FMAX_FRN) }, { F (F_FMAX_24_4) }, { F (F_FMAX_30_1) }, { F (F_FMAX_31_1) }, { 0 } }
};
static const CGEN_IFMT ifmt_froundws ATTRIBUTE_UNUSED = {
32, 32, 0xf0fff0f3, { { F (F_FMAX_0_4) }, { F (F_FMAX_FRD) }, { F (F_FMAX_8_4) }, { F (F_FMAX_12_4) }, { F (F_FMAX_16_4) }, { F (F_FMAX_FRN) }, { F (F_FMAX_24_4) }, { F (F_FMAX_30_1) }, { F (F_FMAX_31_1) }, { 0 } }
};
static const CGEN_IFMT ifmt_fcvtsw ATTRIBUTE_UNUSED = {
32, 32, 0xf0fff0f3, { { F (F_FMAX_0_4) }, { F (F_FMAX_FRD) }, { F (F_FMAX_8_4) }, { F (F_FMAX_12_4) }, { F (F_FMAX_16_4) }, { F (F_FMAX_FRN) }, { F (F_FMAX_24_4) }, { F (F_FMAX_30_1) }, { F (F_FMAX_31_1) }, { 0 } }
};
static const CGEN_IFMT ifmt_fcmpfs ATTRIBUTE_UNUSED = {
32, 32, 0xfffff009, { { F (F_FMAX_0_4) }, { F (F_FMAX_4_4) }, { F (F_FMAX_8_4) }, { F (F_FMAX_12_4) }, { F (F_FMAX_16_4) }, { F (F_FMAX_FRN) }, { F (F_FMAX_FRM) }, { F (F_FMAX_28_1) }, { F (F_FMAX_31_1) }, { 0 } }
};
static const CGEN_IFMT ifmt_cmov_frn_rm ATTRIBUTE_UNUSED = {
32, 32, 0xf00ffff7, { { F (F_FMAX_0_4) }, { F (F_FMAX_FRD) }, { F (F_FMAX_RM) }, { F (F_FMAX_12_4) }, { F (F_FMAX_16_4) }, { F (F_FMAX_20_4) }, { F (F_FMAX_24_4) }, { F (F_FMAX_29_1) }, { F (F_FMAX_30_1) }, { F (F_FMAX_31_1) }, { 0 } }
};
static const CGEN_IFMT ifmt_cmovc_ccrn_rm ATTRIBUTE_UNUSED = {
32, 32, 0xf00fffff, { { F (F_FMAX_0_4) }, { F (F_FMAX_4_4) }, { F (F_FMAX_RM) }, { F (F_FMAX_12_4) }, { F (F_FMAX_16_4) }, { F (F_FMAX_20_4) }, { F (F_FMAX_24_4) }, { F (F_FMAX_28_1) }, { F (F_FMAX_29_1) }, { F (F_FMAX_30_1) }, { F (F_FMAX_31_1) }, { 0 } }
};
#undef F
#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
@ -1705,210 +1669,6 @@ static const CGEN_OPCODE mep_cgen_insn_opcode_table[MAX_INSNS] =
{ { MNEM, 0 } },
& ifmt_mov, { 0x700d }
},
/* fadds ${fmax-FRd},${fmax-FRn},${fmax-FRm} */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (FMAX_FRD), ',', OP (FMAX_FRN), ',', OP (FMAX_FRM), 0 } },
& ifmt_fadds, { 0xf0070000 }
},
/* fsubs ${fmax-FRd},${fmax-FRn},${fmax-FRm} */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (FMAX_FRD), ',', OP (FMAX_FRN), ',', OP (FMAX_FRM), 0 } },
& ifmt_fadds, { 0xf0170000 }
},
/* fmuls ${fmax-FRd},${fmax-FRn},${fmax-FRm} */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (FMAX_FRD), ',', OP (FMAX_FRN), ',', OP (FMAX_FRM), 0 } },
& ifmt_fadds, { 0xf0270000 }
},
/* fdivs ${fmax-FRd},${fmax-FRn},${fmax-FRm} */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (FMAX_FRD), ',', OP (FMAX_FRN), ',', OP (FMAX_FRM), 0 } },
& ifmt_fadds, { 0xf0370000 }
},
/* fsqrts ${fmax-FRd},${fmax-FRn} */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (FMAX_FRD), ',', OP (FMAX_FRN), 0 } },
& ifmt_fsqrts, { 0xf0470000 }
},
/* fabss ${fmax-FRd},${fmax-FRn} */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (FMAX_FRD), ',', OP (FMAX_FRN), 0 } },
& ifmt_fsqrts, { 0xf0570000 }
},
/* fnegs ${fmax-FRd},${fmax-FRn} */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (FMAX_FRD), ',', OP (FMAX_FRN), 0 } },
& ifmt_fsqrts, { 0xf0770000 }
},
/* fmovs ${fmax-FRd},${fmax-FRn} */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (FMAX_FRD), ',', OP (FMAX_FRN), 0 } },
& ifmt_fsqrts, { 0xf0670000 }
},
/* froundws ${fmax-FRd-int},${fmax-FRn} */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (FMAX_FRD_INT), ',', OP (FMAX_FRN), 0 } },
& ifmt_froundws, { 0xf0c70000 }
},
/* ftruncws ${fmax-FRd-int},${fmax-FRn} */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (FMAX_FRD_INT), ',', OP (FMAX_FRN), 0 } },
& ifmt_froundws, { 0xf0d70000 }
},
/* fceilws ${fmax-FRd-int},${fmax-FRn} */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (FMAX_FRD_INT), ',', OP (FMAX_FRN), 0 } },
& ifmt_froundws, { 0xf0e70000 }
},
/* ffloorws ${fmax-FRd-int},${fmax-FRn} */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (FMAX_FRD_INT), ',', OP (FMAX_FRN), 0 } },
& ifmt_froundws, { 0xf0f70000 }
},
/* fcvtws ${fmax-FRd-int},${fmax-FRn} */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (FMAX_FRD_INT), ',', OP (FMAX_FRN), 0 } },
& ifmt_froundws, { 0xf0471000 }
},
/* fcvtsw ${fmax-FRd},${fmax-FRn-int} */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (FMAX_FRD), ',', OP (FMAX_FRN_INT), 0 } },
& ifmt_fcvtsw, { 0xf0079000 }
},
/* fcmpfs ${fmax-FRn},${fmax-FRm} */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (FMAX_FRN), ',', OP (FMAX_FRM), 0 } },
& ifmt_fcmpfs, { 0xf0072000 }
},
/* fcmpus ${fmax-FRn},${fmax-FRm} */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (FMAX_FRN), ',', OP (FMAX_FRM), 0 } },
& ifmt_fcmpfs, { 0xf0172000 }
},
/* fcmpes ${fmax-FRn},${fmax-FRm} */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (FMAX_FRN), ',', OP (FMAX_FRM), 0 } },
& ifmt_fcmpfs, { 0xf0272000 }
},
/* fcmpues ${fmax-FRn},${fmax-FRm} */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (FMAX_FRN), ',', OP (FMAX_FRM), 0 } },
& ifmt_fcmpfs, { 0xf0372000 }
},
/* fcmpls ${fmax-FRn},${fmax-FRm} */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (FMAX_FRN), ',', OP (FMAX_FRM), 0 } },
& ifmt_fcmpfs, { 0xf0472000 }
},
/* fcmpuls ${fmax-FRn},${fmax-FRm} */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (FMAX_FRN), ',', OP (FMAX_FRM), 0 } },
& ifmt_fcmpfs, { 0xf0572000 }
},
/* fcmples ${fmax-FRn},${fmax-FRm} */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (FMAX_FRN), ',', OP (FMAX_FRM), 0 } },
& ifmt_fcmpfs, { 0xf0672000 }
},
/* fcmpules ${fmax-FRn},${fmax-FRm} */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (FMAX_FRN), ',', OP (FMAX_FRM), 0 } },
& ifmt_fcmpfs, { 0xf0772000 }
},
/* fcmpfis ${fmax-FRn},${fmax-FRm} */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (FMAX_FRN), ',', OP (FMAX_FRM), 0 } },
& ifmt_fcmpfs, { 0xf0872000 }
},
/* fcmpuis ${fmax-FRn},${fmax-FRm} */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (FMAX_FRN), ',', OP (FMAX_FRM), 0 } },
& ifmt_fcmpfs, { 0xf0972000 }
},
/* fcmpeis ${fmax-FRn},${fmax-FRm} */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (FMAX_FRN), ',', OP (FMAX_FRM), 0 } },
& ifmt_fcmpfs, { 0xf0a72000 }
},
/* fcmpueis ${fmax-FRn},${fmax-FRm} */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (FMAX_FRN), ',', OP (FMAX_FRM), 0 } },
& ifmt_fcmpfs, { 0xf0b72000 }
},
/* fcmplis ${fmax-FRn},${fmax-FRm} */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (FMAX_FRN), ',', OP (FMAX_FRM), 0 } },
& ifmt_fcmpfs, { 0xf0c72000 }
},
/* fcmpulis ${fmax-FRn},${fmax-FRm} */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (FMAX_FRN), ',', OP (FMAX_FRM), 0 } },
& ifmt_fcmpfs, { 0xf0d72000 }
},
/* fcmpleis ${fmax-FRn},${fmax-FRm} */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (FMAX_FRN), ',', OP (FMAX_FRM), 0 } },
& ifmt_fcmpfs, { 0xf0e72000 }
},
/* fcmpuleis ${fmax-FRn},${fmax-FRm} */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (FMAX_FRN), ',', OP (FMAX_FRM), 0 } },
& ifmt_fcmpfs, { 0xf0f72000 }
},
/* cmov ${fmax-FRd-int},${fmax-Rm} */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (FMAX_FRD_INT), ',', OP (FMAX_RM), 0 } },
& ifmt_cmov_frn_rm, { 0xf007f000 }
},
/* cmov ${fmax-Rm},${fmax-FRd-int} */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (FMAX_RM), ',', OP (FMAX_FRD_INT), 0 } },
& ifmt_cmov_frn_rm, { 0xf007f001 }
},
/* cmovc ${fmax-CCRn},${fmax-Rm} */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (FMAX_CCRN), ',', OP (FMAX_RM), 0 } },
& ifmt_cmovc_ccrn_rm, { 0xf007f002 }
},
/* cmovc ${fmax-Rm},${fmax-CCRn} */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (FMAX_RM), ',', OP (FMAX_CCRN), 0 } },
& ifmt_cmovc_ccrn_rm, { 0xf007f003 }
},
};
#undef A
@ -2004,62 +1764,62 @@ static const CGEN_IBASE mep_cgen_macro_insn_table[] =
/* sb $rnc,$zero($rma) */
{
-1, "sb16-0", "sb", 16,
{ 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
{ 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
},
/* sh $rns,$zero($rma) */
{
-1, "sh16-0", "sh", 16,
{ 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
{ 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
},
/* sw $rnl,$zero($rma) */
{
-1, "sw16-0", "sw", 16,
{ 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
{ 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
},
/* lb $rnc,$zero($rma) */
{
-1, "lb16-0", "lb", 16,
{ 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
{ 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
},
/* lh $rns,$zero($rma) */
{
-1, "lh16-0", "lh", 16,
{ 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
{ 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
},
/* lw $rnl,$zero($rma) */
{
-1, "lw16-0", "lw", 16,
{ 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
{ 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
},
/* lbu $rnuc,$zero($rma) */
{
-1, "lbu16-0", "lbu", 16,
{ 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
{ 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
},
/* lhu $rnus,$zero($rma) */
{
-1, "lhu16-0", "lhu", 16,
{ 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
{ 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
},
/* swcp $crn,$zero($rma) */
{
-1, "swcp16-0", "swcp", 16,
{ 0|A(NO_DIS)|A(OPTIONAL_CP_INSN)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
{ 0|A(NO_DIS)|A(OPTIONAL_CP_INSN)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
},
/* lwcp $crn,$zero($rma) */
{
-1, "lwcp16-0", "lwcp", 16,
{ 0|A(NO_DIS)|A(OPTIONAL_CP_INSN)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
{ 0|A(NO_DIS)|A(OPTIONAL_CP_INSN)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
},
/* smcp $crn64,$zero($rma) */
{
-1, "smcp16-0", "smcp", 16,
{ 0|A(NO_DIS)|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
{ 0|A(NO_DIS)|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
},
/* lmcp $crn64,$zero($rma) */
{
-1, "lmcp16-0", "lmcp", 16,
{ 0|A(NO_DIS)|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xe0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
{ 0|A(NO_DIS)|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } } } }
},
};

26
opcodes/mep-opc.h
View File

@ -148,22 +148,13 @@ typedef enum cgen_insn_type {
, MEP_INSN_RI_15, MEP_INSN_RI_17, MEP_INSN_RI_20, MEP_INSN_RI_21
, MEP_INSN_RI_22, MEP_INSN_RI_23, MEP_INSN_RI_24, MEP_INSN_RI_25
, MEP_INSN_RI_26, MEP_INSN_RI_16, MEP_INSN_RI_18, MEP_INSN_RI_19
, MEP_INSN_FADDS, MEP_INSN_FSUBS, MEP_INSN_FMULS, MEP_INSN_FDIVS
, MEP_INSN_FSQRTS, MEP_INSN_FABSS, MEP_INSN_FNEGS, MEP_INSN_FMOVS
, MEP_INSN_FROUNDWS, MEP_INSN_FTRUNCWS, MEP_INSN_FCEILWS, MEP_INSN_FFLOORWS
, MEP_INSN_FCVTWS, MEP_INSN_FCVTSW, MEP_INSN_FCMPFS, MEP_INSN_FCMPUS
, MEP_INSN_FCMPES, MEP_INSN_FCMPUES, MEP_INSN_FCMPLS, MEP_INSN_FCMPULS
, MEP_INSN_FCMPLES, MEP_INSN_FCMPULES, MEP_INSN_FCMPFIS, MEP_INSN_FCMPUIS
, MEP_INSN_FCMPEIS, MEP_INSN_FCMPUEIS, MEP_INSN_FCMPLIS, MEP_INSN_FCMPULIS
, MEP_INSN_FCMPLEIS, MEP_INSN_FCMPULEIS, MEP_INSN_CMOV_FRN_RM, MEP_INSN_CMOV_RM_FRN
, MEP_INSN_CMOVC_CCRN_RM, MEP_INSN_CMOVC_RM_CCRN
} CGEN_INSN_TYPE;
/* Index of `invalid' insn place holder. */
#define CGEN_INSN_INVALID MEP_INSN_INVALID
/* Total number of insns in table. */
#define MAX_INSNS ((int) MEP_INSN_CMOVC_RM_CCRN + 1)
#define MAX_INSNS ((int) MEP_INSN_RI_19 + 1)
/* This struct records data prior to insertion or after extraction. */
struct cgen_fields
@ -260,21 +251,6 @@ struct cgen_fields
long f_ccrn_hi;
long f_ccrn_lo;
long f_ccrn;
long f_fmax_0_4;
long f_fmax_4_4;
long f_fmax_8_4;
long f_fmax_12_4;
long f_fmax_16_4;
long f_fmax_20_4;
long f_fmax_24_4;
long f_fmax_28_1;
long f_fmax_29_1;
long f_fmax_30_1;
long f_fmax_31_1;
long f_fmax_frd;
long f_fmax_frn;
long f_fmax_frm;
long f_fmax_rm;
};
#define CGEN_INIT_PARSE(od) \

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