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* mep-*: New support for Toshiba Media Processor (MeP).
* Makefile.am: Add support for MeP.
* configure.in: Likewise.
* disassemble.c: Likewise.
* Makefile.in: Regenerated.
* configure: Regenerated.
drow-reverse-20070409-branch
Dave Brolley
19 years ago
13 changed files with 10882 additions and 4 deletions
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/* CPU data header for mep.
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THIS FILE IS MACHINE GENERATED WITH CGEN. |
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Copyright 1996-2005 Free Software Foundation, Inc. |
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This file is part of the GNU Binutils and/or GDB, the GNU debugger. |
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This program is free software; you can redistribute it and/or modify |
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it under the terms of the GNU General Public License as published by |
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the Free Software Foundation; either version 2, or (at your option) |
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any later version. |
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This program is distributed in the hope that it will be useful, |
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but WITHOUT ANY WARRANTY; without even the implied warranty of |
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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GNU General Public License for more details. |
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You should have received a copy of the GNU General Public License along |
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with this program; if not, write to the Free Software Foundation, Inc., |
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51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. |
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*/ |
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#ifndef MEP_CPU_H |
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#define MEP_CPU_H |
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#include "opcode/cgen-bitset.h" |
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#define CGEN_ARCH mep |
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/* Given symbol S, return mep_cgen_<S>. */ |
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#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) |
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#define CGEN_SYM(s) mep##_cgen_##s |
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#else |
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#define CGEN_SYM(s) mep/**/_cgen_/**/s |
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#endif |
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/* Selected cpu families. */ |
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#define HAVE_CPU_MEPF |
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#define CGEN_INSN_LSB0_P 0 |
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/* Minimum size of any insn (in bytes). */ |
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#define CGEN_MIN_INSN_SIZE 2 |
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/* Maximum size of any insn (in bytes). */ |
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#define CGEN_MAX_INSN_SIZE 4 |
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#define CGEN_INT_INSN_P 1 |
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/* Maximum number of syntax elements in an instruction. */ |
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#define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 17 |
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/* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands.
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e.g. In "b,a foo" the ",a" is an operand. If mnemonics have operands |
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we can't hash on everything up to the space. */ |
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#define CGEN_MNEMONIC_OPERANDS |
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/* Maximum number of fields in an instruction. */ |
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#define CGEN_ACTUAL_MAX_IFMT_OPERANDS 11 |
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/* Enums. */ |
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/* Enum declaration for major opcodes. */ |
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typedef enum major { |
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MAJ_0, MAJ_1, MAJ_2, MAJ_3 |
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, MAJ_4, MAJ_5, MAJ_6, MAJ_7 |
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, MAJ_8, MAJ_9, MAJ_10, MAJ_11 |
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, MAJ_12, MAJ_13, MAJ_14, MAJ_15 |
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} MAJOR; |
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/* Enum declaration for condition opcode enum. */ |
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typedef enum fmax_cond { |
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FMAX_F, FMAX_U, FMAX_E, FMAX_UE |
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, FMAX_L, FMAX_UL, FMAX_LE, FMAX_ULE |
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, FMAX_FI, FMAX_UI, FMAX_EI, FMAX_UEI |
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, FMAX_LI, FMAX_ULI, FMAX_LEI, FMAX_ULEI |
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} FMAX_COND; |
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/* Attributes. */ |
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/* Enum declaration for machine type selection. */ |
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typedef enum mach_attr { |
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MACH_BASE, MACH_MEP, MACH_H1, MACH_MAX |
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} MACH_ATTR; |
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/* Enum declaration for instruction set selection. */ |
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typedef enum isa_attr { |
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ISA_MEP, ISA_EXT_CORE1, ISA_EXT_CORE2, ISA_EXT_COP2_16 |
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, ISA_EXT_COP2_32, ISA_EXT_COP2_48, ISA_EXT_COP2_64, ISA_MAX |
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} ISA_ATTR; |
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/* Enum declaration for datatype to use for C intrinsics mapping. */ |
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typedef enum cdata_attr { |
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CDATA_LABEL, CDATA_REGNUM, CDATA_FMAX_FLOAT, CDATA_FMAX_INT |
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, CDATA_POINTER, CDATA_LONG, CDATA_ULONG, CDATA_SHORT |
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, CDATA_USHORT, CDATA_CHAR, CDATA_UCHAR, CDATA_CP_DATA_BUS_INT |
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} CDATA_ATTR; |
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/* Enum declaration for . */ |
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typedef enum config_attr { |
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CONFIG_NONE, CONFIG_SIMPLE, CONFIG_FMAX |
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} CONFIG_ATTR; |
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/* Number of architecture variants. */ |
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#define MAX_ISAS ((int) ISA_MAX) |
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#define MAX_MACHS ((int) MACH_MAX) |
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/* Ifield support. */ |
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/* Ifield attribute indices. */ |
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/* Enum declaration for cgen_ifld attrs. */ |
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typedef enum cgen_ifld_attr { |
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CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED |
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, CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_END_BOOLS, CGEN_IFLD_START_NBOOLS = 31 |
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, CGEN_IFLD_MACH, CGEN_IFLD_ISA, CGEN_IFLD_END_NBOOLS |
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} CGEN_IFLD_ATTR; |
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/* Number of non-boolean elements in cgen_ifld_attr. */ |
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#define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1) |
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/* cgen_ifld attribute accessor macros. */ |
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#define CGEN_ATTR_CGEN_IFLD_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_MACH-CGEN_IFLD_START_NBOOLS-1].nonbitset) |
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#define CGEN_ATTR_CGEN_IFLD_ISA_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_ISA-CGEN_IFLD_START_NBOOLS-1].bitset) |
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#define CGEN_ATTR_CGEN_IFLD_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_VIRTUAL)) != 0) |
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#define CGEN_ATTR_CGEN_IFLD_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_PCREL_ADDR)) != 0) |
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#define CGEN_ATTR_CGEN_IFLD_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_ABS_ADDR)) != 0) |
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#define CGEN_ATTR_CGEN_IFLD_RESERVED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_RESERVED)) != 0) |
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#define CGEN_ATTR_CGEN_IFLD_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGN_OPT)) != 0) |
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#define CGEN_ATTR_CGEN_IFLD_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGNED)) != 0) |
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/* Enum declaration for mep ifield types. */ |
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typedef enum ifield_type { |
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MEP_F_NIL, MEP_F_ANYOF, MEP_F_MAJOR, MEP_F_RN |
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, MEP_F_RN3, MEP_F_RM, MEP_F_RL, MEP_F_SUB2 |
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, MEP_F_SUB3, MEP_F_SUB4, MEP_F_EXT, MEP_F_CRN |
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, MEP_F_CSRN_HI, MEP_F_CSRN_LO, MEP_F_CSRN, MEP_F_CRNX_HI |
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, MEP_F_CRNX_LO, MEP_F_CRNX, MEP_F_0, MEP_F_1 |
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, MEP_F_2, MEP_F_3, MEP_F_4, MEP_F_5 |
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, MEP_F_6, MEP_F_7, MEP_F_8, MEP_F_9 |
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, MEP_F_10, MEP_F_11, MEP_F_12, MEP_F_13 |
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, MEP_F_14, MEP_F_15, MEP_F_16, MEP_F_17 |
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, MEP_F_18, MEP_F_19, MEP_F_20, MEP_F_21 |
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, MEP_F_22, MEP_F_23, MEP_F_24, MEP_F_25 |
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, MEP_F_26, MEP_F_27, MEP_F_28, MEP_F_29 |
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, MEP_F_30, MEP_F_31, MEP_F_8S8A2, MEP_F_12S4A2 |
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, MEP_F_17S16A2, MEP_F_24S5A2N_HI, MEP_F_24S5A2N_LO, MEP_F_24S5A2N |
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, MEP_F_24U5A2N_HI, MEP_F_24U5A2N_LO, MEP_F_24U5A2N, MEP_F_2U6 |
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, MEP_F_7U9, MEP_F_7U9A2, MEP_F_7U9A4, MEP_F_16S16 |
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, MEP_F_2U10, MEP_F_3U5, MEP_F_4U8, MEP_F_5U8 |
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, MEP_F_5U24, MEP_F_6S8, MEP_F_8S8, MEP_F_16U16 |
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, MEP_F_12U16, MEP_F_3U29, MEP_F_8S24, MEP_F_8S24A2 |
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, MEP_F_8S24A4, MEP_F_8S24A8, MEP_F_24U8A4N_HI, MEP_F_24U8A4N_LO |
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, MEP_F_24U8A4N, MEP_F_24U8N_HI, MEP_F_24U8N_LO, MEP_F_24U8N |
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, MEP_F_24U4N_HI, MEP_F_24U4N_LO, MEP_F_24U4N, MEP_F_CALLNUM |
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, MEP_F_CCRN_HI, MEP_F_CCRN_LO, MEP_F_CCRN, MEP_F_FMAX_0_4 |
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, MEP_F_FMAX_4_4, MEP_F_FMAX_8_4, MEP_F_FMAX_12_4, MEP_F_FMAX_16_4 |
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, MEP_F_FMAX_20_4, MEP_F_FMAX_24_4, MEP_F_FMAX_28_1, MEP_F_FMAX_29_1 |
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, MEP_F_FMAX_30_1, MEP_F_FMAX_31_1, MEP_F_FMAX_FRD, MEP_F_FMAX_FRN |
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, MEP_F_FMAX_FRM, MEP_F_FMAX_RM, MEP_F_MAX |
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} IFIELD_TYPE; |
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#define MAX_IFLD ((int) MEP_F_MAX) |
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/* Hardware attribute indices. */ |
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/* Enum declaration for cgen_hw attrs. */ |
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typedef enum cgen_hw_attr { |
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CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE |
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, CGEN_HW_IS_FLOAT, CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH |
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, CGEN_HW_ISA, CGEN_HW_END_NBOOLS |
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} CGEN_HW_ATTR; |
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/* Number of non-boolean elements in cgen_hw_attr. */ |
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#define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1) |
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/* cgen_hw attribute accessor macros. */ |
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#define CGEN_ATTR_CGEN_HW_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_MACH-CGEN_HW_START_NBOOLS-1].nonbitset) |
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#define CGEN_ATTR_CGEN_HW_ISA_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_ISA-CGEN_HW_START_NBOOLS-1].bitset) |
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#define CGEN_ATTR_CGEN_HW_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_VIRTUAL)) != 0) |
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#define CGEN_ATTR_CGEN_HW_CACHE_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_CACHE_ADDR)) != 0) |
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#define CGEN_ATTR_CGEN_HW_PC_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PC)) != 0) |
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#define CGEN_ATTR_CGEN_HW_PROFILE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PROFILE)) != 0) |
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#define CGEN_ATTR_CGEN_HW_IS_FLOAT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_IS_FLOAT)) != 0) |
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/* Enum declaration for mep hardware types. */ |
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typedef enum cgen_hw_type { |
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HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR |
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, HW_H_IADDR, HW_H_PC, HW_H_GPR, HW_H_CSR |
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, HW_H_CR64, HW_H_CR, HW_H_CCR, HW_H_CR_FMAX |
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, HW_H_CCR_FMAX, HW_H_FMAX_COMPARE_I_P, HW_MAX |
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} CGEN_HW_TYPE; |
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#define MAX_HW ((int) HW_MAX) |
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/* Operand attribute indices. */ |
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/* Enum declaration for cgen_operand attrs. */ |
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typedef enum cgen_operand_attr { |
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CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT |
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, CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY |
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, CGEN_OPERAND_RELOC_IMPLIES_OVERFLOW, CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH |
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, CGEN_OPERAND_ISA, CGEN_OPERAND_CDATA, CGEN_OPERAND_ALIGN, CGEN_OPERAND_END_NBOOLS |
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} CGEN_OPERAND_ATTR; |
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/* Number of non-boolean elements in cgen_operand_attr. */ |
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#define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1) |
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/* cgen_operand attribute accessor macros. */ |
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#define CGEN_ATTR_CGEN_OPERAND_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_MACH-CGEN_OPERAND_START_NBOOLS-1].nonbitset) |
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#define CGEN_ATTR_CGEN_OPERAND_ISA_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_ISA-CGEN_OPERAND_START_NBOOLS-1].bitset) |
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#define CGEN_ATTR_CGEN_OPERAND_CDATA_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_CDATA-CGEN_OPERAND_START_NBOOLS-1].nonbitset) |
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#define CGEN_ATTR_CGEN_OPERAND_ALIGN_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_ALIGN-CGEN_OPERAND_START_NBOOLS-1].nonbitset) |
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#define CGEN_ATTR_CGEN_OPERAND_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_VIRTUAL)) != 0) |
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#define CGEN_ATTR_CGEN_OPERAND_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_PCREL_ADDR)) != 0) |
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#define CGEN_ATTR_CGEN_OPERAND_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_ABS_ADDR)) != 0) |
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#define CGEN_ATTR_CGEN_OPERAND_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGN_OPT)) != 0) |
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#define CGEN_ATTR_CGEN_OPERAND_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGNED)) != 0) |
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#define CGEN_ATTR_CGEN_OPERAND_NEGATIVE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_NEGATIVE)) != 0) |
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#define CGEN_ATTR_CGEN_OPERAND_RELAX_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_RELAX)) != 0) |
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#define CGEN_ATTR_CGEN_OPERAND_SEM_ONLY_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SEM_ONLY)) != 0) |
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#define CGEN_ATTR_CGEN_OPERAND_RELOC_IMPLIES_OVERFLOW_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_RELOC_IMPLIES_OVERFLOW)) != 0) |
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/* Enum declaration for mep operand types. */ |
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typedef enum cgen_operand_type { |
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MEP_OPERAND_PC, MEP_OPERAND_R0, MEP_OPERAND_RN, MEP_OPERAND_RM |
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, MEP_OPERAND_RL, MEP_OPERAND_RN3, MEP_OPERAND_RMA, MEP_OPERAND_RNC |
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, MEP_OPERAND_RNUC, MEP_OPERAND_RNS, MEP_OPERAND_RNUS, MEP_OPERAND_RNL |
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, MEP_OPERAND_RNUL, MEP_OPERAND_RN3C, MEP_OPERAND_RN3UC, MEP_OPERAND_RN3S |
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, MEP_OPERAND_RN3US, MEP_OPERAND_RN3L, MEP_OPERAND_RN3UL, MEP_OPERAND_LP |
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, MEP_OPERAND_SAR, MEP_OPERAND_HI, MEP_OPERAND_LO, MEP_OPERAND_MB0 |
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, MEP_OPERAND_ME0, MEP_OPERAND_MB1, MEP_OPERAND_ME1, MEP_OPERAND_PSW |
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, MEP_OPERAND_EPC, MEP_OPERAND_EXC, MEP_OPERAND_NPC, MEP_OPERAND_DBG |
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, MEP_OPERAND_DEPC, MEP_OPERAND_OPT, MEP_OPERAND_R1, MEP_OPERAND_TP |
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, MEP_OPERAND_SP, MEP_OPERAND_TPR, MEP_OPERAND_SPR, MEP_OPERAND_CSRN |
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, MEP_OPERAND_CSRN_IDX, MEP_OPERAND_CRN64, MEP_OPERAND_CRN, MEP_OPERAND_CRNX64 |
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, MEP_OPERAND_CRNX, MEP_OPERAND_CCRN, MEP_OPERAND_CCCC, MEP_OPERAND_PCREL8A2 |
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, MEP_OPERAND_PCREL12A2, MEP_OPERAND_PCREL17A2, MEP_OPERAND_PCREL24A2, MEP_OPERAND_PCABS24A2 |
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, MEP_OPERAND_SDISP16, MEP_OPERAND_SIMM16, MEP_OPERAND_UIMM16, MEP_OPERAND_CODE16 |
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, MEP_OPERAND_UDISP2, MEP_OPERAND_UIMM2, MEP_OPERAND_SIMM6, MEP_OPERAND_SIMM8 |
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, MEP_OPERAND_ADDR24A4, MEP_OPERAND_CODE24, MEP_OPERAND_CALLNUM, MEP_OPERAND_UIMM3 |
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, MEP_OPERAND_UIMM4, MEP_OPERAND_UIMM5, MEP_OPERAND_UDISP7, MEP_OPERAND_UDISP7A2 |
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, MEP_OPERAND_UDISP7A4, MEP_OPERAND_UIMM7A4, MEP_OPERAND_UIMM24, MEP_OPERAND_CIMM4 |
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, MEP_OPERAND_CIMM5, MEP_OPERAND_CDISP8, MEP_OPERAND_CDISP8A2, MEP_OPERAND_CDISP8A4 |
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, MEP_OPERAND_CDISP8A8, MEP_OPERAND_ZERO, MEP_OPERAND_CP_FLAG, MEP_OPERAND_FMAX_FRD |
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, MEP_OPERAND_FMAX_FRN, MEP_OPERAND_FMAX_FRM, MEP_OPERAND_FMAX_FRD_INT, MEP_OPERAND_FMAX_FRN_INT |
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, MEP_OPERAND_FMAX_CCRN, MEP_OPERAND_FMAX_CIRR, MEP_OPERAND_FMAX_CBCR, MEP_OPERAND_FMAX_CERR |
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, MEP_OPERAND_FMAX_RM, MEP_OPERAND_FMAX_COMPARE_I_P, MEP_OPERAND_MAX |
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} CGEN_OPERAND_TYPE; |
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/* Number of operands types. */ |
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#define MAX_OPERANDS 90 |
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/* Maximum number of operands referenced by any insn. */ |
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#define MAX_OPERAND_INSTANCES 8 |
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/* Insn attribute indices. */ |
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/* Enum declaration for cgen_insn attrs. */ |
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typedef enum cgen_insn_attr { |
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CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI |
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, CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED |
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, CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_OPTIONAL_BIT_INSN, CGEN_INSN_OPTIONAL_MUL_INSN |
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, CGEN_INSN_OPTIONAL_DIV_INSN, CGEN_INSN_OPTIONAL_DEBUG_INSN, CGEN_INSN_OPTIONAL_LDZ_INSN, CGEN_INSN_OPTIONAL_ABS_INSN |
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, CGEN_INSN_OPTIONAL_AVE_INSN, CGEN_INSN_OPTIONAL_MINMAX_INSN, CGEN_INSN_OPTIONAL_CLIP_INSN, CGEN_INSN_OPTIONAL_SAT_INSN |
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, CGEN_INSN_OPTIONAL_UCI_INSN, CGEN_INSN_OPTIONAL_DSP_INSN, CGEN_INSN_OPTIONAL_CP_INSN, CGEN_INSN_OPTIONAL_CP64_INSN |
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, CGEN_INSN_OPTIONAL_VLIW64, CGEN_INSN_MAY_TRAP, CGEN_INSN_VLIW_ALONE, CGEN_INSN_VLIW_NO_CORE_NOP |
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, CGEN_INSN_VLIW_NO_COP_NOP, CGEN_INSN_VLIW64_NO_MATCHING_NOP, CGEN_INSN_VLIW32_NO_MATCHING_NOP, CGEN_INSN_VOLATILE |
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, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH, CGEN_INSN_ISA |
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, CGEN_INSN_LATENCY, CGEN_INSN_CONFIG, CGEN_INSN_END_NBOOLS |
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} CGEN_INSN_ATTR; |
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/* Number of non-boolean elements in cgen_insn_attr. */ |
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#define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1) |
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/* cgen_insn attribute accessor macros. */ |
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#define CGEN_ATTR_CGEN_INSN_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_MACH-CGEN_INSN_START_NBOOLS-1].nonbitset) |
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#define CGEN_ATTR_CGEN_INSN_ISA_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_ISA-CGEN_INSN_START_NBOOLS-1].bitset) |
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#define CGEN_ATTR_CGEN_INSN_LATENCY_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_LATENCY-CGEN_INSN_START_NBOOLS-1].nonbitset) |
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#define CGEN_ATTR_CGEN_INSN_CONFIG_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_CONFIG-CGEN_INSN_START_NBOOLS-1].nonbitset) |
|||
#define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_ALIAS)) != 0) |
|||
#define CGEN_ATTR_CGEN_INSN_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_VIRTUAL)) != 0) |
|||
#define CGEN_ATTR_CGEN_INSN_UNCOND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_UNCOND_CTI)) != 0) |
|||
#define CGEN_ATTR_CGEN_INSN_COND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_COND_CTI)) != 0) |
|||
#define CGEN_ATTR_CGEN_INSN_SKIP_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_SKIP_CTI)) != 0) |
|||
#define CGEN_ATTR_CGEN_INSN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_DELAY_SLOT)) != 0) |
|||
#define CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXABLE)) != 0) |
|||
#define CGEN_ATTR_CGEN_INSN_RELAXED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXED)) != 0) |
|||
#define CGEN_ATTR_CGEN_INSN_NO_DIS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_NO_DIS)) != 0) |
|||
#define CGEN_ATTR_CGEN_INSN_PBB_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_PBB)) != 0) |
|||
#define CGEN_ATTR_CGEN_INSN_OPTIONAL_BIT_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_OPTIONAL_BIT_INSN)) != 0) |
|||
#define CGEN_ATTR_CGEN_INSN_OPTIONAL_MUL_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_OPTIONAL_MUL_INSN)) != 0) |
|||
#define CGEN_ATTR_CGEN_INSN_OPTIONAL_DIV_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_OPTIONAL_DIV_INSN)) != 0) |
|||
#define CGEN_ATTR_CGEN_INSN_OPTIONAL_DEBUG_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_OPTIONAL_DEBUG_INSN)) != 0) |
|||
#define CGEN_ATTR_CGEN_INSN_OPTIONAL_LDZ_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_OPTIONAL_LDZ_INSN)) != 0) |
|||
#define CGEN_ATTR_CGEN_INSN_OPTIONAL_ABS_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_OPTIONAL_ABS_INSN)) != 0) |
|||
#define CGEN_ATTR_CGEN_INSN_OPTIONAL_AVE_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_OPTIONAL_AVE_INSN)) != 0) |
|||
#define CGEN_ATTR_CGEN_INSN_OPTIONAL_MINMAX_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_OPTIONAL_MINMAX_INSN)) != 0) |
|||
#define CGEN_ATTR_CGEN_INSN_OPTIONAL_CLIP_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_OPTIONAL_CLIP_INSN)) != 0) |
|||
#define CGEN_ATTR_CGEN_INSN_OPTIONAL_SAT_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_OPTIONAL_SAT_INSN)) != 0) |
|||
#define CGEN_ATTR_CGEN_INSN_OPTIONAL_UCI_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_OPTIONAL_UCI_INSN)) != 0) |
|||
#define CGEN_ATTR_CGEN_INSN_OPTIONAL_DSP_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_OPTIONAL_DSP_INSN)) != 0) |
|||
#define CGEN_ATTR_CGEN_INSN_OPTIONAL_CP_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_OPTIONAL_CP_INSN)) != 0) |
|||
#define CGEN_ATTR_CGEN_INSN_OPTIONAL_CP64_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_OPTIONAL_CP64_INSN)) != 0) |
|||
#define CGEN_ATTR_CGEN_INSN_OPTIONAL_VLIW64_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_OPTIONAL_VLIW64)) != 0) |
|||
#define CGEN_ATTR_CGEN_INSN_MAY_TRAP_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_MAY_TRAP)) != 0) |
|||
#define CGEN_ATTR_CGEN_INSN_VLIW_ALONE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_VLIW_ALONE)) != 0) |
|||
#define CGEN_ATTR_CGEN_INSN_VLIW_NO_CORE_NOP_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_VLIW_NO_CORE_NOP)) != 0) |
|||
#define CGEN_ATTR_CGEN_INSN_VLIW_NO_COP_NOP_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_VLIW_NO_COP_NOP)) != 0) |
|||
#define CGEN_ATTR_CGEN_INSN_VLIW64_NO_MATCHING_NOP_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_VLIW64_NO_MATCHING_NOP)) != 0) |
|||
#define CGEN_ATTR_CGEN_INSN_VLIW32_NO_MATCHING_NOP_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_VLIW32_NO_MATCHING_NOP)) != 0) |
|||
#define CGEN_ATTR_CGEN_INSN_VOLATILE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_VOLATILE)) != 0) |
|||
|
|||
/* cgen.h uses things we just defined. */ |
|||
#include "opcode/cgen.h" |
|||
|
|||
extern const struct cgen_ifld mep_cgen_ifld_table[]; |
|||
|
|||
/* Attributes. */ |
|||
extern const CGEN_ATTR_TABLE mep_cgen_hardware_attr_table[]; |
|||
extern const CGEN_ATTR_TABLE mep_cgen_ifield_attr_table[]; |
|||
extern const CGEN_ATTR_TABLE mep_cgen_operand_attr_table[]; |
|||
extern const CGEN_ATTR_TABLE mep_cgen_insn_attr_table[]; |
|||
|
|||
/* Hardware decls. */ |
|||
|
|||
extern CGEN_KEYWORD mep_cgen_opval_h_gpr; |
|||
extern CGEN_KEYWORD mep_cgen_opval_h_csr; |
|||
extern CGEN_KEYWORD mep_cgen_opval_h_cr64; |
|||
extern CGEN_KEYWORD mep_cgen_opval_h_cr; |
|||
extern CGEN_KEYWORD mep_cgen_opval_h_ccr; |
|||
extern CGEN_KEYWORD mep_cgen_opval_h_cr_fmax; |
|||
extern CGEN_KEYWORD mep_cgen_opval_h_ccr_fmax; |
|||
|
|||
extern const CGEN_HW_ENTRY mep_cgen_hw_table[]; |
|||
|
|||
|
|||
|
|||
#endif /* MEP_CPU_H */ |
|||
File diff suppressed because it is too large
File diff suppressed because it is too large
File diff suppressed because it is too large
@ -0,0 +1,294 @@ |
|||
/* Instruction opcode header for mep.
|
|||
|
|||
THIS FILE IS MACHINE GENERATED WITH CGEN. |
|||
|
|||
Copyright 1996-2005 Free Software Foundation, Inc. |
|||
|
|||
This file is part of the GNU Binutils and/or GDB, the GNU debugger. |
|||
|
|||
This program is free software; you can redistribute it and/or modify |
|||
it under the terms of the GNU General Public License as published by |
|||
the Free Software Foundation; either version 2, or (at your option) |
|||
any later version. |
|||
|
|||
This program is distributed in the hope that it will be useful, |
|||
but WITHOUT ANY WARRANTY; without even the implied warranty of |
|||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|||
GNU General Public License for more details. |
|||
|
|||
You should have received a copy of the GNU General Public License along |
|||
with this program; if not, write to the Free Software Foundation, Inc., |
|||
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. |
|||
|
|||
*/ |
|||
|
|||
#ifndef MEP_OPC_H |
|||
#define MEP_OPC_H |
|||
|
|||
/* -- opc.h */ |
|||
|
|||
#undef CGEN_DIS_HASH_SIZE |
|||
#define CGEN_DIS_HASH_SIZE 1 |
|||
|
|||
#undef CGEN_DIS_HASH |
|||
#define CGEN_DIS_HASH(buffer, insn) 0 |
|||
|
|||
#define CGEN_VERBOSE_ASSEMBLER_ERRORS |
|||
|
|||
typedef struct |
|||
{ |
|||
char * name; |
|||
int config_enum; |
|||
unsigned cpu_flag; |
|||
int big_endian; |
|||
int vliw_bits; |
|||
CGEN_ATTR_VALUE_BITSET_TYPE cop16_isa; |
|||
CGEN_ATTR_VALUE_BITSET_TYPE cop32_isa; |
|||
CGEN_ATTR_VALUE_BITSET_TYPE cop48_isa; |
|||
CGEN_ATTR_VALUE_BITSET_TYPE cop64_isa; |
|||
CGEN_ATTR_VALUE_BITSET_TYPE cop_isa; |
|||
CGEN_ATTR_VALUE_BITSET_TYPE core_isa; |
|||
unsigned int option_mask; |
|||
} mep_config_map_struct; |
|||
|
|||
extern mep_config_map_struct mep_config_map[]; |
|||
extern int mep_config_index; |
|||
|
|||
extern void init_mep_all_core_isas_mask (void); |
|||
extern void init_mep_all_cop_isas_mask (void); |
|||
extern CGEN_ATTR_VALUE_BITSET_TYPE mep_cop_isa (void); |
|||
|
|||
#define MEP_CONFIG (mep_config_map[mep_config_index].config_enum) |
|||
#define MEP_CPU (mep_config_map[mep_config_index].cpu_flag) |
|||
#define MEP_OMASK (mep_config_map[mep_config_index].option_mask) |
|||
#define MEP_VLIW (mep_config_map[mep_config_index].vliw_bits > 0) |
|||
#define MEP_VLIW32 (mep_config_map[mep_config_index].vliw_bits == 32) |
|||
#define MEP_VLIW64 (mep_config_map[mep_config_index].vliw_bits == 64) |
|||
#define MEP_COP16_ISA (mep_config_map[mep_config_index].cop16_isa) |
|||
#define MEP_COP32_ISA (mep_config_map[mep_config_index].cop32_isa) |
|||
#define MEP_COP48_ISA (mep_config_map[mep_config_index].cop48_isa) |
|||
#define MEP_COP64_ISA (mep_config_map[mep_config_index].cop64_isa) |
|||
#define MEP_COP_ISA (mep_config_map[mep_config_index].cop_isa) |
|||
#define MEP_CORE_ISA (mep_config_map[mep_config_index].core_isa) |
|||
|
|||
extern int mep_insn_supported_by_isa (const CGEN_INSN *, CGEN_ATTR_VALUE_BITSET_TYPE *); |
|||
|
|||
/* A mask for all ISAs executed by the core. */ |
|||
#define MEP_ALL_CORE_ISAS_MASK mep_all_core_isas_mask |
|||
extern CGEN_ATTR_VALUE_BITSET_TYPE mep_all_core_isas_mask; |
|||
|
|||
#define MEP_INSN_CORE_P(insn) ( \ |
|||
init_mep_all_core_isas_mask (), \ |
|||
mep_insn_supported_by_isa (insn, & MEP_ALL_CORE_ISAS_MASK) \ |
|||
) |
|||
|
|||
/* A mask for all ISAs executed by a VLIW coprocessor. */ |
|||
#define MEP_ALL_COP_ISAS_MASK mep_all_cop_isas_mask |
|||
extern CGEN_ATTR_VALUE_BITSET_TYPE mep_all_cop_isas_mask; |
|||
|
|||
#define MEP_INSN_COP_P(insn) ( \ |
|||
init_mep_all_cop_isas_mask (), \ |
|||
mep_insn_supported_by_isa (insn, & MEP_ALL_COP_ISAS_MASK) \ |
|||
) |
|||
|
|||
extern int mep_cgen_insn_supported (CGEN_CPU_DESC, const CGEN_INSN *); |
|||
|
|||
/* -- asm.c */ |
|||
/* Enum declaration for mep instruction types. */ |
|||
typedef enum cgen_insn_type { |
|||
MEP_INSN_INVALID, MEP_INSN_SB, MEP_INSN_SH, MEP_INSN_SW |
|||
, MEP_INSN_LB, MEP_INSN_LH, MEP_INSN_LW, MEP_INSN_LBU |
|||
, MEP_INSN_LHU, MEP_INSN_SW_SP, MEP_INSN_LW_SP, MEP_INSN_SB_TP |
|||
, MEP_INSN_SH_TP, MEP_INSN_SW_TP, MEP_INSN_LB_TP, MEP_INSN_LH_TP |
|||
, MEP_INSN_LW_TP, MEP_INSN_LBU_TP, MEP_INSN_LHU_TP, MEP_INSN_SB16 |
|||
, MEP_INSN_SH16, MEP_INSN_SW16, MEP_INSN_LB16, MEP_INSN_LH16 |
|||
, MEP_INSN_LW16, MEP_INSN_LBU16, MEP_INSN_LHU16, MEP_INSN_SW24 |
|||
, MEP_INSN_LW24, MEP_INSN_EXTB, MEP_INSN_EXTH, MEP_INSN_EXTUB |
|||
, MEP_INSN_EXTUH, MEP_INSN_SSARB, MEP_INSN_MOV, MEP_INSN_MOVI8 |
|||
, MEP_INSN_MOVI16, MEP_INSN_MOVU24, MEP_INSN_MOVU16, MEP_INSN_MOVH |
|||
, MEP_INSN_ADD3, MEP_INSN_ADD, MEP_INSN_ADD3I, MEP_INSN_ADVCK3 |
|||
, MEP_INSN_SUB, MEP_INSN_SBVCK3, MEP_INSN_NEG, MEP_INSN_SLT3 |
|||
, MEP_INSN_SLTU3, MEP_INSN_SLT3I, MEP_INSN_SLTU3I, MEP_INSN_SL1AD3 |
|||
, MEP_INSN_SL2AD3, MEP_INSN_ADD3X, MEP_INSN_SLT3X, MEP_INSN_SLTU3X |
|||
, MEP_INSN_OR, MEP_INSN_AND, MEP_INSN_XOR, MEP_INSN_NOR |
|||
, MEP_INSN_OR3, MEP_INSN_AND3, MEP_INSN_XOR3, MEP_INSN_SRA |
|||
, MEP_INSN_SRL, MEP_INSN_SLL, MEP_INSN_SRAI, MEP_INSN_SRLI |
|||
, MEP_INSN_SLLI, MEP_INSN_SLL3, MEP_INSN_FSFT, MEP_INSN_BRA |
|||
, MEP_INSN_BEQZ, MEP_INSN_BNEZ, MEP_INSN_BEQI, MEP_INSN_BNEI |
|||
, MEP_INSN_BLTI, MEP_INSN_BGEI, MEP_INSN_BEQ, MEP_INSN_BNE |
|||
, MEP_INSN_BSR12, MEP_INSN_BSR24, MEP_INSN_JMP, MEP_INSN_JMP24 |
|||
, MEP_INSN_JSR, MEP_INSN_RET, MEP_INSN_REPEAT, MEP_INSN_EREPEAT |
|||
, MEP_INSN_STC_LP, MEP_INSN_STC_HI, MEP_INSN_STC_LO, MEP_INSN_STC |
|||
, MEP_INSN_LDC_LP, MEP_INSN_LDC_HI, MEP_INSN_LDC_LO, MEP_INSN_LDC |
|||
, MEP_INSN_DI, MEP_INSN_EI, MEP_INSN_RETI, MEP_INSN_HALT |
|||
, MEP_INSN_SLEEP, MEP_INSN_SWI, MEP_INSN_BREAK, MEP_INSN_SYNCM |
|||
, MEP_INSN_STCB, MEP_INSN_LDCB, MEP_INSN_BSETM, MEP_INSN_BCLRM |
|||
, MEP_INSN_BNOTM, MEP_INSN_BTSTM, MEP_INSN_TAS, MEP_INSN_CACHE |
|||
, MEP_INSN_MUL, MEP_INSN_MULU, MEP_INSN_MULR, MEP_INSN_MULRU |
|||
, MEP_INSN_MADD, MEP_INSN_MADDU, MEP_INSN_MADDR, MEP_INSN_MADDRU |
|||
, MEP_INSN_DIV, MEP_INSN_DIVU, MEP_INSN_DRET, MEP_INSN_DBREAK |
|||
, MEP_INSN_LDZ, MEP_INSN_ABS, MEP_INSN_AVE, MEP_INSN_MIN |
|||
, MEP_INSN_MAX, MEP_INSN_MINU, MEP_INSN_MAXU, MEP_INSN_CLIP |
|||
, MEP_INSN_CLIPU, MEP_INSN_SADD, MEP_INSN_SSUB, MEP_INSN_SADDU |
|||
, MEP_INSN_SSUBU, MEP_INSN_SWCP, MEP_INSN_LWCP, MEP_INSN_SMCP |
|||
, MEP_INSN_LMCP, MEP_INSN_SWCPI, MEP_INSN_LWCPI, MEP_INSN_SMCPI |
|||
, MEP_INSN_LMCPI, MEP_INSN_SWCP16, MEP_INSN_LWCP16, MEP_INSN_SMCP16 |
|||
, MEP_INSN_LMCP16, MEP_INSN_SBCPA, MEP_INSN_LBCPA, MEP_INSN_SHCPA |
|||
, MEP_INSN_LHCPA, MEP_INSN_SWCPA, MEP_INSN_LWCPA, MEP_INSN_SMCPA |
|||
, MEP_INSN_LMCPA, MEP_INSN_SBCPM0, MEP_INSN_LBCPM0, MEP_INSN_SHCPM0 |
|||
, MEP_INSN_LHCPM0, MEP_INSN_SWCPM0, MEP_INSN_LWCPM0, MEP_INSN_SMCPM0 |
|||
, MEP_INSN_LMCPM0, MEP_INSN_SBCPM1, MEP_INSN_LBCPM1, MEP_INSN_SHCPM1 |
|||
, MEP_INSN_LHCPM1, MEP_INSN_SWCPM1, MEP_INSN_LWCPM1, MEP_INSN_SMCPM1 |
|||
, MEP_INSN_LMCPM1, MEP_INSN_BCPEQ, MEP_INSN_BCPNE, MEP_INSN_BCPAT |
|||
, MEP_INSN_BCPAF, MEP_INSN_SYNCCP, MEP_INSN_JSRV, MEP_INSN_BSRV |
|||
, MEP_INSN_SIM_SYSCALL, MEP_INSN_RI_0, MEP_INSN_RI_1, MEP_INSN_RI_2 |
|||
, MEP_INSN_RI_3, MEP_INSN_RI_4, MEP_INSN_RI_5, MEP_INSN_RI_6 |
|||
, MEP_INSN_RI_7, MEP_INSN_RI_8, MEP_INSN_RI_9, MEP_INSN_RI_10 |
|||
, MEP_INSN_RI_11, MEP_INSN_RI_12, MEP_INSN_RI_13, MEP_INSN_RI_14 |
|||
, MEP_INSN_RI_15, MEP_INSN_RI_17, MEP_INSN_RI_20, MEP_INSN_RI_21 |
|||
, MEP_INSN_RI_22, MEP_INSN_RI_23, MEP_INSN_RI_24, MEP_INSN_RI_25 |
|||
, MEP_INSN_RI_26, MEP_INSN_RI_16, MEP_INSN_RI_18, MEP_INSN_RI_19 |
|||
, MEP_INSN_FADDS, MEP_INSN_FSUBS, MEP_INSN_FMULS, MEP_INSN_FDIVS |
|||
, MEP_INSN_FSQRTS, MEP_INSN_FABSS, MEP_INSN_FNEGS, MEP_INSN_FMOVS |
|||
, MEP_INSN_FROUNDWS, MEP_INSN_FTRUNCWS, MEP_INSN_FCEILWS, MEP_INSN_FFLOORWS |
|||
, MEP_INSN_FCVTWS, MEP_INSN_FCVTSW, MEP_INSN_FCMPFS, MEP_INSN_FCMPUS |
|||
, MEP_INSN_FCMPES, MEP_INSN_FCMPUES, MEP_INSN_FCMPLS, MEP_INSN_FCMPULS |
|||
, MEP_INSN_FCMPLES, MEP_INSN_FCMPULES, MEP_INSN_FCMPFIS, MEP_INSN_FCMPUIS |
|||
, MEP_INSN_FCMPEIS, MEP_INSN_FCMPUEIS, MEP_INSN_FCMPLIS, MEP_INSN_FCMPULIS |
|||
, MEP_INSN_FCMPLEIS, MEP_INSN_FCMPULEIS, MEP_INSN_CMOV_FRN_RM, MEP_INSN_CMOV_RM_FRN |
|||
, MEP_INSN_CMOVC_CCRN_RM, MEP_INSN_CMOVC_RM_CCRN |
|||
} CGEN_INSN_TYPE; |
|||
|
|||
/* Index of `invalid' insn place holder. */ |
|||
#define CGEN_INSN_INVALID MEP_INSN_INVALID |
|||
|
|||
/* Total number of insns in table. */ |
|||
#define MAX_INSNS ((int) MEP_INSN_CMOVC_RM_CCRN + 1) |
|||
|
|||
/* This struct records data prior to insertion or after extraction. */ |
|||
struct cgen_fields |
|||
{ |
|||
int length; |
|||
long f_nil; |
|||
long f_anyof; |
|||
long f_major; |
|||
long f_rn; |
|||
long f_rn3; |
|||
long f_rm; |
|||
long f_rl; |
|||
long f_sub2; |
|||
long f_sub3; |
|||
long f_sub4; |
|||
long f_ext; |
|||
long f_crn; |
|||
long f_csrn_hi; |
|||
long f_csrn_lo; |
|||
long f_csrn; |
|||
long f_crnx_hi; |
|||
long f_crnx_lo; |
|||
long f_crnx; |
|||
long f_0; |
|||
long f_1; |
|||
long f_2; |
|||
long f_3; |
|||
long f_4; |
|||
long f_5; |
|||
long f_6; |
|||
long f_7; |
|||
long f_8; |
|||
long f_9; |
|||
long f_10; |
|||
long f_11; |
|||
long f_12; |
|||
long f_13; |
|||
long f_14; |
|||
long f_15; |
|||
long f_16; |
|||
long f_17; |
|||
long f_18; |
|||
long f_19; |
|||
long f_20; |
|||
long f_21; |
|||
long f_22; |
|||
long f_23; |
|||
long f_24; |
|||
long f_25; |
|||
long f_26; |
|||
long f_27; |
|||
long f_28; |
|||
long f_29; |
|||
long f_30; |
|||
long f_31; |
|||
long f_8s8a2; |
|||
long f_12s4a2; |
|||
long f_17s16a2; |
|||
long f_24s5a2n_hi; |
|||
long f_24s5a2n_lo; |
|||
long f_24s5a2n; |
|||
long f_24u5a2n_hi; |
|||
long f_24u5a2n_lo; |
|||
long f_24u5a2n; |
|||
long f_2u6; |
|||
long f_7u9; |
|||
long f_7u9a2; |
|||
long f_7u9a4; |
|||
long f_16s16; |
|||
long f_2u10; |
|||
long f_3u5; |
|||
long f_4u8; |
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long f_5u8; |
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long f_5u24; |
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long f_6s8; |
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long f_8s8; |
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long f_16u16; |
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long f_12u16; |
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long f_3u29; |
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long f_8s24; |
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long f_8s24a2; |
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long f_8s24a4; |
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long f_8s24a8; |
|||
long f_24u8a4n_hi; |
|||
long f_24u8a4n_lo; |
|||
long f_24u8a4n; |
|||
long f_24u8n_hi; |
|||
long f_24u8n_lo; |
|||
long f_24u8n; |
|||
long f_24u4n_hi; |
|||
long f_24u4n_lo; |
|||
long f_24u4n; |
|||
long f_callnum; |
|||
long f_ccrn_hi; |
|||
long f_ccrn_lo; |
|||
long f_ccrn; |
|||
long f_fmax_0_4; |
|||
long f_fmax_4_4; |
|||
long f_fmax_8_4; |
|||
long f_fmax_12_4; |
|||
long f_fmax_16_4; |
|||
long f_fmax_20_4; |
|||
long f_fmax_24_4; |
|||
long f_fmax_28_1; |
|||
long f_fmax_29_1; |
|||
long f_fmax_30_1; |
|||
long f_fmax_31_1; |
|||
long f_fmax_frd; |
|||
long f_fmax_frn; |
|||
long f_fmax_frm; |
|||
long f_fmax_rm; |
|||
}; |
|||
|
|||
#define CGEN_INIT_PARSE(od) \ |
|||
{\ |
|||
} |
|||
#define CGEN_INIT_INSERT(od) \ |
|||
{\ |
|||
} |
|||
#define CGEN_INIT_EXTRACT(od) \ |
|||
{\ |
|||
} |
|||
#define CGEN_INIT_PRINT(od) \ |
|||
{\ |
|||
} |
|||
|
|||
|
|||
#endif /* MEP_OPC_H */ |
|||
Loading…
Reference in new issue