riscv
/
binutils-gdb
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity
Browse Source

sim regen 

This regenerates sim files.

Tested with the following tools from a recent binutils build in
sim-site-config.exp, plus a few cross compilers.

set AS_FOR_TARGET_AARCH64 "/home/alan/build/gas/aarch64-linux-gnu/gas/as-new"
set LD_FOR_TARGET_AARCH64 "/home/alan/build/gas/aarch64-linux-gnu/ld/ld-new"
set CC_FOR_TARGET_AARCH64 "aarch64-linux-gnu-gcc"
set AS_FOR_TARGET_ARM "/home/alan/build/gas/arm-linux-gnueabi/gas/as-new"
set LD_FOR_TARGET_ARM "/home/alan/build/gas/arm-linux-gnueabi/ld/ld-new"
set CC_FOR_TARGET_ARM "arm-linux-gnueabi-gcc"
set AS_FOR_TARGET_AVR "/home/alan/build/gas/avr-elf/gas/as-new"
set LD_FOR_TARGET_AVR "/home/alan/build/gas/avr-elf/ld/ld-new"
set CC_FOR_TARGET_AVR ""
set AS_FOR_TARGET_BFIN "/home/alan/build/gas/bfin-elf/gas/as-new"
set LD_FOR_TARGET_BFIN "/home/alan/build/gas/bfin-elf/ld/ld-new"
set CC_FOR_TARGET_BFIN ""
set AS_FOR_TARGET_BPF "/home/alan/build/gas/bpf-none/gas/as-new"
set LD_FOR_TARGET_BPF "/home/alan/build/gas/bpf-none/ld/ld-new"
set CC_FOR_TARGET_BPF ""
set AS_FOR_TARGET_CR16 "/home/alan/build/gas/cr16-elf/gas/as-new"
set LD_FOR_TARGET_CR16 "/home/alan/build/gas/cr16-elf/ld/ld-new"
set CC_FOR_TARGET_CR16 ""
set AS_FOR_TARGET_CRIS "/home/alan/build/gas/cris-elf/gas/as-new"
set LD_FOR_TARGET_CRIS "/home/alan/build/gas/cris-elf/ld/ld-new"
set CC_FOR_TARGET_CRIS ""
set AS_FOR_TARGET_D10V "/home/alan/build/gas/d10v-elf/gas/as-new"
set LD_FOR_TARGET_D10V "/home/alan/build/gas/d10v-elf/ld/ld-new"
set CC_FOR_TARGET_D10V ""
set AS_FOR_TARGET_FRV "/home/alan/build/gas/frv-elf/gas/as-new"
set LD_FOR_TARGET_FRV "/home/alan/build/gas/frv-elf/ld/ld-new"
set CC_FOR_TARGET_FRV ""
set AS_FOR_TARGET_FT32 "/home/alan/build/gas/ft32-elf/gas/as-new"
set LD_FOR_TARGET_FT32 "/home/alan/build/gas/ft32-elf/ld/ld-new"
set CC_FOR_TARGET_FT32 ""
set AS_FOR_TARGET_H8300 "/home/alan/build/gas/h8300-elf/gas/as-new"
set LD_FOR_TARGET_H8300 "/home/alan/build/gas/h8300-elf/ld/ld-new"
set CC_FOR_TARGET_H8300 ""
set AS_FOR_TARGET_IQ2000 "/home/alan/build/gas/iq2000-elf/gas/as-new"
set LD_FOR_TARGET_IQ2000 "/home/alan/build/gas/iq2000-elf/ld/ld-new"
set CC_FOR_TARGET_IQ2000 ""
set AS_FOR_TARGET_LM32 "/home/alan/build/gas/lm32-linux-gnu/gas/as-new"
set LD_FOR_TARGET_LM32 "/home/alan/build/gas/lm32-linux-gnu/ld/ld-new"
set CC_FOR_TARGET_LM32 ""
set AS_FOR_TARGET_M32C "/home/alan/build/gas/m32c-elf/gas/as-new"
set LD_FOR_TARGET_M32C "/home/alan/build/gas/m32c-elf/ld/ld-new"
set CC_FOR_TARGET_M32C ""
set AS_FOR_TARGET_M32R "/home/alan/build/gas/m32r-elf/gas/as-new"
set LD_FOR_TARGET_M32R "/home/alan/build/gas/m32r-elf/ld/ld-new"
set CC_FOR_TARGET_M32R ""
set AS_FOR_TARGET_M68HC11 "/home/alan/build/gas/m68hc11-elf/gas/as-new"
set LD_FOR_TARGET_M68HC11 "/home/alan/build/gas/m68hc11-elf/ld/ld-new"
set CC_FOR_TARGET_M68HC11 ""
set AS_FOR_TARGET_MCORE "/home/alan/build/gas/mcore-elf/gas/as-new"
set LD_FOR_TARGET_MCORE "/home/alan/build/gas/mcore-elf/ld/ld-new"
set CC_FOR_TARGET_MCORE ""
set AS_FOR_TARGET_MICROBLAZE "/home/alan/build/gas/microblaze-linux-gnu/gas/as-new"
set LD_FOR_TARGET_MICROBLAZE "/home/alan/build/gas/microblaze-linux-gnu/ld/ld-new"
set CC_FOR_TARGET_MICROBLAZE "microblaze-linux-gnu-gcc"
set AS_FOR_TARGET_MIPS "/home/alan/build/gas/mips-linux-gnu/gas/as-new"
set LD_FOR_TARGET_MIPS "/home/alan/build/gas/mips-linux-gnu/ld/ld-new"
set CC_FOR_TARGET_MIPS "mips-linux-gnu-gcc"
set AS_FOR_TARGET_MN10300 "/home/alan/build/gas/mn10300-elf/gas/as-new"
set LD_FOR_TARGET_MN10300 "/home/alan/build/gas/mn10300-elf/ld/ld-new"
set CC_FOR_TARGET_MN10300 ""
set AS_FOR_TARGET_MOXIE "/home/alan/build/gas/moxie-elf/gas/as-new"
set LD_FOR_TARGET_MOXIE "/home/alan/build/gas/moxie-elf/ld/ld-new"
set CC_FOR_TARGET_MOXIE ""
set AS_FOR_TARGET_MSP430 "/home/alan/build/gas/msp430-elf/gas/as-new"
set LD_FOR_TARGET_MSP430 "/home/alan/build/gas/msp430-elf/ld/ld-new"
set CC_FOR_TARGET_MSP430 ""
set AS_FOR_TARGET_OR1K "/home/alan/build/gas/or1k-linux-gnu/gas/as-new"
set LD_FOR_TARGET_OR1K "/home/alan/build/gas/or1k-linux-gnu/ld/ld-new"
set CC_FOR_TARGET_OR1K ""
set AS_FOR_TARGET_PPC "/home/alan/build/gas/powerpc-linux-gnu/gas/as-new"
set LD_FOR_TARGET_PPC "/home/alan/build/gas/powerpc-linux-gnu/ld/ld-new"
set CC_FOR_TARGET_PPC "powerpc-linux-gnu-gcc"
set AS_FOR_TARGET_PRU "/home/alan/build/gas/pru-elf/gas/as-new"
set LD_FOR_TARGET_PRU "/home/alan/build/gas/pru-elf/ld/ld-new"
set CC_FOR_TARGET_PRU ""
set AS_FOR_TARGET_RISCV "/home/alan/build/gas/riscv32-elf/gas/as-new"
set LD_FOR_TARGET_RISCV "/home/alan/build/gas/riscv32-elf/ld/ld-new"
set CC_FOR_TARGET_RISCV ""
set AS_FOR_TARGET_RL78 "/home/alan/build/gas/rl78-elf/gas/as-new"
set LD_FOR_TARGET_RL78 "/home/alan/build/gas/rl78-elf/ld/ld-new"
set CC_FOR_TARGET_RL78 ""
set AS_FOR_TARGET_RX "/home/alan/build/gas/rx-elf/gas/as-new"
set LD_FOR_TARGET_RX "/home/alan/build/gas/rx-elf/ld/ld-new"
set CC_FOR_TARGET_RX ""
set AS_FOR_TARGET_SH "/home/alan/build/gas/sh-rtems/gas/as-new"
set LD_FOR_TARGET_SH "/home/alan/build/gas/sh-rtems/ld/ld-new"
set CC_FOR_TARGET_SH ""
set AS_FOR_TARGET_ERC32 ""
set LD_FOR_TARGET_ERC32 ""
set CC_FOR_TARGET_ERC32 ""
set AS_FOR_TARGET_V850 "/home/alan/build/gas/v850-elf/gas/as-new"
set LD_FOR_TARGET_V850 "/home/alan/build/gas/v850-elf/ld/ld-new"
set CC_FOR_TARGET_V850 ""

Results both before and after were:
FAIL: crisv10 mem1.ms (execution)
FAIL: crisv10 mem2.ms (execution)
FAIL: crisv32 mem1.ms (execution)
FAIL: crisv32 mem2.ms (execution)
FAIL: microblaze fail.s (execution)
FAIL: microblaze pass.s (execution)
expected passes            5288
unexpected failures        6
expected failures          3
untested testcases         373
unsupported tests          14
gdb-14-branch
Alan Modra 3 years ago
parent
c7631501b2
commit
9d4f36166d
70 changed files with 14594 additions and 357 deletions
Whitespace
Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL
Split View
Diff Options
Show Stats Download Patch File Download Diff File
  1. 5
      sim/cris/arch.c
  2. 13
      sim/cris/arch.h
  3. 5
      sim/cris/cpuall.h
  4. 5
      sim/cris/cpuv10.c
  5. 5
      sim/cris/cpuv10.h
  6. 5
      sim/cris/cpuv32.c
  7. 5
      sim/cris/cpuv32.h
  8. 5
      sim/cris/decodev10.c
  9. 6
      sim/cris/decodev10.h
  10. 5
      sim/cris/decodev32.c
  11. 7
      sim/cris/decodev32.h
  12. 5
      sim/cris/modelv10.c
  13. 5
      sim/cris/modelv32.c
  14. 5
      sim/cris/semcrisv10f-switch.c
  15. 5
      sim/cris/semcrisv32f-switch.c
  16. 5
      sim/frv/arch.c
  17. 13
      sim/frv/arch.h
  18. 5
      sim/frv/cpu.c
  19. 21
      sim/frv/cpu.h
  20. 5
      sim/frv/cpuall.h
  21. 27
      sim/frv/decode.c
  22. 5
      sim/frv/decode.h
  23. 5
      sim/frv/model.c
  24. 5
      sim/frv/sem.c
  25. 5
      sim/iq2000/arch.c
  26. 13
      sim/iq2000/arch.h
  27. 5
      sim/iq2000/cpu.c
  28. 13
      sim/iq2000/cpu.h
  29. 5
      sim/iq2000/cpuall.h
  30. 289
      sim/iq2000/decode.c
  31. 9
      sim/iq2000/decode.h
  32. 5
      sim/iq2000/model.c
  33. 9
      sim/iq2000/sem-switch.c
  34. 9
      sim/iq2000/sem.c
  35. 5
      sim/lm32/arch.c
  36. 13
      sim/lm32/arch.h
  37. 5
      sim/lm32/cpu.c
  38. 9
      sim/lm32/cpu.h
  39. 5
      sim/lm32/cpuall.h
  40. 13
      sim/lm32/decode.c
  41. 5
      sim/lm32/decode.h
  42. 5
      sim/lm32/model.c
  43. 5
      sim/lm32/sem-switch.c
  44. 5
      sim/lm32/sem.c
  45. 5
      sim/m32r/arch.c
  46. 13
      sim/m32r/arch.h
  47. 5
      sim/m32r/cpu.c
  48. 13
      sim/m32r/cpu.h
  49. 5
      sim/m32r/cpu2.c
  50. 13
      sim/m32r/cpu2.h
  51. 5
      sim/m32r/cpuall.h
  52. 5
      sim/m32r/cpux.c
  53. 13
      sim/m32r/cpux.h
  54. 23
      sim/m32r/decode.c
  55. 5
      sim/m32r/decode.h
  56. 27
      sim/m32r/decode2.c
  57. 5
      sim/m32r/decode2.h
  58. 27
      sim/m32r/decodex.c
  59. 5
      sim/m32r/decodex.h
  60. 5
      sim/m32r/model.c
  61. 5
      sim/m32r/model2.c
  62. 5
      sim/m32r/modelx.c
  63. 5
      sim/m32r/sem-switch.c
  64. 5
      sim/m32r/sem.c
  65. 5
      sim/m32r/sem2-switch.c
  66. 5
      sim/m32r/semx-switch.c
  67. 4
      sim/or1k/cpu.h
  68. 12
      sim/or1k/decode.c
  69. 2
      sim/or1k/sem-switch.c
  70. 14120
      sim/semcrisv32f-switch.c

5
sim/cris/arch.c
View File

@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright 1996-2023 Free Software Foundation, Inc.
Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, see <http://www.gnu.org/licenses/>.
with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/

13
sim/cris/arch.h
View File

@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright 1996-2023 Free Software Foundation, Inc.
Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@ -17,13 +17,22 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, see <http://www.gnu.org/licenses/>.
with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
#ifndef CRIS_ARCH_H
#define CRIS_ARCH_H
#define TARGET_BIG_ENDIAN 1
#define WI SI
#define UWI USI
#define AI USI
#define IAI USI
/* Enum declaration for model types. */
typedef enum model_type {
MODEL_CRISV10, MODEL_CRISV32, MODEL_MAX

5
sim/cris/cpuall.h
View File

@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright 1996-2023 Free Software Foundation, Inc.
Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, see <http://www.gnu.org/licenses/>.
with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/

5
sim/cris/cpuv10.c
View File

@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright 1996-2023 Free Software Foundation, Inc.
Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, see <http://www.gnu.org/licenses/>.
with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/

5
sim/cris/cpuv10.h
View File

@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright 1996-2023 Free Software Foundation, Inc.
Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, see <http://www.gnu.org/licenses/>.
with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/

5
sim/cris/cpuv32.c
View File

@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright 1996-2023 Free Software Foundation, Inc.
Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, see <http://www.gnu.org/licenses/>.
with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/

5
sim/cris/cpuv32.h
View File

@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright 1996-2023 Free Software Foundation, Inc.
Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, see <http://www.gnu.org/licenses/>.
with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/

5
sim/cris/decodev10.c
View File

@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright 1996-2023 Free Software Foundation, Inc.
Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, see <http://www.gnu.org/licenses/>.
with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/

6
sim/cris/decodev10.h
View File

@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright 1996-2023 Free Software Foundation, Inc.
Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, see <http://www.gnu.org/licenses/>.
with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
@ -30,7 +31,6 @@ extern const IDESC *crisv10f_decode (SIM_CPU *, IADDR,
extern void crisv10f_init_idesc_table (SIM_CPU *);
extern void crisv10f_sem_init_idesc_table (SIM_CPU *);
extern void crisv10f_semf_init_idesc_table (SIM_CPU *);
extern void crisv10f_specific_init (SIM_CPU *);
/* Enum declaration for instructions in cpu family crisv10f. */
typedef enum crisv10f_insn_type {

5
sim/cris/decodev32.c
View File

@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright 1996-2023 Free Software Foundation, Inc.
Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, see <http://www.gnu.org/licenses/>.
with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/

7
sim/cris/decodev32.h
View File

@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright 1996-2023 Free Software Foundation, Inc.
Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, see <http://www.gnu.org/licenses/>.
with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
@ -30,7 +31,6 @@ extern const IDESC *crisv32f_decode (SIM_CPU *, IADDR,
extern void crisv32f_init_idesc_table (SIM_CPU *);
extern void crisv32f_sem_init_idesc_table (SIM_CPU *);
extern void crisv32f_semf_init_idesc_table (SIM_CPU *);
extern void crisv32f_specific_init (SIM_CPU *);
/* Enum declaration for instructions in cpu family crisv32f. */
typedef enum crisv32f_insn_type {
@ -127,7 +127,6 @@ extern int crisv32f_model_crisv32_u_exec_to_sr (SIM_CPU *, const IDESC *, int /*
extern int crisv32f_model_crisv32_u_exec_movem (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*Rs*/, INT /*Rd*/);
extern int crisv32f_model_crisv32_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*Rd*/, INT /*Rs*/, INT /*Rd*/);
extern int crisv32f_model_crisv32_u_skip4 (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int crisv32f_model_crisv32_u_stall (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int crisv32f_model_crisv32_u_const32 (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int crisv32f_model_crisv32_u_const16 (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int crisv32f_model_crisv32_u_jump (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*Pd*/);

5
sim/cris/modelv10.c
View File

@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright 1996-2023 Free Software Foundation, Inc.
Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, see <http://www.gnu.org/licenses/>.
with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/

5
sim/cris/modelv32.c
View File

@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright 1996-2023 Free Software Foundation, Inc.
Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, see <http://www.gnu.org/licenses/>.
with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/

5
sim/cris/semcrisv10f-switch.c
View File

@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright 1996-2023 Free Software Foundation, Inc.
Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, see <http://www.gnu.org/licenses/>.
with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/

5
sim/cris/semcrisv32f-switch.c
View File

@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright 1996-2023 Free Software Foundation, Inc.
Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, see <http://www.gnu.org/licenses/>.
with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/

5
sim/frv/arch.c
View File

@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright 1996-2023 Free Software Foundation, Inc.
Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, see <http://www.gnu.org/licenses/>.
with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/

13
sim/frv/arch.h
View File

@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright 1996-2023 Free Software Foundation, Inc.
Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@ -17,13 +17,22 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, see <http://www.gnu.org/licenses/>.
with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
#ifndef FRV_ARCH_H
#define FRV_ARCH_H
#define TARGET_BIG_ENDIAN 1
#define WI SI
#define UWI USI
#define AI USI
#define IAI USI
/* Enum declaration for model types. */
typedef enum model_type {
MODEL_FRV, MODEL_FR550, MODEL_FR500, MODEL_TOMCAT

5
sim/frv/cpu.c
View File

@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright 1996-2023 Free Software Foundation, Inc.
Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, see <http://www.gnu.org/licenses/>.
with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/

21
sim/frv/cpu.h
View File

@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright 1996-2023 Free Software Foundation, Inc.
Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, see <http://www.gnu.org/licenses/>.
with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
@ -2191,7 +2192,7 @@ struct scache {
f_ICCi_2_null = EXTRACT_LSB0_UINT (insn, 32, 26, 2); \
f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
f_hint = EXTRACT_LSB0_UINT (insn, 32, 17, 2); \
f_label16 = ((((EXTRACT_LSB0_SINT (insn, 32, 15, 16)) << (2))) + (pc)); \
f_label16 = ((((EXTRACT_LSB0_SINT (insn, 32, 15, 16)) * (4))) + (pc)); \
#define EXTRACT_IFMT_BNO_VARS \
UINT f_pack; \
@ -2225,7 +2226,7 @@ struct scache {
f_ICCi_2 = EXTRACT_LSB0_UINT (insn, 32, 26, 2); \
f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
f_hint = EXTRACT_LSB0_UINT (insn, 32, 17, 2); \
f_label16 = ((((EXTRACT_LSB0_SINT (insn, 32, 15, 16)) << (2))) + (pc)); \
f_label16 = ((((EXTRACT_LSB0_SINT (insn, 32, 15, 16)) * (4))) + (pc)); \
#define EXTRACT_IFMT_FBRA_VARS \
UINT f_pack; \
@ -2242,7 +2243,7 @@ struct scache {
f_FCCi_2_null = EXTRACT_LSB0_UINT (insn, 32, 26, 2); \
f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
f_hint = EXTRACT_LSB0_UINT (insn, 32, 17, 2); \
f_label16 = ((((EXTRACT_LSB0_SINT (insn, 32, 15, 16)) << (2))) + (pc)); \
f_label16 = ((((EXTRACT_LSB0_SINT (insn, 32, 15, 16)) * (4))) + (pc)); \
#define EXTRACT_IFMT_FBNO_VARS \
UINT f_pack; \
@ -2276,7 +2277,7 @@ struct scache {
f_FCCi_2 = EXTRACT_LSB0_UINT (insn, 32, 26, 2); \
f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
f_hint = EXTRACT_LSB0_UINT (insn, 32, 17, 2); \
f_label16 = ((((EXTRACT_LSB0_SINT (insn, 32, 15, 16)) << (2))) + (pc)); \
f_label16 = ((((EXTRACT_LSB0_SINT (insn, 32, 15, 16)) * (4))) + (pc)); \
#define EXTRACT_IFMT_BCTRLR_VARS \
UINT f_pack; \
@ -2595,7 +2596,7 @@ struct scache {
f_labelH6 = EXTRACT_LSB0_SINT (insn, 32, 30, 6); \
f_labelL18 = EXTRACT_LSB0_UINT (insn, 32, 17, 18); \
{\
f_label24 = ((((((((f_labelH6) << (18))) | (f_labelL18))) << (2))) + (pc));\
f_label24 = ((((((((f_labelH6) * (((1) << (18))))) | (f_labelL18))) * (4))) + (pc));\
}\
#define EXTRACT_IFMT_RETT_VARS \
@ -3584,7 +3585,7 @@ struct scache {
f_u12_h = EXTRACT_LSB0_SINT (insn, 32, 17, 6); \
f_u12_l = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
{\
f_u12 = ((((f_u12_h) << (6))) | (f_u12_l));\
f_u12 = ((((f_u12_h) * (64))) | (f_u12_l));\
}\
#define EXTRACT_IFMT_MHSETHIS_VARS \
@ -3605,7 +3606,7 @@ struct scache {
f_u12_h = EXTRACT_LSB0_SINT (insn, 32, 17, 6); \
f_u12_l = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
{\
f_u12 = ((((f_u12_h) << (6))) | (f_u12_l));\
f_u12 = ((((f_u12_h) * (64))) | (f_u12_l));\
}\
#define EXTRACT_IFMT_MHDSETS_VARS \
@ -3626,7 +3627,7 @@ struct scache {
f_u12_h = EXTRACT_LSB0_SINT (insn, 32, 17, 6); \
f_u12_l = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
{\
f_u12 = ((((f_u12_h) << (6))) | (f_u12_l));\
f_u12 = ((((f_u12_h) * (64))) | (f_u12_l));\
}\
#define EXTRACT_IFMT_MHSETLOH_VARS \

5
sim/frv/cpuall.h
View File

@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright 1996-2023 Free Software Foundation, Inc.
Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, see <http://www.gnu.org/licenses/>.
with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/

27
sim/frv/decode.c
View File

@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright 1996-2023 Free Software Foundation, Inc.
Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, see <http://www.gnu.org/licenses/>.
with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
@ -26,6 +27,8 @@ This file is part of the GNU simulators.
#include "sim-main.h"
#include "sim-assert.h"
#include "cgen-mem.h"
#include "cgen-ops.h"
/* The instruction descriptor array.
This is computed at runtime. Space for it is not malloc'd to save a
@ -7302,7 +7305,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc,
SI f_label16;
f_hint = EXTRACT_LSB0_UINT (insn, 32, 17, 2);
f_label16 = ((((EXTRACT_LSB0_SINT (insn, 32, 15, 16)) << (2))) + (pc));
f_label16 = ((((EXTRACT_LSB0_SINT (insn, 32, 15, 16)) * (4))) + (pc));
/* Record the fields for the semantic handler. */
FLD (f_hint) = f_hint;
@ -7328,7 +7331,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc,
SI f_label16;
f_hint = EXTRACT_LSB0_UINT (insn, 32, 17, 2);
f_label16 = ((((EXTRACT_LSB0_SINT (insn, 32, 15, 16)) << (2))) + (pc));
f_label16 = ((((EXTRACT_LSB0_SINT (insn, 32, 15, 16)) * (4))) + (pc));
/* Record the fields for the semantic handler. */
FLD (f_hint) = f_hint;
@ -7350,7 +7353,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc,
f_ICCi_2 = EXTRACT_LSB0_UINT (insn, 32, 26, 2);
f_hint = EXTRACT_LSB0_UINT (insn, 32, 17, 2);
f_label16 = ((((EXTRACT_LSB0_SINT (insn, 32, 15, 16)) << (2))) + (pc));
f_label16 = ((((EXTRACT_LSB0_SINT (insn, 32, 15, 16)) * (4))) + (pc));
/* Record the fields for the semantic handler. */
FLD (f_ICCi_2) = f_ICCi_2;
@ -7378,7 +7381,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc,
SI f_label16;
f_hint = EXTRACT_LSB0_UINT (insn, 32, 17, 2);
f_label16 = ((((EXTRACT_LSB0_SINT (insn, 32, 15, 16)) << (2))) + (pc));
f_label16 = ((((EXTRACT_LSB0_SINT (insn, 32, 15, 16)) * (4))) + (pc));
/* Record the fields for the semantic handler. */
FLD (f_hint) = f_hint;
@ -7404,7 +7407,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc,
SI f_label16;
f_hint = EXTRACT_LSB0_UINT (insn, 32, 17, 2);
f_label16 = ((((EXTRACT_LSB0_SINT (insn, 32, 15, 16)) << (2))) + (pc));
f_label16 = ((((EXTRACT_LSB0_SINT (insn, 32, 15, 16)) * (4))) + (pc));
/* Record the fields for the semantic handler. */
FLD (f_hint) = f_hint;
@ -7426,7 +7429,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc,
f_FCCi_2 = EXTRACT_LSB0_UINT (insn, 32, 26, 2);
f_hint = EXTRACT_LSB0_UINT (insn, 32, 17, 2);
f_label16 = ((((EXTRACT_LSB0_SINT (insn, 32, 15, 16)) << (2))) + (pc));
f_label16 = ((((EXTRACT_LSB0_SINT (insn, 32, 15, 16)) * (4))) + (pc));
/* Record the fields for the semantic handler. */
FLD (f_FCCi_2) = f_FCCi_2;
@ -7936,7 +7939,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc,
f_labelH6 = EXTRACT_LSB0_SINT (insn, 32, 30, 6);
f_labelL18 = EXTRACT_LSB0_UINT (insn, 32, 17, 18);
{
f_label24 = ((((((((f_labelH6) << (18))) | (f_labelL18))) << (2))) + (pc));
f_label24 = ((((((((f_labelH6) * (((1) << (18))))) | (f_labelL18))) * (4))) + (pc));
}
/* Record the fields for the semantic handler. */
@ -9919,7 +9922,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc,
f_u12_h = EXTRACT_LSB0_SINT (insn, 32, 17, 6);
f_u12_l = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
{
f_u12 = ((((f_u12_h) << (6))) | (f_u12_l));
f_u12 = ((((f_u12_h) * (64))) | (f_u12_l));
}
/* Record the fields for the semantic handler. */
@ -9952,7 +9955,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc,
f_u12_h = EXTRACT_LSB0_SINT (insn, 32, 17, 6);
f_u12_l = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
{
f_u12 = ((((f_u12_h) << (6))) | (f_u12_l));
f_u12 = ((((f_u12_h) * (64))) | (f_u12_l));
}
/* Record the fields for the semantic handler. */
@ -9985,7 +9988,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc,
f_u12_h = EXTRACT_LSB0_SINT (insn, 32, 17, 6);
f_u12_l = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
{
f_u12 = ((((f_u12_h) << (6))) | (f_u12_l));
f_u12 = ((((f_u12_h) * (64))) | (f_u12_l));
}
/* Record the fields for the semantic handler. */

5
sim/frv/decode.h
View File

@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright 1996-2023 Free Software Foundation, Inc.
Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, see <http://www.gnu.org/licenses/>.
with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/

5
sim/frv/model.c
View File

@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright 1996-2023 Free Software Foundation, Inc.
Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, see <http://www.gnu.org/licenses/>.
with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/

5
sim/frv/sem.c
View File

@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright 1996-2023 Free Software Foundation, Inc.
Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, see <http://www.gnu.org/licenses/>.
with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/

5
sim/iq2000/arch.c
View File

@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright 1996-2023 Free Software Foundation, Inc.
Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, see <http://www.gnu.org/licenses/>.
with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/

13
sim/iq2000/arch.h
View File

@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright 1996-2023 Free Software Foundation, Inc.
Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@ -17,13 +17,22 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, see <http://www.gnu.org/licenses/>.
with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
#ifndef IQ2000_ARCH_H
#define IQ2000_ARCH_H
#define TARGET_BIG_ENDIAN 1
#define WI SI
#define UWI USI
#define AI USI
#define IAI USI
/* Enum declaration for model types. */
typedef enum model_type {
MODEL_IQ2000, MODEL_MAX

5
sim/iq2000/cpu.c
View File

@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright 1996-2023 Free Software Foundation, Inc.
Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, see <http://www.gnu.org/licenses/>.
with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/

13
sim/iq2000/cpu.h
View File

@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright 1996-2023 Free Software Foundation, Inc.
Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, see <http://www.gnu.org/licenses/>.
with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
@ -277,7 +278,7 @@ struct scache {
f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
f_offset = ((((EXTRACT_LSB0_SINT (insn, 32, 15, 16)) << (2))) + (((pc) + (4)))); \
f_offset = ((((EXTRACT_LSB0_SINT (insn, 32, 15, 16)) * (4))) + (((pc) + (4)))); \
#define EXTRACT_IFMT_BBV_VARS \
UINT f_opcode; \
@ -290,7 +291,7 @@ struct scache {
f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
f_offset = ((((EXTRACT_LSB0_SINT (insn, 32, 15, 16)) << (2))) + (((pc) + (4)))); \
f_offset = ((((EXTRACT_LSB0_SINT (insn, 32, 15, 16)) * (4))) + (((pc) + (4)))); \
#define EXTRACT_IFMT_BGEZ_VARS \
UINT f_opcode; \
@ -303,7 +304,7 @@ struct scache {
f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
f_offset = ((((EXTRACT_LSB0_SINT (insn, 32, 15, 16)) << (2))) + (((pc) + (4)))); \
f_offset = ((((EXTRACT_LSB0_SINT (insn, 32, 15, 16)) * (4))) + (((pc) + (4)))); \
#define EXTRACT_IFMT_JALR_VARS \
UINT f_opcode; \
@ -436,7 +437,7 @@ struct scache {
f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
f_offset = ((((EXTRACT_LSB0_SINT (insn, 32, 15, 16)) << (2))) + (((pc) + (4)))); \
f_offset = ((((EXTRACT_LSB0_SINT (insn, 32, 15, 16)) * (4))) + (((pc) + (4)))); \
#define EXTRACT_IFMT_CFC0_VARS \
UINT f_opcode; \

5
sim/iq2000/cpuall.h
View File

@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright 1996-2023 Free Software Foundation, Inc.
Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, see <http://www.gnu.org/licenses/>.
with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/

289
sim/iq2000/decode.c
View File

@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright 1996-2023 Free Software Foundation, Inc.
Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, see <http://www.gnu.org/licenses/>.
with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
@ -26,6 +27,8 @@ This file is part of the GNU simulators.
#include "sim-main.h"
#include "sim-assert.h"
#include "cgen-mem.h"
#include "cgen-ops.h"
/* The instruction descriptor array.
This is computed at runtime. Space for it is not malloc'd to save a
@ -105,7 +108,7 @@ static const struct insn_sem iq2000bf_insn_sem[] =
{ IQ2000_INSN_SH, IQ2000BF_INSN_SH, IQ2000BF_SFMT_SH },
{ IQ2000_INSN_SW, IQ2000BF_INSN_SW, IQ2000BF_SFMT_SW },
{ IQ2000_INSN_BREAK, IQ2000BF_INSN_BREAK, IQ2000BF_SFMT_BREAK },
{ IQ2000_INSN_SYSCALL, IQ2000BF_INSN_SYSCALL, IQ2000BF_SFMT_SYSCALL },
{ IQ2000_INSN_SYSCALL, IQ2000BF_INSN_SYSCALL, IQ2000BF_SFMT_BREAK },
{ IQ2000_INSN_ANDOUI, IQ2000BF_INSN_ANDOUI, IQ2000BF_SFMT_ANDOUI },
{ IQ2000_INSN_ORUI, IQ2000BF_INSN_ORUI, IQ2000BF_SFMT_ANDOUI },
{ IQ2000_INSN_BGTZ, IQ2000BF_INSN_BGTZ, IQ2000BF_SFMT_BGEZ },
@ -122,68 +125,68 @@ static const struct insn_sem iq2000bf_insn_sem[] =
{ IQ2000_INSN_BC0TL, IQ2000BF_INSN_BC0TL, IQ2000BF_SFMT_BCTXT },
{ IQ2000_INSN_BC3T, IQ2000BF_INSN_BC3T, IQ2000BF_SFMT_BCTXT },
{ IQ2000_INSN_BC3TL, IQ2000BF_INSN_BC3TL, IQ2000BF_SFMT_BCTXT },
{ IQ2000_INSN_CFC0, IQ2000BF_INSN_CFC0, IQ2000BF_SFMT_SYSCALL },
{ IQ2000_INSN_CFC1, IQ2000BF_INSN_CFC1, IQ2000BF_SFMT_SYSCALL },
{ IQ2000_INSN_CFC2, IQ2000BF_INSN_CFC2, IQ2000BF_SFMT_SYSCALL },
{ IQ2000_INSN_CFC3, IQ2000BF_INSN_CFC3, IQ2000BF_SFMT_SYSCALL },
{ IQ2000_INSN_CHKHDR, IQ2000BF_INSN_CHKHDR, IQ2000BF_SFMT_SYSCALL },
{ IQ2000_INSN_CTC0, IQ2000BF_INSN_CTC0, IQ2000BF_SFMT_SYSCALL },
{ IQ2000_INSN_CTC1, IQ2000BF_INSN_CTC1, IQ2000BF_SFMT_SYSCALL },
{ IQ2000_INSN_CTC2, IQ2000BF_INSN_CTC2, IQ2000BF_SFMT_SYSCALL },
{ IQ2000_INSN_CTC3, IQ2000BF_INSN_CTC3, IQ2000BF_SFMT_SYSCALL },
{ IQ2000_INSN_CFC0, IQ2000BF_INSN_CFC0, IQ2000BF_SFMT_CFC0 },
{ IQ2000_INSN_CFC1, IQ2000BF_INSN_CFC1, IQ2000BF_SFMT_CFC0 },
{ IQ2000_INSN_CFC2, IQ2000BF_INSN_CFC2, IQ2000BF_SFMT_CFC0 },
{ IQ2000_INSN_CFC3, IQ2000BF_INSN_CFC3, IQ2000BF_SFMT_CFC0 },
{ IQ2000_INSN_CHKHDR, IQ2000BF_INSN_CHKHDR, IQ2000BF_SFMT_CFC0 },
{ IQ2000_INSN_CTC0, IQ2000BF_INSN_CTC0, IQ2000BF_SFMT_CFC0 },
{ IQ2000_INSN_CTC1, IQ2000BF_INSN_CTC1, IQ2000BF_SFMT_CFC0 },
{ IQ2000_INSN_CTC2, IQ2000BF_INSN_CTC2, IQ2000BF_SFMT_CFC0 },
{ IQ2000_INSN_CTC3, IQ2000BF_INSN_CTC3, IQ2000BF_SFMT_CFC0 },
{ IQ2000_INSN_JCR, IQ2000BF_INSN_JCR, IQ2000BF_SFMT_BCTXT },
{ IQ2000_INSN_LUC32, IQ2000BF_INSN_LUC32, IQ2000BF_SFMT_SYSCALL },
{ IQ2000_INSN_LUC32L, IQ2000BF_INSN_LUC32L, IQ2000BF_SFMT_SYSCALL },
{ IQ2000_INSN_LUC64, IQ2000BF_INSN_LUC64, IQ2000BF_SFMT_SYSCALL },
{ IQ2000_INSN_LUC64L, IQ2000BF_INSN_LUC64L, IQ2000BF_SFMT_SYSCALL },
{ IQ2000_INSN_LUK, IQ2000BF_INSN_LUK, IQ2000BF_SFMT_SYSCALL },
{ IQ2000_INSN_LULCK, IQ2000BF_INSN_LULCK, IQ2000BF_SFMT_SYSCALL },
{ IQ2000_INSN_LUM32, IQ2000BF_INSN_LUM32, IQ2000BF_SFMT_SYSCALL },
{ IQ2000_INSN_LUM32L, IQ2000BF_INSN_LUM32L, IQ2000BF_SFMT_SYSCALL },
{ IQ2000_INSN_LUM64, IQ2000BF_INSN_LUM64, IQ2000BF_SFMT_SYSCALL },
{ IQ2000_INSN_LUM64L, IQ2000BF_INSN_LUM64L, IQ2000BF_SFMT_SYSCALL },
{ IQ2000_INSN_LUR, IQ2000BF_INSN_LUR, IQ2000BF_SFMT_SYSCALL },
{ IQ2000_INSN_LURL, IQ2000BF_INSN_LURL, IQ2000BF_SFMT_SYSCALL },
{ IQ2000_INSN_LUULCK, IQ2000BF_INSN_LUULCK, IQ2000BF_SFMT_SYSCALL },
{ IQ2000_INSN_MFC0, IQ2000BF_INSN_MFC0, IQ2000BF_SFMT_SYSCALL },
{ IQ2000_INSN_MFC1, IQ2000BF_INSN_MFC1, IQ2000BF_SFMT_SYSCALL },
{ IQ2000_INSN_MFC2, IQ2000BF_INSN_MFC2, IQ2000BF_SFMT_SYSCALL },
{ IQ2000_INSN_MFC3, IQ2000BF_INSN_MFC3, IQ2000BF_SFMT_SYSCALL },
{ IQ2000_INSN_MTC0, IQ2000BF_INSN_MTC0, IQ2000BF_SFMT_SYSCALL },
{ IQ2000_INSN_MTC1, IQ2000BF_INSN_MTC1, IQ2000BF_SFMT_SYSCALL },
{ IQ2000_INSN_MTC2, IQ2000BF_INSN_MTC2, IQ2000BF_SFMT_SYSCALL },
{ IQ2000_INSN_MTC3, IQ2000BF_INSN_MTC3, IQ2000BF_SFMT_SYSCALL },
{ IQ2000_INSN_PKRL, IQ2000BF_INSN_PKRL, IQ2000BF_SFMT_SYSCALL },
{ IQ2000_INSN_PKRLR1, IQ2000BF_INSN_PKRLR1, IQ2000BF_SFMT_SYSCALL },
{ IQ2000_INSN_PKRLR30, IQ2000BF_INSN_PKRLR30, IQ2000BF_SFMT_SYSCALL },
{ IQ2000_INSN_RB, IQ2000BF_INSN_RB, IQ2000BF_SFMT_SYSCALL },
{ IQ2000_INSN_RBR1, IQ2000BF_INSN_RBR1, IQ2000BF_SFMT_SYSCALL },
{ IQ2000_INSN_RBR30, IQ2000BF_INSN_RBR30, IQ2000BF_SFMT_SYSCALL },
{ IQ2000_INSN_RFE, IQ2000BF_INSN_RFE, IQ2000BF_SFMT_SYSCALL },
{ IQ2000_INSN_RX, IQ2000BF_INSN_RX, IQ2000BF_SFMT_SYSCALL },
{ IQ2000_INSN_RXR1, IQ2000BF_INSN_RXR1, IQ2000BF_SFMT_SYSCALL },
{ IQ2000_INSN_RXR30, IQ2000BF_INSN_RXR30, IQ2000BF_SFMT_SYSCALL },
{ IQ2000_INSN_SLEEP, IQ2000BF_INSN_SLEEP, IQ2000BF_SFMT_SYSCALL },
{ IQ2000_INSN_SRRD, IQ2000BF_INSN_SRRD, IQ2000BF_SFMT_SYSCALL },
{ IQ2000_INSN_SRRDL, IQ2000BF_INSN_SRRDL, IQ2000BF_SFMT_SYSCALL },
{ IQ2000_INSN_SRULCK, IQ2000BF_INSN_SRULCK, IQ2000BF_SFMT_SYSCALL },
{ IQ2000_INSN_SRWR, IQ2000BF_INSN_SRWR, IQ2000BF_SFMT_SYSCALL },
{ IQ2000_INSN_SRWRU, IQ2000BF_INSN_SRWRU, IQ2000BF_SFMT_SYSCALL },
{ IQ2000_INSN_TRAPQFL, IQ2000BF_INSN_TRAPQFL, IQ2000BF_SFMT_SYSCALL },
{ IQ2000_INSN_TRAPQNE, IQ2000BF_INSN_TRAPQNE, IQ2000BF_SFMT_SYSCALL },
{ IQ2000_INSN_TRAPREL, IQ2000BF_INSN_TRAPREL, IQ2000BF_SFMT_SYSCALL },
{ IQ2000_INSN_WB, IQ2000BF_INSN_WB, IQ2000BF_SFMT_SYSCALL },
{ IQ2000_INSN_WBU, IQ2000BF_INSN_WBU, IQ2000BF_SFMT_SYSCALL },
{ IQ2000_INSN_WBR1, IQ2000BF_INSN_WBR1, IQ2000BF_SFMT_SYSCALL },
{ IQ2000_INSN_WBR1U, IQ2000BF_INSN_WBR1U, IQ2000BF_SFMT_SYSCALL },
{ IQ2000_INSN_WBR30, IQ2000BF_INSN_WBR30, IQ2000BF_SFMT_SYSCALL },
{ IQ2000_INSN_WBR30U, IQ2000BF_INSN_WBR30U, IQ2000BF_SFMT_SYSCALL },
{ IQ2000_INSN_WX, IQ2000BF_INSN_WX, IQ2000BF_SFMT_SYSCALL },
{ IQ2000_INSN_WXU, IQ2000BF_INSN_WXU, IQ2000BF_SFMT_SYSCALL },
{ IQ2000_INSN_WXR1, IQ2000BF_INSN_WXR1, IQ2000BF_SFMT_SYSCALL },
{ IQ2000_INSN_WXR1U, IQ2000BF_INSN_WXR1U, IQ2000BF_SFMT_SYSCALL },
{ IQ2000_INSN_WXR30, IQ2000BF_INSN_WXR30, IQ2000BF_SFMT_SYSCALL },
{ IQ2000_INSN_WXR30U, IQ2000BF_INSN_WXR30U, IQ2000BF_SFMT_SYSCALL },
{ IQ2000_INSN_LUC32, IQ2000BF_INSN_LUC32, IQ2000BF_SFMT_CFC0 },
{ IQ2000_INSN_LUC32L, IQ2000BF_INSN_LUC32L, IQ2000BF_SFMT_CFC0 },
{ IQ2000_INSN_LUC64, IQ2000BF_INSN_LUC64, IQ2000BF_SFMT_CFC0 },
{ IQ2000_INSN_LUC64L, IQ2000BF_INSN_LUC64L, IQ2000BF_SFMT_CFC0 },
{ IQ2000_INSN_LUK, IQ2000BF_INSN_LUK, IQ2000BF_SFMT_CFC0 },
{ IQ2000_INSN_LULCK, IQ2000BF_INSN_LULCK, IQ2000BF_SFMT_CFC0 },
{ IQ2000_INSN_LUM32, IQ2000BF_INSN_LUM32, IQ2000BF_SFMT_CFC0 },
{ IQ2000_INSN_LUM32L, IQ2000BF_INSN_LUM32L, IQ2000BF_SFMT_CFC0 },
{ IQ2000_INSN_LUM64, IQ2000BF_INSN_LUM64, IQ2000BF_SFMT_CFC0 },
{ IQ2000_INSN_LUM64L, IQ2000BF_INSN_LUM64L, IQ2000BF_SFMT_CFC0 },
{ IQ2000_INSN_LUR, IQ2000BF_INSN_LUR, IQ2000BF_SFMT_CFC0 },
{ IQ2000_INSN_LURL, IQ2000BF_INSN_LURL, IQ2000BF_SFMT_CFC0 },
{ IQ2000_INSN_LUULCK, IQ2000BF_INSN_LUULCK, IQ2000BF_SFMT_CFC0 },
{ IQ2000_INSN_MFC0, IQ2000BF_INSN_MFC0, IQ2000BF_SFMT_CFC0 },
{ IQ2000_INSN_MFC1, IQ2000BF_INSN_MFC1, IQ2000BF_SFMT_CFC0 },
{ IQ2000_INSN_MFC2, IQ2000BF_INSN_MFC2, IQ2000BF_SFMT_CFC0 },
{ IQ2000_INSN_MFC3, IQ2000BF_INSN_MFC3, IQ2000BF_SFMT_CFC0 },
{ IQ2000_INSN_MTC0, IQ2000BF_INSN_MTC0, IQ2000BF_SFMT_CFC0 },
{ IQ2000_INSN_MTC1, IQ2000BF_INSN_MTC1, IQ2000BF_SFMT_CFC0 },
{ IQ2000_INSN_MTC2, IQ2000BF_INSN_MTC2, IQ2000BF_SFMT_CFC0 },
{ IQ2000_INSN_MTC3, IQ2000BF_INSN_MTC3, IQ2000BF_SFMT_CFC0 },
{ IQ2000_INSN_PKRL, IQ2000BF_INSN_PKRL, IQ2000BF_SFMT_CFC0 },
{ IQ2000_INSN_PKRLR1, IQ2000BF_INSN_PKRLR1, IQ2000BF_SFMT_CFC0 },
{ IQ2000_INSN_PKRLR30, IQ2000BF_INSN_PKRLR30, IQ2000BF_SFMT_CFC0 },
{ IQ2000_INSN_RB, IQ2000BF_INSN_RB, IQ2000BF_SFMT_CFC0 },
{ IQ2000_INSN_RBR1, IQ2000BF_INSN_RBR1, IQ2000BF_SFMT_CFC0 },
{ IQ2000_INSN_RBR30, IQ2000BF_INSN_RBR30, IQ2000BF_SFMT_CFC0 },
{ IQ2000_INSN_RFE, IQ2000BF_INSN_RFE, IQ2000BF_SFMT_CFC0 },
{ IQ2000_INSN_RX, IQ2000BF_INSN_RX, IQ2000BF_SFMT_CFC0 },
{ IQ2000_INSN_RXR1, IQ2000BF_INSN_RXR1, IQ2000BF_SFMT_CFC0 },
{ IQ2000_INSN_RXR30, IQ2000BF_INSN_RXR30, IQ2000BF_SFMT_CFC0 },
{ IQ2000_INSN_SLEEP, IQ2000BF_INSN_SLEEP, IQ2000BF_SFMT_CFC0 },
{ IQ2000_INSN_SRRD, IQ2000BF_INSN_SRRD, IQ2000BF_SFMT_CFC0 },
{ IQ2000_INSN_SRRDL, IQ2000BF_INSN_SRRDL, IQ2000BF_SFMT_CFC0 },
{ IQ2000_INSN_SRULCK, IQ2000BF_INSN_SRULCK, IQ2000BF_SFMT_CFC0 },
{ IQ2000_INSN_SRWR, IQ2000BF_INSN_SRWR, IQ2000BF_SFMT_CFC0 },
{ IQ2000_INSN_SRWRU, IQ2000BF_INSN_SRWRU, IQ2000BF_SFMT_CFC0 },
{ IQ2000_INSN_TRAPQFL, IQ2000BF_INSN_TRAPQFL, IQ2000BF_SFMT_CFC0 },
{ IQ2000_INSN_TRAPQNE, IQ2000BF_INSN_TRAPQNE, IQ2000BF_SFMT_CFC0 },
{ IQ2000_INSN_TRAPREL, IQ2000BF_INSN_TRAPREL, IQ2000BF_SFMT_CFC0 },
{ IQ2000_INSN_WB, IQ2000BF_INSN_WB, IQ2000BF_SFMT_CFC0 },
{ IQ2000_INSN_WBU, IQ2000BF_INSN_WBU, IQ2000BF_SFMT_CFC0 },
{ IQ2000_INSN_WBR1, IQ2000BF_INSN_WBR1, IQ2000BF_SFMT_CFC0 },
{ IQ2000_INSN_WBR1U, IQ2000BF_INSN_WBR1U, IQ2000BF_SFMT_CFC0 },
{ IQ2000_INSN_WBR30, IQ2000BF_INSN_WBR30, IQ2000BF_SFMT_CFC0 },
{ IQ2000_INSN_WBR30U, IQ2000BF_INSN_WBR30U, IQ2000BF_SFMT_CFC0 },
{ IQ2000_INSN_WX, IQ2000BF_INSN_WX, IQ2000BF_SFMT_CFC0 },
{ IQ2000_INSN_WXU, IQ2000BF_INSN_WXU, IQ2000BF_SFMT_CFC0 },
{ IQ2000_INSN_WXR1, IQ2000BF_INSN_WXR1, IQ2000BF_SFMT_CFC0 },
{ IQ2000_INSN_WXR1U, IQ2000BF_INSN_WXR1U, IQ2000BF_SFMT_CFC0 },
{ IQ2000_INSN_WXR30, IQ2000BF_INSN_WXR30, IQ2000BF_SFMT_CFC0 },
{ IQ2000_INSN_WXR30U, IQ2000BF_INSN_WXR30U, IQ2000BF_SFMT_CFC0 },
{ IQ2000_INSN_LDW, IQ2000BF_INSN_LDW, IQ2000BF_SFMT_LDW },
{ IQ2000_INSN_SDW, IQ2000BF_INSN_SDW, IQ2000BF_SFMT_SDW },
{ IQ2000_INSN_J, IQ2000BF_INSN_J, IQ2000BF_SFMT_J },
@ -320,7 +323,7 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc,
itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 12 :
if ((entire_insn & 0xfc00003f) == 0xc)
{ itype = IQ2000BF_INSN_SYSCALL; goto extract_sfmt_syscall; }
{ itype = IQ2000BF_INSN_SYSCALL; goto extract_sfmt_break; }
itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 13 :
if ((entire_insn & 0xffffffff) == 0xd)
@ -328,7 +331,7 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc,
itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 14 :
if ((entire_insn & 0xfc00003f) == 0xe)
{ itype = IQ2000BF_INSN_SLEEP; goto extract_sfmt_syscall; }
{ itype = IQ2000BF_INSN_SLEEP; goto extract_sfmt_cfc0; }
itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 16 :
if ((entire_insn & 0xfc0007ff) == 0x20)
@ -464,28 +467,28 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc,
case 4 : /* fall through */
case 6 :
if ((entire_insn & 0xffe007ff) == 0x40000000)
{ itype = IQ2000BF_INSN_MFC0; goto extract_sfmt_syscall; }
{ itype = IQ2000BF_INSN_MFC0; goto extract_sfmt_cfc0; }
itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 8 : /* fall through */
case 10 : /* fall through */
case 12 : /* fall through */
case 14 :
if ((entire_insn & 0xffe007ff) == 0x40400000)
{ itype = IQ2000BF_INSN_CFC0; goto extract_sfmt_syscall; }
{ itype = IQ2000BF_INSN_CFC0; goto extract_sfmt_cfc0; }
itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 16 : /* fall through */
case 18 : /* fall through */
case 20 : /* fall through */
case 22 :
if ((entire_insn & 0xffe007ff) == 0x40800000)
{ itype = IQ2000BF_INSN_MTC0; goto extract_sfmt_syscall; }
{ itype = IQ2000BF_INSN_MTC0; goto extract_sfmt_cfc0; }
itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 24 : /* fall through */
case 26 : /* fall through */
case 28 : /* fall through */
case 30 :
if ((entire_insn & 0xffe007ff) == 0x40c00000)
{ itype = IQ2000BF_INSN_CTC0; goto extract_sfmt_syscall; }
{ itype = IQ2000BF_INSN_CTC0; goto extract_sfmt_cfc0; }
itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 32 : /* fall through */
case 33 :
@ -509,7 +512,7 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc,
itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 65 :
if ((entire_insn & 0xffffffff) == 0x42000010)
{ itype = IQ2000BF_INSN_RFE; goto extract_sfmt_syscall; }
{ itype = IQ2000BF_INSN_RFE; goto extract_sfmt_cfc0; }
itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty;
default : itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty;
}
@ -521,19 +524,19 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc,
{
case 0 :
if ((entire_insn & 0xffe007ff) == 0x44000000)
{ itype = IQ2000BF_INSN_MFC1; goto extract_sfmt_syscall; }
{ itype = IQ2000BF_INSN_MFC1; goto extract_sfmt_cfc0; }
itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 1 :
if ((entire_insn & 0xffe007ff) == 0x44400000)
{ itype = IQ2000BF_INSN_CFC1; goto extract_sfmt_syscall; }
{ itype = IQ2000BF_INSN_CFC1; goto extract_sfmt_cfc0; }
itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 2 :
if ((entire_insn & 0xffe007ff) == 0x44800000)
{ itype = IQ2000BF_INSN_MTC1; goto extract_sfmt_syscall; }
{ itype = IQ2000BF_INSN_MTC1; goto extract_sfmt_cfc0; }
itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 3 :
if ((entire_insn & 0xffe007ff) == 0x44c00000)
{ itype = IQ2000BF_INSN_CTC1; goto extract_sfmt_syscall; }
{ itype = IQ2000BF_INSN_CTC1; goto extract_sfmt_cfc0; }
itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty;
default : itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty;
}
@ -550,86 +553,86 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc,
{
case 0 :
if ((entire_insn & 0xffe007ff) == 0x48000000)
{ itype = IQ2000BF_INSN_MFC2; goto extract_sfmt_syscall; }
{ itype = IQ2000BF_INSN_MFC2; goto extract_sfmt_cfc0; }
itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 1 :
if ((entire_insn & 0xffe007ff) == 0x48800000)
{ itype = IQ2000BF_INSN_MTC2; goto extract_sfmt_syscall; }
{ itype = IQ2000BF_INSN_MTC2; goto extract_sfmt_cfc0; }
itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty;
default : itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty;
}
}
case 32 :
if ((entire_insn & 0xffe0ffff) == 0x48200000)
{ itype = IQ2000BF_INSN_LUULCK; goto extract_sfmt_syscall; }
{ itype = IQ2000BF_INSN_LUULCK; goto extract_sfmt_cfc0; }
itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 33 :
if ((entire_insn & 0xffe007ff) == 0x48200001)
{ itype = IQ2000BF_INSN_LUR; goto extract_sfmt_syscall; }
{ itype = IQ2000BF_INSN_LUR; goto extract_sfmt_cfc0; }
itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 34 :
if ((entire_insn & 0xffe007ff) == 0x48200002)
{ itype = IQ2000BF_INSN_LUM32; goto extract_sfmt_syscall; }
{ itype = IQ2000BF_INSN_LUM32; goto extract_sfmt_cfc0; }
itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 35 :
if ((entire_insn & 0xffe007ff) == 0x48200003)
{ itype = IQ2000BF_INSN_LUC32; goto extract_sfmt_syscall; }
{ itype = IQ2000BF_INSN_LUC32; goto extract_sfmt_cfc0; }
itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 36 :
if ((entire_insn & 0xffe0ffff) == 0x48200004)
{ itype = IQ2000BF_INSN_LULCK; goto extract_sfmt_syscall; }
{ itype = IQ2000BF_INSN_LULCK; goto extract_sfmt_cfc0; }
itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 37 :
if ((entire_insn & 0xffe007ff) == 0x48200005)
{ itype = IQ2000BF_INSN_LURL; goto extract_sfmt_syscall; }
{ itype = IQ2000BF_INSN_LURL; goto extract_sfmt_cfc0; }
itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 38 :
if ((entire_insn & 0xffe007ff) == 0x48200006)
{ itype = IQ2000BF_INSN_LUM32L; goto extract_sfmt_syscall; }
{ itype = IQ2000BF_INSN_LUM32L; goto extract_sfmt_cfc0; }
itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 39 :
if ((entire_insn & 0xffe007ff) == 0x48200007)
{ itype = IQ2000BF_INSN_LUC32L; goto extract_sfmt_syscall; }
{ itype = IQ2000BF_INSN_LUC32L; goto extract_sfmt_cfc0; }
itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 40 :
if ((entire_insn & 0xffe007ff) == 0x48200008)
{ itype = IQ2000BF_INSN_LUK; goto extract_sfmt_syscall; }
{ itype = IQ2000BF_INSN_LUK; goto extract_sfmt_cfc0; }
itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 42 :
if ((entire_insn & 0xffe007ff) == 0x4820000a)
{ itype = IQ2000BF_INSN_LUM64; goto extract_sfmt_syscall; }
{ itype = IQ2000BF_INSN_LUM64; goto extract_sfmt_cfc0; }
itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 43 :
if ((entire_insn & 0xffe007ff) == 0x4820000b)
{ itype = IQ2000BF_INSN_LUC64; goto extract_sfmt_syscall; }
{ itype = IQ2000BF_INSN_LUC64; goto extract_sfmt_cfc0; }
itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 46 :
if ((entire_insn & 0xffe007ff) == 0x4820000e)
{ itype = IQ2000BF_INSN_LUM64L; goto extract_sfmt_syscall; }
{ itype = IQ2000BF_INSN_LUM64L; goto extract_sfmt_cfc0; }
itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 47 :
if ((entire_insn & 0xffe007ff) == 0x4820000f)
{ itype = IQ2000BF_INSN_LUC64L; goto extract_sfmt_syscall; }
{ itype = IQ2000BF_INSN_LUC64L; goto extract_sfmt_cfc0; }
itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 48 :
if ((entire_insn & 0xffe0ffff) == 0x48200010)
{ itype = IQ2000BF_INSN_SRRD; goto extract_sfmt_syscall; }
{ itype = IQ2000BF_INSN_SRRD; goto extract_sfmt_cfc0; }
itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 49 :
if ((entire_insn & 0xffe007ff) == 0x48200011)
{ itype = IQ2000BF_INSN_SRWR; goto extract_sfmt_syscall; }
{ itype = IQ2000BF_INSN_SRWR; goto extract_sfmt_cfc0; }
itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 52 :
if ((entire_insn & 0xffe0ffff) == 0x48200014)
{ itype = IQ2000BF_INSN_SRRDL; goto extract_sfmt_syscall; }
{ itype = IQ2000BF_INSN_SRRDL; goto extract_sfmt_cfc0; }
itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 53 :
if ((entire_insn & 0xffe007ff) == 0x48200015)
{ itype = IQ2000BF_INSN_SRWRU; goto extract_sfmt_syscall; }
{ itype = IQ2000BF_INSN_SRWRU; goto extract_sfmt_cfc0; }
itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 54 :
if ((entire_insn & 0xffe0ffff) == 0x48200016)
{ itype = IQ2000BF_INSN_SRULCK; goto extract_sfmt_syscall; }
{ itype = IQ2000BF_INSN_SRULCK; goto extract_sfmt_cfc0; }
itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 64 :
{
@ -638,11 +641,11 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc,
{
case 0 :
if ((entire_insn & 0xffe007ff) == 0x48400000)
{ itype = IQ2000BF_INSN_CFC2; goto extract_sfmt_syscall; }
{ itype = IQ2000BF_INSN_CFC2; goto extract_sfmt_cfc0; }
itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 1 :
if ((entire_insn & 0xffe007ff) == 0x48c00000)
{ itype = IQ2000BF_INSN_CTC2; goto extract_sfmt_syscall; }
{ itype = IQ2000BF_INSN_CTC2; goto extract_sfmt_cfc0; }
itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty;
default : itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty;
}
@ -657,7 +660,7 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc,
{
case 0 :
if ((entire_insn & 0xffe007ff) == 0x4c000000)
{ itype = IQ2000BF_INSN_MFC3; goto extract_sfmt_syscall; }
{ itype = IQ2000BF_INSN_MFC3; goto extract_sfmt_cfc0; }
itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 4 :
{
@ -666,15 +669,15 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc,
{
case 0 :
if ((entire_insn & 0xffe007ff) == 0x4c200000)
{ itype = IQ2000BF_INSN_WB; goto extract_sfmt_syscall; }
{ itype = IQ2000BF_INSN_WB; goto extract_sfmt_cfc0; }
itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 1 :
if ((entire_insn & 0xffe007ff) == 0x4c200004)
{ itype = IQ2000BF_INSN_RB; goto extract_sfmt_syscall; }
{ itype = IQ2000BF_INSN_RB; goto extract_sfmt_cfc0; }
itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 2 :
if ((entire_insn & 0xffffffff) == 0x4c200008)
{ itype = IQ2000BF_INSN_TRAPQFL; goto extract_sfmt_syscall; }
{ itype = IQ2000BF_INSN_TRAPQFL; goto extract_sfmt_cfc0; }
itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty;
default : itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty;
}
@ -686,11 +689,11 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc,
{
case 0 :
if ((entire_insn & 0xffe007ff) == 0x4c200001)
{ itype = IQ2000BF_INSN_WBU; goto extract_sfmt_syscall; }
{ itype = IQ2000BF_INSN_WBU; goto extract_sfmt_cfc0; }
itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 1 :
if ((entire_insn & 0xffffffff) == 0x4c200009)
{ itype = IQ2000BF_INSN_TRAPQNE; goto extract_sfmt_syscall; }
{ itype = IQ2000BF_INSN_TRAPQNE; goto extract_sfmt_cfc0; }
itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty;
default : itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty;
}
@ -702,15 +705,15 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc,
{
case 0 :
if ((entire_insn & 0xffe007ff) == 0x4c200002)
{ itype = IQ2000BF_INSN_WX; goto extract_sfmt_syscall; }
{ itype = IQ2000BF_INSN_WX; goto extract_sfmt_cfc0; }
itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 1 :
if ((entire_insn & 0xffe007ff) == 0x4c200006)
{ itype = IQ2000BF_INSN_RX; goto extract_sfmt_syscall; }
{ itype = IQ2000BF_INSN_RX; goto extract_sfmt_cfc0; }
itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 2 :
if ((entire_insn & 0xffe0ffff) == 0x4c20000a)
{ itype = IQ2000BF_INSN_TRAPREL; goto extract_sfmt_syscall; }
{ itype = IQ2000BF_INSN_TRAPREL; goto extract_sfmt_cfc0; }
itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty;
default : itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty;
}
@ -722,26 +725,26 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc,
{
case 0 :
if ((entire_insn & 0xffe007ff) == 0x4c200003)
{ itype = IQ2000BF_INSN_WXU; goto extract_sfmt_syscall; }
{ itype = IQ2000BF_INSN_WXU; goto extract_sfmt_cfc0; }
itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 1 :
if ((entire_insn & 0xffe007ff) == 0x4c200007)
{ itype = IQ2000BF_INSN_PKRL; goto extract_sfmt_syscall; }
{ itype = IQ2000BF_INSN_PKRL; goto extract_sfmt_cfc0; }
itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty;
default : itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty;
}
}
case 8 :
if ((entire_insn & 0xffe007ff) == 0x4c400000)
{ itype = IQ2000BF_INSN_CFC3; goto extract_sfmt_syscall; }
{ itype = IQ2000BF_INSN_CFC3; goto extract_sfmt_cfc0; }
itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 16 :
if ((entire_insn & 0xffe007ff) == 0x4c800000)
{ itype = IQ2000BF_INSN_MTC3; goto extract_sfmt_syscall; }
{ itype = IQ2000BF_INSN_MTC3; goto extract_sfmt_cfc0; }
itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 24 :
if ((entire_insn & 0xffe007ff) == 0x4cc00000)
{ itype = IQ2000BF_INSN_CTC3; goto extract_sfmt_syscall; }
{ itype = IQ2000BF_INSN_CTC3; goto extract_sfmt_cfc0; }
itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 32 : /* fall through */
case 33 : /* fall through */
@ -772,64 +775,64 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc,
}
case 36 :
if ((entire_insn & 0xffe007ff) == 0x4d200000)
{ itype = IQ2000BF_INSN_CHKHDR; goto extract_sfmt_syscall; }
{ itype = IQ2000BF_INSN_CHKHDR; goto extract_sfmt_cfc0; }
itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 64 : /* fall through */
case 65 : /* fall through */
case 66 : /* fall through */
case 67 : itype = IQ2000BF_INSN_WBR1; goto extract_sfmt_syscall;
case 67 : itype = IQ2000BF_INSN_WBR1; goto extract_sfmt_cfc0;
case 68 : /* fall through */
case 69 : /* fall through */
case 70 : /* fall through */
case 71 : itype = IQ2000BF_INSN_WBR1U; goto extract_sfmt_syscall;
case 71 : itype = IQ2000BF_INSN_WBR1U; goto extract_sfmt_cfc0;
case 72 : /* fall through */
case 73 : /* fall through */
case 74 : /* fall through */
case 75 : itype = IQ2000BF_INSN_WBR30; goto extract_sfmt_syscall;
case 75 : itype = IQ2000BF_INSN_WBR30; goto extract_sfmt_cfc0;
case 76 : /* fall through */
case 77 : /* fall through */
case 78 : /* fall through */
case 79 : itype = IQ2000BF_INSN_WBR30U; goto extract_sfmt_syscall;
case 79 : itype = IQ2000BF_INSN_WBR30U; goto extract_sfmt_cfc0;
case 80 : /* fall through */
case 81 : /* fall through */
case 82 : /* fall through */
case 83 : itype = IQ2000BF_INSN_WXR1; goto extract_sfmt_syscall;
case 83 : itype = IQ2000BF_INSN_WXR1; goto extract_sfmt_cfc0;
case 84 : /* fall through */
case 85 : /* fall through */
case 86 : /* fall through */
case 87 : itype = IQ2000BF_INSN_WXR1U; goto extract_sfmt_syscall;
case 87 : itype = IQ2000BF_INSN_WXR1U; goto extract_sfmt_cfc0;
case 88 : /* fall through */
case 89 : /* fall through */
case 90 : /* fall through */
case 91 : itype = IQ2000BF_INSN_WXR30; goto extract_sfmt_syscall;
case 91 : itype = IQ2000BF_INSN_WXR30; goto extract_sfmt_cfc0;
case 92 : /* fall through */
case 93 : /* fall through */
case 94 : /* fall through */
case 95 : itype = IQ2000BF_INSN_WXR30U; goto extract_sfmt_syscall;
case 95 : itype = IQ2000BF_INSN_WXR30U; goto extract_sfmt_cfc0;
case 96 : /* fall through */
case 97 : /* fall through */
case 98 : /* fall through */
case 99 : itype = IQ2000BF_INSN_RBR1; goto extract_sfmt_syscall;
case 99 : itype = IQ2000BF_INSN_RBR1; goto extract_sfmt_cfc0;
case 104 : /* fall through */
case 105 : /* fall through */
case 106 : /* fall through */
case 107 : itype = IQ2000BF_INSN_RBR30; goto extract_sfmt_syscall;
case 107 : itype = IQ2000BF_INSN_RBR30; goto extract_sfmt_cfc0;
case 112 : /* fall through */
case 113 : /* fall through */
case 114 : /* fall through */
case 115 : itype = IQ2000BF_INSN_RXR1; goto extract_sfmt_syscall;
case 115 : itype = IQ2000BF_INSN_RXR1; goto extract_sfmt_cfc0;
case 116 : /* fall through */
case 117 : /* fall through */
case 118 : /* fall through */
case 119 : itype = IQ2000BF_INSN_PKRLR1; goto extract_sfmt_syscall;
case 119 : itype = IQ2000BF_INSN_PKRLR1; goto extract_sfmt_cfc0;
case 120 : /* fall through */
case 121 : /* fall through */
case 122 : /* fall through */
case 123 : itype = IQ2000BF_INSN_RXR30; goto extract_sfmt_syscall;
case 123 : itype = IQ2000BF_INSN_RXR30; goto extract_sfmt_cfc0;
case 124 : /* fall through */
case 125 : /* fall through */
case 126 : /* fall through */
case 127 : itype = IQ2000BF_INSN_PKRLR30; goto extract_sfmt_syscall;
case 127 : itype = IQ2000BF_INSN_PKRLR30; goto extract_sfmt_cfc0;
default : itype = IQ2000BF_INSN_X_INVALID; goto extract_sfmt_empty;
}
}
@ -1070,7 +1073,7 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc,
f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5);
f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5);
f_offset = ((((EXTRACT_LSB0_SINT (insn, 32, 15, 16)) << (2))) + (((pc) + (4))));
f_offset = ((((EXTRACT_LSB0_SINT (insn, 32, 15, 16)) * (4))) + (((pc) + (4))));
/* Record the fields for the semantic handler. */
FLD (f_rt) = f_rt;
@ -1099,7 +1102,7 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc,
f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5);
f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5);
f_offset = ((((EXTRACT_LSB0_SINT (insn, 32, 15, 16)) << (2))) + (((pc) + (4))));
f_offset = ((((EXTRACT_LSB0_SINT (insn, 32, 15, 16)) * (4))) + (((pc) + (4))));
/* Record the fields for the semantic handler. */
FLD (f_rs) = f_rs;
@ -1126,7 +1129,7 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc,
SI f_offset;
f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5);
f_offset = ((((EXTRACT_LSB0_SINT (insn, 32, 15, 16)) << (2))) + (((pc) + (4))));
f_offset = ((((EXTRACT_LSB0_SINT (insn, 32, 15, 16)) * (4))) + (((pc) + (4))));
/* Record the fields for the semantic handler. */
FLD (f_rs) = f_rs;
@ -1152,7 +1155,7 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc,
SI f_offset;
f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5);
f_offset = ((((EXTRACT_LSB0_SINT (insn, 32, 15, 16)) << (2))) + (((pc) + (4))));
f_offset = ((((EXTRACT_LSB0_SINT (insn, 32, 15, 16)) * (4))) + (((pc) + (4))));
/* Record the fields for the semantic handler. */
FLD (f_rs) = f_rs;
@ -1391,19 +1394,6 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc,
{
}
#endif
#undef FLD
return idesc;
}
extract_sfmt_syscall:
{
const IDESC *idesc = &iq2000bf_insn_data[itype];
#define FLD(f) abuf->fields.sfmt_empty.f
/* Record the fields for the semantic handler. */
CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_syscall", (char *) 0));
#undef FLD
return idesc;
}
@ -1466,6 +1456,19 @@ iq2000bf_decode (SIM_CPU *current_cpu, IADDR pc,
/* Record the fields for the semantic handler. */
CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bctxt", (char *) 0));
#undef FLD
return idesc;
}
extract_sfmt_cfc0:
{
const IDESC *idesc = &iq2000bf_insn_data[itype];
#define FLD(f) abuf->fields.sfmt_empty.f
/* Record the fields for the semantic handler. */
CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cfc0", (char *) 0));
#undef FLD
return idesc;
}

9
sim/iq2000/decode.h
View File

@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright 1996-2023 Free Software Foundation, Inc.
Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, see <http://www.gnu.org/licenses/>.
with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
@ -80,8 +81,8 @@ typedef enum iq2000bf_sfmt_type {
, IQ2000BF_SFMT_BBI, IQ2000BF_SFMT_BBV, IQ2000BF_SFMT_BGEZ, IQ2000BF_SFMT_BGEZAL
, IQ2000BF_SFMT_JALR, IQ2000BF_SFMT_JR, IQ2000BF_SFMT_LB, IQ2000BF_SFMT_LH
, IQ2000BF_SFMT_LUI, IQ2000BF_SFMT_LW, IQ2000BF_SFMT_SB, IQ2000BF_SFMT_SH
, IQ2000BF_SFMT_SW, IQ2000BF_SFMT_BREAK, IQ2000BF_SFMT_SYSCALL, IQ2000BF_SFMT_ANDOUI
, IQ2000BF_SFMT_MRGB, IQ2000BF_SFMT_BCTXT, IQ2000BF_SFMT_LDW, IQ2000BF_SFMT_SDW
, IQ2000BF_SFMT_SW, IQ2000BF_SFMT_BREAK, IQ2000BF_SFMT_ANDOUI, IQ2000BF_SFMT_MRGB
, IQ2000BF_SFMT_BCTXT, IQ2000BF_SFMT_CFC0, IQ2000BF_SFMT_LDW, IQ2000BF_SFMT_SDW
, IQ2000BF_SFMT_J, IQ2000BF_SFMT_JAL
} IQ2000BF_SFMT_TYPE;

5
sim/iq2000/model.c
View File

@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright 1996-2023 Free Software Foundation, Inc.
Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, see <http://www.gnu.org/licenses/>.
with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/

9
sim/iq2000/sem-switch.c
View File

@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright 1996-2023 Free Software Foundation, Inc.
Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, see <http://www.gnu.org/licenses/>.
with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
@ -1809,10 +1810,10 @@ do_break (current_cpu, pc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
#define FLD(f) abuf->fields.sfmt_empty.f
int UNUSED written = 0;
IADDR pc = abuf->addr;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
do_syscall (current_cpu, pc);
do_syscall (current_cpu, pc);
#undef FLD
}

9
sim/iq2000/sem.c
View File

@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright 1996-2023 Free Software Foundation, Inc.
Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, see <http://www.gnu.org/licenses/>.
with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
@ -1747,10 +1748,10 @@ SEM_FN_NAME (iq2000bf,syscall) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
#define FLD(f) abuf->fields.sfmt_empty.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int UNUSED written = 0;
IADDR pc = abuf->addr;
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
do_syscall (current_cpu, pc);
do_syscall (current_cpu, pc);
return vpc;
#undef FLD

5
sim/lm32/arch.c
View File

@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright 1996-2023 Free Software Foundation, Inc.
Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, see <http://www.gnu.org/licenses/>.
with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/

13
sim/lm32/arch.h
View File

@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright 1996-2023 Free Software Foundation, Inc.
Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@ -17,13 +17,22 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, see <http://www.gnu.org/licenses/>.
with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
#ifndef LM32_ARCH_H
#define LM32_ARCH_H
#define TARGET_BIG_ENDIAN 1
#define WI SI
#define UWI USI
#define AI USI
#define IAI USI
/* Enum declaration for model types. */
typedef enum model_type {
MODEL_LM32, MODEL_MAX

5
sim/lm32/cpu.c
View File

@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright 1996-2023 Free Software Foundation, Inc.
Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, see <http://www.gnu.org/licenses/>.
with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/

9
sim/lm32/cpu.h
View File

@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright 1996-2023 Free Software Foundation, Inc.
Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, see <http://www.gnu.org/licenses/>.
with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
@ -247,7 +248,7 @@ struct scache {
#define EXTRACT_IFMT_BI_CODE \
length = 4; \
f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
f_call = ((pc) + (((SI) (((EXTRACT_LSB0_SINT (insn, 32, 25, 26)) << (6))) >> (4)))); \
f_call = ((pc) + (((((((((EXTRACT_LSB0_SINT (insn, 32, 25, 26)) & (67108863))) << (2))) ^ (134217728))) - (134217728)))); \
#define EXTRACT_IFMT_BE_VARS \
UINT f_opcode; \
@ -260,7 +261,7 @@ struct scache {
f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
f_r0 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
f_r1 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
f_branch = ((pc) + (((SI) (((EXTRACT_LSB0_SINT (insn, 32, 15, 16)) << (16))) >> (14)))); \
f_branch = ((pc) + (((((((((EXTRACT_LSB0_SINT (insn, 32, 15, 16)) & (65535))) << (2))) ^ (131072))) - (131072)))); \
#define EXTRACT_IFMT_ORI_VARS \
UINT f_opcode; \

5
sim/lm32/cpuall.h
View File

@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright 1996-2023 Free Software Foundation, Inc.
Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, see <http://www.gnu.org/licenses/>.
with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/

13
sim/lm32/decode.c
View File

@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright 1996-2023 Free Software Foundation, Inc.
Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, see <http://www.gnu.org/licenses/>.
with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
@ -26,6 +27,8 @@ This file is part of the GNU simulators.
#include "sim-main.h"
#include "sim-assert.h"
#include "cgen-mem.h"
#include "cgen-ops.h"
/* The instruction descriptor array.
This is computed at runtime. Space for it is not malloc'd to save a
@ -474,7 +477,7 @@ lm32bf_decode (SIM_CPU *current_cpu, IADDR pc,
#define FLD(f) abuf->fields.sfmt_bi.f
SI f_call;
f_call = ((pc) + (((SI) (((EXTRACT_LSB0_SINT (insn, 32, 25, 26)) << (6))) >> (4))));
f_call = ((pc) + (((((((((EXTRACT_LSB0_SINT (insn, 32, 25, 26)) & (67108863))) << (2))) ^ (134217728))) - (134217728))));
/* Record the fields for the semantic handler. */
FLD (i_call) = f_call;
@ -495,7 +498,7 @@ lm32bf_decode (SIM_CPU *current_cpu, IADDR pc,
f_r0 = EXTRACT_LSB0_UINT (insn, 32, 25, 5);
f_r1 = EXTRACT_LSB0_UINT (insn, 32, 20, 5);
f_branch = ((pc) + (((SI) (((EXTRACT_LSB0_SINT (insn, 32, 15, 16)) << (16))) >> (14))));
f_branch = ((pc) + (((((((((EXTRACT_LSB0_SINT (insn, 32, 15, 16)) & (65535))) << (2))) ^ (131072))) - (131072))));
/* Record the fields for the semantic handler. */
FLD (f_r0) = f_r0;
@ -531,7 +534,7 @@ lm32bf_decode (SIM_CPU *current_cpu, IADDR pc,
#define FLD(f) abuf->fields.sfmt_bi.f
SI f_call;
f_call = ((pc) + (((SI) (((EXTRACT_LSB0_SINT (insn, 32, 25, 26)) << (6))) >> (4))));
f_call = ((pc) + (((((((((EXTRACT_LSB0_SINT (insn, 32, 25, 26)) & (67108863))) << (2))) ^ (134217728))) - (134217728))));
/* Record the fields for the semantic handler. */
FLD (i_call) = f_call;

5
sim/lm32/decode.h
View File

@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright 1996-2023 Free Software Foundation, Inc.
Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, see <http://www.gnu.org/licenses/>.
with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/

5
sim/lm32/model.c
View File

@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright 1996-2023 Free Software Foundation, Inc.
Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, see <http://www.gnu.org/licenses/>.
with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/

5
sim/lm32/sem-switch.c
View File

@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright 1996-2023 Free Software Foundation, Inc.
Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, see <http://www.gnu.org/licenses/>.
with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/

5
sim/lm32/sem.c
View File

@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright 1996-2023 Free Software Foundation, Inc.
Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, see <http://www.gnu.org/licenses/>.
with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/

5
sim/m32r/arch.c
View File

@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright 1996-2023 Free Software Foundation, Inc.
Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, see <http://www.gnu.org/licenses/>.
with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/

13
sim/m32r/arch.h
View File

@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright 1996-2023 Free Software Foundation, Inc.
Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@ -17,13 +17,22 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, see <http://www.gnu.org/licenses/>.
with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
#ifndef M32R_ARCH_H
#define M32R_ARCH_H
#define TARGET_BIG_ENDIAN 1
#define WI SI
#define UWI USI
#define AI USI
#define IAI USI
/* Enum declaration for model types. */
typedef enum model_type {
MODEL_M32R_D, MODEL_TEST, MODEL_M32RX, MODEL_M32R2

5
sim/m32r/cpu.c
View File

@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright 1996-2023 Free Software Foundation, Inc.
Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, see <http://www.gnu.org/licenses/>.
with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/

13
sim/m32r/cpu.h
View File

@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright 1996-2023 Free Software Foundation, Inc.
Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, see <http://www.gnu.org/licenses/>.
with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
@ -397,7 +398,7 @@ struct scache {
length = 2; \
f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
f_disp8 = ((((EXTRACT_MSB0_SINT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
f_disp8 = ((((EXTRACT_MSB0_SINT (insn, 16, 8, 8)) * (4))) + (((pc) & (-4)))); \
#define EXTRACT_IFMT_BC24_VARS \
UINT f_op1; \
@ -408,7 +409,7 @@ struct scache {
length = 4; \
f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
f_disp24 = ((((EXTRACT_MSB0_SINT (insn, 32, 8, 24)) << (2))) + (pc)); \
f_disp24 = ((((EXTRACT_MSB0_SINT (insn, 32, 8, 24)) * (4))) + (pc)); \
#define EXTRACT_IFMT_BEQ_VARS \
UINT f_op1; \
@ -423,7 +424,7 @@ struct scache {
f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
f_disp16 = ((((EXTRACT_MSB0_SINT (insn, 32, 16, 16)) << (2))) + (pc)); \
f_disp16 = ((((EXTRACT_MSB0_SINT (insn, 32, 16, 16)) * (4))) + (pc)); \
#define EXTRACT_IFMT_BEQZ_VARS \
UINT f_op1; \
@ -438,7 +439,7 @@ struct scache {
f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
f_disp16 = ((((EXTRACT_MSB0_SINT (insn, 32, 16, 16)) << (2))) + (pc)); \
f_disp16 = ((((EXTRACT_MSB0_SINT (insn, 32, 16, 16)) * (4))) + (pc)); \
#define EXTRACT_IFMT_CMP_VARS \
UINT f_op1; \

5
sim/m32r/cpu2.c
View File

@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright 1996-2023 Free Software Foundation, Inc.
Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, see <http://www.gnu.org/licenses/>.
with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/

13
sim/m32r/cpu2.h
View File

@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright 1996-2023 Free Software Foundation, Inc.
Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, see <http://www.gnu.org/licenses/>.
with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
@ -428,7 +429,7 @@ struct scache {
length = 2; \
f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
f_disp8 = ((((EXTRACT_MSB0_SINT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
f_disp8 = ((((EXTRACT_MSB0_SINT (insn, 16, 8, 8)) * (4))) + (((pc) & (-4)))); \
#define EXTRACT_IFMT_BC24_VARS \
UINT f_op1; \
@ -439,7 +440,7 @@ struct scache {
length = 4; \
f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
f_disp24 = ((((EXTRACT_MSB0_SINT (insn, 32, 8, 24)) << (2))) + (pc)); \
f_disp24 = ((((EXTRACT_MSB0_SINT (insn, 32, 8, 24)) * (4))) + (pc)); \
#define EXTRACT_IFMT_BEQ_VARS \
UINT f_op1; \
@ -454,7 +455,7 @@ struct scache {
f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
f_disp16 = ((((EXTRACT_MSB0_SINT (insn, 32, 16, 16)) << (2))) + (pc)); \
f_disp16 = ((((EXTRACT_MSB0_SINT (insn, 32, 16, 16)) * (4))) + (pc)); \
#define EXTRACT_IFMT_BEQZ_VARS \
UINT f_op1; \
@ -469,7 +470,7 @@ struct scache {
f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
f_disp16 = ((((EXTRACT_MSB0_SINT (insn, 32, 16, 16)) << (2))) + (pc)); \
f_disp16 = ((((EXTRACT_MSB0_SINT (insn, 32, 16, 16)) * (4))) + (pc)); \
#define EXTRACT_IFMT_CMP_VARS \
UINT f_op1; \

5
sim/m32r/cpuall.h
View File

@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright 1996-2023 Free Software Foundation, Inc.
Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, see <http://www.gnu.org/licenses/>.
with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/

5
sim/m32r/cpux.c
View File

@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright 1996-2023 Free Software Foundation, Inc.
Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, see <http://www.gnu.org/licenses/>.
with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/

13
sim/m32r/cpux.h
View File

@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright 1996-2023 Free Software Foundation, Inc.
Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, see <http://www.gnu.org/licenses/>.
with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
@ -428,7 +429,7 @@ struct scache {
length = 2; \
f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
f_disp8 = ((((EXTRACT_MSB0_SINT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
f_disp8 = ((((EXTRACT_MSB0_SINT (insn, 16, 8, 8)) * (4))) + (((pc) & (-4)))); \
#define EXTRACT_IFMT_BC24_VARS \
UINT f_op1; \
@ -439,7 +440,7 @@ struct scache {
length = 4; \
f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
f_disp24 = ((((EXTRACT_MSB0_SINT (insn, 32, 8, 24)) << (2))) + (pc)); \
f_disp24 = ((((EXTRACT_MSB0_SINT (insn, 32, 8, 24)) * (4))) + (pc)); \
#define EXTRACT_IFMT_BEQ_VARS \
UINT f_op1; \
@ -454,7 +455,7 @@ struct scache {
f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
f_disp16 = ((((EXTRACT_MSB0_SINT (insn, 32, 16, 16)) << (2))) + (pc)); \
f_disp16 = ((((EXTRACT_MSB0_SINT (insn, 32, 16, 16)) * (4))) + (pc)); \
#define EXTRACT_IFMT_BEQZ_VARS \
UINT f_op1; \
@ -469,7 +470,7 @@ struct scache {
f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
f_disp16 = ((((EXTRACT_MSB0_SINT (insn, 32, 16, 16)) << (2))) + (pc)); \
f_disp16 = ((((EXTRACT_MSB0_SINT (insn, 32, 16, 16)) * (4))) + (pc)); \
#define EXTRACT_IFMT_CMP_VARS \
UINT f_op1; \

23
sim/m32r/decode.c
View File

@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright 1996-2023 Free Software Foundation, Inc.
Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, see <http://www.gnu.org/licenses/>.
with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
@ -26,6 +27,8 @@ This file is part of the GNU simulators.
#include "sim-main.h"
#include "sim-assert.h"
#include "cgen-mem.h"
#include "cgen-ops.h"
/* The instruction descriptor array.
This is computed at runtime. Space for it is not malloc'd to save a
@ -844,7 +847,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
#define FLD(f) abuf->fields.sfmt_bl8.f
SI f_disp8;
f_disp8 = ((((EXTRACT_MSB0_SINT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4))));
f_disp8 = ((((EXTRACT_MSB0_SINT (insn, 16, 8, 8)) * (4))) + (((pc) & (-4))));
/* Record the fields for the semantic handler. */
FLD (i_disp8) = f_disp8;
@ -867,7 +870,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
#define FLD(f) abuf->fields.sfmt_bl24.f
SI f_disp24;
f_disp24 = ((((EXTRACT_MSB0_SINT (insn, 32, 8, 24)) << (2))) + (pc));
f_disp24 = ((((EXTRACT_MSB0_SINT (insn, 32, 8, 24)) * (4))) + (pc));
/* Record the fields for the semantic handler. */
FLD (i_disp24) = f_disp24;
@ -894,7 +897,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
f_disp16 = ((((EXTRACT_MSB0_SINT (insn, 32, 16, 16)) << (2))) + (pc));
f_disp16 = ((((EXTRACT_MSB0_SINT (insn, 32, 16, 16)) * (4))) + (pc));
/* Record the fields for the semantic handler. */
FLD (f_r1) = f_r1;
@ -925,7 +928,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
SI f_disp16;
f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
f_disp16 = ((((EXTRACT_MSB0_SINT (insn, 32, 16, 16)) << (2))) + (pc));
f_disp16 = ((((EXTRACT_MSB0_SINT (insn, 32, 16, 16)) * (4))) + (pc));
/* Record the fields for the semantic handler. */
FLD (f_r2) = f_r2;
@ -951,7 +954,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
#define FLD(f) abuf->fields.sfmt_bl8.f
SI f_disp8;
f_disp8 = ((((EXTRACT_MSB0_SINT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4))));
f_disp8 = ((((EXTRACT_MSB0_SINT (insn, 16, 8, 8)) * (4))) + (((pc) & (-4))));
/* Record the fields for the semantic handler. */
FLD (i_disp8) = f_disp8;
@ -975,7 +978,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
#define FLD(f) abuf->fields.sfmt_bl24.f
SI f_disp24;
f_disp24 = ((((EXTRACT_MSB0_SINT (insn, 32, 8, 24)) << (2))) + (pc));
f_disp24 = ((((EXTRACT_MSB0_SINT (insn, 32, 8, 24)) * (4))) + (pc));
/* Record the fields for the semantic handler. */
FLD (i_disp24) = f_disp24;
@ -999,7 +1002,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
#define FLD(f) abuf->fields.sfmt_bl8.f
SI f_disp8;
f_disp8 = ((((EXTRACT_MSB0_SINT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4))));
f_disp8 = ((((EXTRACT_MSB0_SINT (insn, 16, 8, 8)) * (4))) + (((pc) & (-4))));
/* Record the fields for the semantic handler. */
FLD (i_disp8) = f_disp8;
@ -1022,7 +1025,7 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
#define FLD(f) abuf->fields.sfmt_bl24.f
SI f_disp24;
f_disp24 = ((((EXTRACT_MSB0_SINT (insn, 32, 8, 24)) << (2))) + (pc));
f_disp24 = ((((EXTRACT_MSB0_SINT (insn, 32, 8, 24)) * (4))) + (pc));
/* Record the fields for the semantic handler. */
FLD (i_disp24) = f_disp24;

5
sim/m32r/decode.h
View File

@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright 1996-2023 Free Software Foundation, Inc.
Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, see <http://www.gnu.org/licenses/>.
with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/

27
sim/m32r/decode2.c
View File

@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright 1996-2023 Free Software Foundation, Inc.
Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, see <http://www.gnu.org/licenses/>.
with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
@ -26,6 +27,8 @@ This file is part of the GNU simulators.
#include "sim-main.h"
#include "sim-assert.h"
#include "cgen-mem.h"
#include "cgen-ops.h"
/* Insn can't be executed in parallel.
Or is that "do NOt Pass to Air defense Radar"? :-) */
@ -1033,7 +1036,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc,
#define FLD(f) abuf->fields.sfmt_bl8.f
SI f_disp8;
f_disp8 = ((((EXTRACT_MSB0_SINT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4))));
f_disp8 = ((((EXTRACT_MSB0_SINT (insn, 16, 8, 8)) * (4))) + (((pc) & (-4))));
/* Record the fields for the semantic handler. */
FLD (i_disp8) = f_disp8;
@ -1056,7 +1059,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc,
#define FLD(f) abuf->fields.sfmt_bl24.f
SI f_disp24;
f_disp24 = ((((EXTRACT_MSB0_SINT (insn, 32, 8, 24)) << (2))) + (pc));
f_disp24 = ((((EXTRACT_MSB0_SINT (insn, 32, 8, 24)) * (4))) + (pc));
/* Record the fields for the semantic handler. */
FLD (i_disp24) = f_disp24;
@ -1083,7 +1086,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc,
f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
f_disp16 = ((((EXTRACT_MSB0_SINT (insn, 32, 16, 16)) << (2))) + (pc));
f_disp16 = ((((EXTRACT_MSB0_SINT (insn, 32, 16, 16)) * (4))) + (pc));
/* Record the fields for the semantic handler. */
FLD (f_r1) = f_r1;
@ -1114,7 +1117,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc,
SI f_disp16;
f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
f_disp16 = ((((EXTRACT_MSB0_SINT (insn, 32, 16, 16)) << (2))) + (pc));
f_disp16 = ((((EXTRACT_MSB0_SINT (insn, 32, 16, 16)) * (4))) + (pc));
/* Record the fields for the semantic handler. */
FLD (f_r2) = f_r2;
@ -1140,7 +1143,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc,
#define FLD(f) abuf->fields.sfmt_bl8.f
SI f_disp8;
f_disp8 = ((((EXTRACT_MSB0_SINT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4))));
f_disp8 = ((((EXTRACT_MSB0_SINT (insn, 16, 8, 8)) * (4))) + (((pc) & (-4))));
/* Record the fields for the semantic handler. */
FLD (i_disp8) = f_disp8;
@ -1164,7 +1167,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc,
#define FLD(f) abuf->fields.sfmt_bl24.f
SI f_disp24;
f_disp24 = ((((EXTRACT_MSB0_SINT (insn, 32, 8, 24)) << (2))) + (pc));
f_disp24 = ((((EXTRACT_MSB0_SINT (insn, 32, 8, 24)) * (4))) + (pc));
/* Record the fields for the semantic handler. */
FLD (i_disp24) = f_disp24;
@ -1188,7 +1191,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc,
#define FLD(f) abuf->fields.sfmt_bl8.f
SI f_disp8;
f_disp8 = ((((EXTRACT_MSB0_SINT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4))));
f_disp8 = ((((EXTRACT_MSB0_SINT (insn, 16, 8, 8)) * (4))) + (((pc) & (-4))));
/* Record the fields for the semantic handler. */
FLD (i_disp8) = f_disp8;
@ -1212,7 +1215,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc,
#define FLD(f) abuf->fields.sfmt_bl24.f
SI f_disp24;
f_disp24 = ((((EXTRACT_MSB0_SINT (insn, 32, 8, 24)) << (2))) + (pc));
f_disp24 = ((((EXTRACT_MSB0_SINT (insn, 32, 8, 24)) * (4))) + (pc));
/* Record the fields for the semantic handler. */
FLD (i_disp24) = f_disp24;
@ -1236,7 +1239,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc,
#define FLD(f) abuf->fields.sfmt_bl8.f
SI f_disp8;
f_disp8 = ((((EXTRACT_MSB0_SINT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4))));
f_disp8 = ((((EXTRACT_MSB0_SINT (insn, 16, 8, 8)) * (4))) + (((pc) & (-4))));
/* Record the fields for the semantic handler. */
FLD (i_disp8) = f_disp8;
@ -1259,7 +1262,7 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc,
#define FLD(f) abuf->fields.sfmt_bl24.f
SI f_disp24;
f_disp24 = ((((EXTRACT_MSB0_SINT (insn, 32, 8, 24)) << (2))) + (pc));
f_disp24 = ((((EXTRACT_MSB0_SINT (insn, 32, 8, 24)) * (4))) + (pc));
/* Record the fields for the semantic handler. */
FLD (i_disp24) = f_disp24;

5
sim/m32r/decode2.h
View File

@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright 1996-2023 Free Software Foundation, Inc.
Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, see <http://www.gnu.org/licenses/>.
with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/

27
sim/m32r/decodex.c
View File

@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright 1996-2023 Free Software Foundation, Inc.
Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, see <http://www.gnu.org/licenses/>.
with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
@ -26,6 +27,8 @@ This file is part of the GNU simulators.
#include "sim-main.h"
#include "sim-assert.h"
#include "cgen-mem.h"
#include "cgen-ops.h"
/* Insn can't be executed in parallel.
Or is that "do NOt Pass to Air defense Radar"? :-) */
@ -974,7 +977,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
#define FLD(f) abuf->fields.sfmt_bl8.f
SI f_disp8;
f_disp8 = ((((EXTRACT_MSB0_SINT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4))));
f_disp8 = ((((EXTRACT_MSB0_SINT (insn, 16, 8, 8)) * (4))) + (((pc) & (-4))));
/* Record the fields for the semantic handler. */
FLD (i_disp8) = f_disp8;
@ -997,7 +1000,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
#define FLD(f) abuf->fields.sfmt_bl24.f
SI f_disp24;
f_disp24 = ((((EXTRACT_MSB0_SINT (insn, 32, 8, 24)) << (2))) + (pc));
f_disp24 = ((((EXTRACT_MSB0_SINT (insn, 32, 8, 24)) * (4))) + (pc));
/* Record the fields for the semantic handler. */
FLD (i_disp24) = f_disp24;
@ -1024,7 +1027,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
f_disp16 = ((((EXTRACT_MSB0_SINT (insn, 32, 16, 16)) << (2))) + (pc));
f_disp16 = ((((EXTRACT_MSB0_SINT (insn, 32, 16, 16)) * (4))) + (pc));
/* Record the fields for the semantic handler. */
FLD (f_r1) = f_r1;
@ -1055,7 +1058,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
SI f_disp16;
f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
f_disp16 = ((((EXTRACT_MSB0_SINT (insn, 32, 16, 16)) << (2))) + (pc));
f_disp16 = ((((EXTRACT_MSB0_SINT (insn, 32, 16, 16)) * (4))) + (pc));
/* Record the fields for the semantic handler. */
FLD (f_r2) = f_r2;
@ -1081,7 +1084,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
#define FLD(f) abuf->fields.sfmt_bl8.f
SI f_disp8;
f_disp8 = ((((EXTRACT_MSB0_SINT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4))));
f_disp8 = ((((EXTRACT_MSB0_SINT (insn, 16, 8, 8)) * (4))) + (((pc) & (-4))));
/* Record the fields for the semantic handler. */
FLD (i_disp8) = f_disp8;
@ -1105,7 +1108,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
#define FLD(f) abuf->fields.sfmt_bl24.f
SI f_disp24;
f_disp24 = ((((EXTRACT_MSB0_SINT (insn, 32, 8, 24)) << (2))) + (pc));
f_disp24 = ((((EXTRACT_MSB0_SINT (insn, 32, 8, 24)) * (4))) + (pc));
/* Record the fields for the semantic handler. */
FLD (i_disp24) = f_disp24;
@ -1129,7 +1132,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
#define FLD(f) abuf->fields.sfmt_bl8.f
SI f_disp8;
f_disp8 = ((((EXTRACT_MSB0_SINT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4))));
f_disp8 = ((((EXTRACT_MSB0_SINT (insn, 16, 8, 8)) * (4))) + (((pc) & (-4))));
/* Record the fields for the semantic handler. */
FLD (i_disp8) = f_disp8;
@ -1153,7 +1156,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
#define FLD(f) abuf->fields.sfmt_bl24.f
SI f_disp24;
f_disp24 = ((((EXTRACT_MSB0_SINT (insn, 32, 8, 24)) << (2))) + (pc));
f_disp24 = ((((EXTRACT_MSB0_SINT (insn, 32, 8, 24)) * (4))) + (pc));
/* Record the fields for the semantic handler. */
FLD (i_disp24) = f_disp24;
@ -1177,7 +1180,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
#define FLD(f) abuf->fields.sfmt_bl8.f
SI f_disp8;
f_disp8 = ((((EXTRACT_MSB0_SINT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4))));
f_disp8 = ((((EXTRACT_MSB0_SINT (insn, 16, 8, 8)) * (4))) + (((pc) & (-4))));
/* Record the fields for the semantic handler. */
FLD (i_disp8) = f_disp8;
@ -1200,7 +1203,7 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
#define FLD(f) abuf->fields.sfmt_bl24.f
SI f_disp24;
f_disp24 = ((((EXTRACT_MSB0_SINT (insn, 32, 8, 24)) << (2))) + (pc));
f_disp24 = ((((EXTRACT_MSB0_SINT (insn, 32, 8, 24)) * (4))) + (pc));
/* Record the fields for the semantic handler. */
FLD (i_disp24) = f_disp24;

5
sim/m32r/decodex.h
View File

@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright 1996-2023 Free Software Foundation, Inc.
Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, see <http://www.gnu.org/licenses/>.
with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/

5
sim/m32r/model.c
View File

@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright 1996-2023 Free Software Foundation, Inc.
Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, see <http://www.gnu.org/licenses/>.
with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/

5
sim/m32r/model2.c
View File

@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright 1996-2023 Free Software Foundation, Inc.
Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, see <http://www.gnu.org/licenses/>.
with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/

5
sim/m32r/modelx.c
View File

@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright 1996-2023 Free Software Foundation, Inc.
Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, see <http://www.gnu.org/licenses/>.
with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/

5
sim/m32r/sem-switch.c
View File

@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright 1996-2023 Free Software Foundation, Inc.
Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, see <http://www.gnu.org/licenses/>.
with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/

5
sim/m32r/sem.c
View File

@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright 1996-2023 Free Software Foundation, Inc.
Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, see <http://www.gnu.org/licenses/>.
with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/

5
sim/m32r/sem2-switch.c
View File

@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright 1996-2023 Free Software Foundation, Inc.
Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, see <http://www.gnu.org/licenses/>.
with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/

5
sim/m32r/semx-switch.c
View File

@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright 1996-2023 Free Software Foundation, Inc.
Copyright (C) 1996-2023 Free Software Foundation, Inc.
This file is part of the GNU simulators.
@ -17,7 +17,8 @@ This file is part of the GNU simulators.
License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, see <http://www.gnu.org/licenses/>.
with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/

4
sim/or1k/cpu.h
View File

@ -4647,7 +4647,7 @@ struct scache {
#define EXTRACT_IFMT_L_J_CODE \
length = 4; \
f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
f_disp26 = ((((EXTRACT_LSB0_SINT (insn, 32, 25, 26)) << (2))) + (pc)); \
f_disp26 = ((((EXTRACT_LSB0_SINT (insn, 32, 25, 26)) * (4))) + (pc)); \
#define EXTRACT_IFMT_L_ADRP_VARS \
UINT f_opcode; \
@ -4658,7 +4658,7 @@ struct scache {
length = 4; \
f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
f_r1 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
f_disp21 = ((((EXTRACT_LSB0_SINT (insn, 32, 20, 21)) + (((SI) (pc) >> (13))))) << (13)); \
f_disp21 = ((((EXTRACT_LSB0_SINT (insn, 32, 20, 21)) + (((SI) (pc) >> (13))))) * (8192)); \
#define EXTRACT_IFMT_L_JR_VARS \
UINT f_opcode; \

12
sim/or1k/decode.c
View File

@ -27,6 +27,8 @@ This file is part of the GNU simulators.
#include "sim-main.h"
#include "sim-assert.h"
#include "cgen-mem.h"
#include "cgen-ops.h"
/* The instruction descriptor array.
This is computed at runtime. Space for it is not malloc'd to save a
@ -240,7 +242,7 @@ or1k32bf_init_idesc_table (SIM_CPU *cpu)
init_idesc (cpu, id, t);
/* Now fill in the values for the chosen cpu. */
for (t = or1k32bf_insn_sem, tend = t + sizeof (or1k32bf_insn_sem) / sizeof (*t);
for (t = or1k32bf_insn_sem, tend = t + ARRAY_SIZE (or1k32bf_insn_sem);
t != tend; ++t)
{
init_idesc (cpu, & table[t->index], t);
@ -1918,7 +1920,7 @@ or1k32bf_decode (SIM_CPU *current_cpu, IADDR pc,
#define FLD(f) abuf->fields.sfmt_l_j.f
USI f_disp26;
f_disp26 = ((((EXTRACT_LSB0_SINT (insn, 32, 25, 26)) << (2))) + (pc));
f_disp26 = ((((EXTRACT_LSB0_SINT (insn, 32, 25, 26)) * (4))) + (pc));
/* Record the fields for the semantic handler. */
FLD (i_disp26) = f_disp26;
@ -1937,7 +1939,7 @@ or1k32bf_decode (SIM_CPU *current_cpu, IADDR pc,
USI f_disp21;
f_r1 = EXTRACT_LSB0_UINT (insn, 32, 25, 5);
f_disp21 = ((((EXTRACT_LSB0_SINT (insn, 32, 20, 21)) + (((SI) (pc) >> (13))))) << (13));
f_disp21 = ((((EXTRACT_LSB0_SINT (insn, 32, 20, 21)) + (((SI) (pc) >> (13))))) * (8192));
/* Record the fields for the semantic handler. */
FLD (f_r1) = f_r1;
@ -1955,7 +1957,7 @@ or1k32bf_decode (SIM_CPU *current_cpu, IADDR pc,
#define FLD(f) abuf->fields.sfmt_l_j.f
USI f_disp26;
f_disp26 = ((((EXTRACT_LSB0_SINT (insn, 32, 25, 26)) << (2))) + (pc));
f_disp26 = ((((EXTRACT_LSB0_SINT (insn, 32, 25, 26)) * (4))) + (pc));
/* Record the fields for the semantic handler. */
FLD (i_disp26) = f_disp26;
@ -2006,7 +2008,7 @@ or1k32bf_decode (SIM_CPU *current_cpu, IADDR pc,
#define FLD(f) abuf->fields.sfmt_l_j.f
USI f_disp26;
f_disp26 = ((((EXTRACT_LSB0_SINT (insn, 32, 25, 26)) << (2))) + (pc));
f_disp26 = ((((EXTRACT_LSB0_SINT (insn, 32, 25, 26)) * (4))) + (pc));
/* Record the fields for the semantic handler. */
FLD (i_disp26) = f_disp26;

2
sim/or1k/sem-switch.c
View File

@ -199,7 +199,7 @@ This file is part of the GNU simulators.
/* If hyper-fast [well not unnecessarily slow] execution is selected, turn
off frills like tracing and profiling. */
/* FIXME: A better way would be to have TRACE_RESULT check for something
/* FIXME: A better way would be to have CGEN_TRACE_RESULT check for something
that can cause it to be optimized out. Another way would be to emit
special handlers into the instruction "stream". */

14120
sim/semcrisv32f-switch.c
View File

File diff suppressed because it is too large
Write Preview
Loading…
Cancel
Save