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* metag-dis.c: Initialize outf->bytes_per_chunk to 4 

which also makes the disassembler output be in little
	endian like it should be.

	* metag/labelarithmetic.d: Fix the expected disassembler
	output to be in little endian format
	* metag/metacore12.d: likewise
	* metag/metacore21.d: likewise
	* metag/metacore21ext.d: likewise
	* metag/metadsp21.d: likewise
	* metag/metadsp21ext.d: likewise
	* metag/metafpu.d: likewise
	* metag/metafpuext.d: likewise
	* metag/tls.d: likewise

	* ld-metag/pcrel.d: Fix the expected disassembler
	output to be in little endian format
	* ld-metag/shared.d: likewise
	* ld-metag/stub.d: likewise
	* ld-metag/stub_pic_app.d: likewise
	* ld-metag/stub_pic_shared.d: likewise
	* ld-metag/stub_shared.d: likewise
gdb_7_6-branch
Nick Clifton 14 years ago
parent
a043396b72
commit
9d1df426e2
19 changed files with 43614 additions and 43584 deletions
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  1. 13
      gas/testsuite/ChangeLog
  2. 14
      gas/testsuite/gas/metag/labelarithmetic.d
  3. 13734
      gas/testsuite/gas/metag/metacore12.d
  4. 15750
      gas/testsuite/gas/metag/metacore21.d
  5. 18
      gas/testsuite/gas/metag/metacore21ext.d
  6. 52594
      gas/testsuite/gas/metag/metadsp21.d
  7. 4
      gas/testsuite/gas/metag/metadsp21ext.d
  8. 4458
      gas/testsuite/gas/metag/metafpu21.d
  9. 380
      gas/testsuite/gas/metag/metafpu21ext.d
  10. 18
      gas/testsuite/gas/metag/tls.d
  11. 10
      ld/testsuite/ChangeLog
  12. 12
      ld/testsuite/ld-metag/pcrel.d
  13. 56
      ld/testsuite/ld-metag/shared.d
  14. 8
      ld/testsuite/ld-metag/stub.d
  15. 38
      ld/testsuite/ld-metag/stub_pic_app.d
  16. 38
      ld/testsuite/ld-metag/stub_pic_shared.d
  17. 46
      ld/testsuite/ld-metag/stub_shared.d
  18. 6
      opcodes/ChangeLog
  19. 1
      opcodes/metag-dis.c

13
gas/testsuite/ChangeLog
View File

@ -1,3 +1,16 @@
2013-02-15 Markos Chandras <markos.chandras@imgtec.com>
* gas/metag/labelarithmetic.d: Fix the expected disassembler
output to be in little endian format
* gas/metag/metacore12.d: likewise
* gas/metag/metacore21.d: likewise
* gas/metag/metacore21ext.d: likewise
* gas/metag/metadsp21.d: likewise
* gas/metag/metadsp21ext.d: likewise
* gas/metag/metafpu.d: likewise
* gas/metag/metafpuext.d: likewise
* gas/metag/tls.d: likewise
2013-02-15 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* gas/arm/neon-vmov-bad.d: New file.

14
gas/testsuite/gas/metag/labelarithmetic.d
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@ -7,16 +7,16 @@
Disassembly of section \.text:
00000000 <lbl1>:
.*: 20 04 2c 86 ADD TXL1START,CPC0,#0x10
.*: 862c0420 ADD TXL1START,CPC0,#0x10
00000004 <lbl2>:
.*: 04 20 00 80 MOV A0StP,CPC0
.*: a0 00 00 82 ADD A0StP,A0StP,#0x14
.*: 00 8c 01 a3 MOV TXL1END,A0StP
.*: 80002004 MOV A0StP,CPC0
.*: 820000a0 ADD A0StP,A0StP,#0x14
.*: a3018c00 MOV TXL1END,A0StP
00000010 <loop_start>:
.*: 04 04 18 00 MOV D0Ar2,D0Ar4
.*: fe ff ff a0 NOP
.*: 00180404 MOV D0Ar2,D0Ar4
.*: a0fffffe NOP
00000018 <loop_end>:
.*: 04 02 18 01 MOV D1Ar1,D1Ar5
.*: 01180204 MOV D1Ar1,D1Ar5

13734
gas/testsuite/gas/metag/metacore12.d
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File diff suppressed because it is too large

15750
gas/testsuite/gas/metag/metacore21.d
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File diff suppressed because it is too large

18
gas/testsuite/gas/metag/metacore21ext.d
View File

@ -7,12 +7,12 @@
Disassembly of section \.text:
00000000 <.text>:
.*: 40 46 00 60 MULD D0Re0,D0Ar6,D0Ar2
.*: ad 41 c0 c7 MOVL RABZ,\[D0Ar6\+\+\]
.*: cd 41 c8 c7 MOVL RAWZ,\[D1Ar5\+\+\]
.*: ad 81 d0 c7 MOVL RADZ,\[D0Ar4\+\+\]
.*: cd 81 e0 c7 MOVL RABX,\[D1Ar3\+\+\]
.*: ad c1 e8 c7 MOVL RAWX,\[D0Ar2\+\+\]
.*: cd c1 f0 c7 MOVL RADX,\[D1Ar1\+\+\]
.*: ad 01 f9 c7 MOVL RAMX,\[D0FrT\+\+\]
.*: ed 81 f8 c7 MOVL RAMX,\[A0\.2\+\+\]
.*: 60004640 MULD D0Re0,D0Ar6,D0Ar2
.*: c7c041ad MOVL RABZ,\[D0Ar6\+\+\]
.*: c7c841cd MOVL RAWZ,\[D1Ar5\+\+\]
.*: c7d081ad MOVL RADZ,\[D0Ar4\+\+\]
.*: c7e081cd MOVL RABX,\[D1Ar3\+\+\]
.*: c7e8c1ad MOVL RAWX,\[D0Ar2\+\+\]
.*: c7f0c1cd MOVL RADX,\[D1Ar1\+\+\]
.*: c7f901ad MOVL RAMX,\[D0FrT\+\+\]
.*: c7f881ed MOVL RAMX,\[A0\.2\+\+\]

52594
gas/testsuite/gas/metag/metadsp21.d
View File

File diff suppressed because it is too large

4
gas/testsuite/gas/metag/metadsp21ext.d
View File

@ -7,5 +7,5 @@
Disassembly of section \.text:
00000000 <.text>:
.*: e0 ce 02 90 D T0 #0x0,#0xb,#0x7,#0xe
.*: e0 ce 82 90 D T0 #0x10,#0xb,#0x7,#0xe
.*: 9002cee0 D T0 #0x0,#0xb,#0x7,#0xe
.*: 9082cee0 D T0 #0x10,#0xb,#0x7,#0xe

4458
gas/testsuite/gas/metag/metafpu21.d
View File

File diff suppressed because it is too large

380
gas/testsuite/gas/metag/metafpu21ext.d
View File

@ -7,193 +7,193 @@
Disassembly of section \.text:
00000000 <.text>:
.*: a0 80 00 f0 FD ABS FX\.0,FX\.2
.*: 80 00 18 f0 F ABS FX\.3,FX\.0
.*: c0 00 31 f0 FL ABS FX\.6,FX\.4
.*: 03 22 00 be F MMOVD D1Re0,D1Ar1,D1\.7,FX\.0,FX\.1,FX\.2
.*: 82 00 02 be F MMOVD D0Re0,D0Ar6,FX\.8,FX\.9
.*: 82 a0 00 bf F MMOVL D0Re0,D0Ar6,D0\.7,FX\.2,FX\.4,FX\.6
.*: 83 00 18 bf F MMOVL D1Ar1,D1RtP,FX\.0,FX\.2
.*: 03 22 00 ce F MMOVD FX\.0,FX\.1,FX\.2,D1Re0,D1Ar1,D1\.7
.*: 82 00 02 ce F MMOVD FX\.8,FX\.9,D0Re0,D0Ar6
.*: 82 a0 00 cf F MMOVL FX\.2,FX\.4,FX\.6,D0Re0,D0Ar6,D0\.7
.*: 83 00 18 cf F MMOVL FX\.0,FX\.2,D1Ar1,D1RtP
.*: 20 80 00 f0 FD MOV FX\.0,FX\.2
.*: 00 00 18 f0 F MOV FX\.3,FX\.0
.*: 40 00 31 f0 FL MOV FX\.6,FX\.4
.*: fb ff 07 f0 FD MOV FX\.0,#0xffff
.*: 81 00 18 f0 F MOV FX\.3,#0x10
.*: 05 78 30 f0 FL MOV FX\.6,#0xf00
.*: 20 81 00 f0 FD NEG FX\.0,FX\.2
.*: 00 01 18 f0 F NEG FX\.3,FX\.0
.*: 40 01 31 f0 FL NEG FX\.6,FX\.4
.*: 80 51 30 f0 F PACK FX\.6,FX\.1,FX\.8
.*: c0 01 30 f0 FL SWAP FX\.6,FX\.0
.*: 20 80 01 f3 FD CMP FX\.6,FX\.0
.*: 00 80 01 f3 F CMP FX\.6,FX\.0
.*: 40 80 01 f3 FL CMP FX\.6,FX\.0
.*: 20 80 09 f3 FDA CMP FX\.6,FX\.0
.*: 00 80 09 f3 FA CMP FX\.6,FX\.0
.*: 40 80 09 f3 FLA CMP FX\.6,FX\.0
.*: a0 80 01 f3 FDQ CMP FX\.6,FX\.0
.*: 80 80 01 f3 FQ CMP FX\.6,FX\.0
.*: c0 80 01 f3 FLQ CMP FX\.6,FX\.0
.*: a0 80 09 f3 FDAQ CMP FX\.6,FX\.0
.*: 80 80 09 f3 FAQ CMP FX\.6,FX\.0
.*: c0 80 09 f3 FLAQ CMP FX\.6,FX\.0
.*: 20 81 01 f3 FD CMP FX\.6,#0
.*: 00 81 01 f3 F CMP FX\.6,#0
.*: 40 81 01 f3 FL CMP FX\.6,#0
.*: a1 04 30 f3 FD MAX FX\.6,FX\.0,FX\.2
.*: 81 0a 19 f3 F MAX FX\.3,FX\.4,FX\.5
.*: c1 0c 11 f3 FL MAX FX\.2,FX\.4,FX\.6
.*: 21 04 30 f3 FD MIN FX\.6,FX\.0,FX\.2
.*: 01 0a 19 f3 F MIN FX\.3,FX\.4,FX\.5
.*: 41 0c 11 f3 FL MIN FX\.2,FX\.4,FX\.6
.*: 21 41 30 f2 F DTOF FX\.6,FX\.1
.*: 01 81 00 f2 F FTOD FX\.0,FX\.2
.*: 40 03 30 f2 FL FTOH FX\.6,FX\.0
.*: 00 43 19 f2 F FTOH FX\.3,FX\.5
.*: 20 03 10 f2 F DTOH FX\.2,FX\.0
.*: 00 71 30 f2 FZ FTOI FX\.6,FX\.1
.*: 00 21 11 f2 F FTOI FX\.2,FX\.4
.*: 40 21 20 f2 FL FTOI FX\.4,FX\.0
.*: 40 71 19 f2 FLZ FTOI FX\.3,FX\.5
.*: 20 61 30 f2 F DTOI FX\.6,FX\.1
.*: 20 71 30 f2 FZ DTOI FX\.6,FX\.1
.*: 20 23 11 f2 F DTOL FX\.2,FX\.4
.*: 20 33 11 f2 FZ DTOL FX\.2,FX\.4
.*: 00 c6 30 f2 F FTOX FX\.6,FX\.3,#0x3
.*: 40 08 20 f2 FL FTOX FX\.4,FX\.0,#0x4
.*: 20 10 11 f2 F DTOX FX\.2,FX\.4,#0x8
.*: a0 06 11 f2 F DTOXL FX\.2,FX\.4,#0x6
.*: 21 03 31 f2 F HTOD FX\.6,FX\.4
.*: 41 83 30 f2 FL HTOF FX\.6,FX\.2
.*: 01 03 11 f2 F HTOF FX\.2,FX\.4
.*: 01 61 30 f2 F ITOF FX\.6,FX\.1
.*: 41 21 20 f2 FL ITOF FX\.4,FX\.0
.*: 21 21 11 f2 F ITOD FX\.2,FX\.4
.*: 21 23 11 f2 F LTOD FX\.2,FX\.4
.*: 01 c4 10 f2 F XTOF FX\.2,FX\.3,#0x2
.*: 41 06 30 f2 FL XTOF FX\.6,FX\.0,#0x3
.*: 21 08 11 f2 F XTOD FX\.2,FX\.4,#0x4
.*: a1 07 11 f2 F XLTOD FX\.2,FX\.4,#0x7
.*: 21 88 00 f1 FD ADD FX\.0,FX\.2,FX\.4
.*: 01 40 18 f1 F ADD FX\.3,FX\.1,FX\.0
.*: 41 04 31 f1 FL ADD FX\.6,FX\.4,FX\.2
.*: a1 88 00 f1 FDI ADD FX\.0,FX\.2,FX\.4
.*: 81 40 18 f1 FI ADD FX\.3,FX\.1,FX\.0
.*: c1 04 31 f1 FLI ADD FX\.6,FX\.4,FX\.2
.*: 20 89 00 f1 FD MUL FX\.0,FX\.2,FX\.4
.*: 00 41 18 f1 F MUL FX\.3,FX\.1,FX\.0
.*: 40 05 31 f1 FL MUL FX\.6,FX\.4,FX\.2
.*: a0 89 00 f1 FDI MUL FX\.0,FX\.2,FX\.4
.*: 80 41 18 f1 FI MUL FX\.3,FX\.1,FX\.0
.*: c0 05 31 f1 FLI MUL FX\.6,FX\.4,FX\.2
.*: 21 89 00 f1 FD SUB FX\.0,FX\.2,FX\.4
.*: 01 41 18 f1 F SUB FX\.3,FX\.1,FX\.0
.*: 41 05 31 f1 FL SUB FX\.6,FX\.4,FX\.2
.*: a1 89 00 f1 FDI SUB FX\.0,FX\.2,FX\.4
.*: 81 41 18 f1 FI SUB FX\.3,FX\.1,FX\.0
.*: c1 05 31 f1 FLI SUB FX\.6,FX\.4,FX\.2
.*: 20 88 00 f6 FD MAC ACF\.0,FX\.2,FX\.4
.*: 00 40 00 f6 F MAC ACF\.0,FX\.1,FX\.0
.*: 24 88 00 f6 FD MAR FX\.0,FX\.2,FX\.4
.*: 04 40 18 f6 F MAR FX\.3,FX\.1,FX\.0
.*: 24 89 00 f6 FD MARS FX\.0,FX\.2,FX\.4
.*: 04 41 18 f6 F MARS FX\.3,FX\.1,FX\.0
.*: 28 0c 11 f6 FD MAW FX\.2,FX\.4,FX\.6
.*: 08 0c 08 f6 F MAW FX\.1,FX\.0,FX\.6
.*: 28 0d 11 f6 FD MAWS FX\.2,FX\.4,FX\.6
.*: 08 0d 08 f6 F MAWS FX\.1,FX\.0,FX\.6
.*: 29 0c 01 f6 FD MAW1 FX\.4,FX\.6
.*: 09 0c 00 f6 F MAW1 FX\.0,FX\.6
.*: 29 0d 01 f6 FD MAWS1 FX\.4,FX\.6
.*: 09 0d 00 f6 F MAWS1 FX\.0,FX\.6
.*: 20 88 00 f5 FD MXA FX\.0,FX\.2,FX\.4
.*: 00 40 18 f5 F MXA FX\.3,FX\.1,FX\.0
.*: 40 04 31 f5 FL MXA FX\.6,FX\.4,FX\.2
.*: a0 88 00 f5 FDI MXA FX\.0,FX\.2,FX\.4
.*: 80 40 18 f5 FI MXA FX\.3,FX\.1,FX\.0
.*: c0 04 31 f5 FLI MXA FX\.6,FX\.4,FX\.2
.*: 20 89 00 f5 FD MXAS FX\.0,FX\.2,FX\.4
.*: 00 41 18 f5 F MXAS FX\.3,FX\.1,FX\.0
.*: 40 05 31 f5 FL MXAS FX\.6,FX\.4,FX\.2
.*: a0 89 00 f5 FDI MXAS FX\.0,FX\.2,FX\.4
.*: 80 41 18 f5 FI MXAS FX\.3,FX\.1,FX\.0
.*: c0 05 31 f5 FLI MXAS FX\.6,FX\.4,FX\.2
.*: 21 88 00 f5 FD MXA1 FX\.0,FX\.2,FX\.4
.*: 01 40 18 f5 F MXA1 FX\.3,FX\.1,FX\.0
.*: 41 04 31 f5 FL MXA1 FX\.6,FX\.4,FX\.2
.*: a1 88 00 f5 FDI MXA1 FX\.0,FX\.2,FX\.4
.*: 81 40 18 f5 FI MXA1 FX\.3,FX\.1,FX\.0
.*: c1 04 31 f5 FLI MXA1 FX\.6,FX\.4,FX\.2
.*: 21 89 00 f5 FD MXAS1 FX\.0,FX\.2,FX\.4
.*: 01 41 18 f5 F MXAS1 FX\.3,FX\.1,FX\.0
.*: 41 05 31 f5 FL MXAS1 FX\.6,FX\.4,FX\.2
.*: a1 89 00 f5 FDI MXAS1 FX\.0,FX\.2,FX\.4
.*: 81 41 18 f5 FI MXAS1 FX\.3,FX\.1,FX\.0
.*: c1 05 31 f5 FLI MXAS1 FX\.6,FX\.4,FX\.2
.*: 30 88 00 f6 FD MUZ FX\.0,FX\.2,FX\.4
.*: 10 4c 21 f6 F MUZ FX\.4,FX\.5,FX\.6
.*: 50 04 31 f6 FL MUZ FX\.6,FX\.4,FX\.2
.*: b0 88 00 f6 FDI MUZ FX\.0,FX\.2,FX\.4
.*: 90 4c 21 f6 FI MUZ FX\.4,FX\.5,FX\.6
.*: d0 04 31 f6 FLI MUZ FX\.6,FX\.4,FX\.2
.*: 32 88 00 f6 FDQ MUZ FX\.0,FX\.2,FX\.4
.*: 12 4c 21 f6 FQ MUZ FX\.4,FX\.5,FX\.6
.*: 52 04 31 f6 FLQ MUZ FX\.6,FX\.4,FX\.2
.*: b2 88 00 f6 FDIQ MUZ FX\.0,FX\.2,FX\.4
.*: 92 4c 21 f6 FIQ MUZ FX\.4,FX\.5,FX\.6
.*: d2 04 31 f6 FLIQ MUZ FX\.6,FX\.4,FX\.2
.*: 30 89 00 f6 FD MUZS FX\.0,FX\.2,FX\.4
.*: 10 4d 21 f6 F MUZS FX\.4,FX\.5,FX\.6
.*: 50 05 31 f6 FL MUZS FX\.6,FX\.4,FX\.2
.*: 31 88 00 f6 FD MUZ1 FX\.0,FX\.2,FX\.4
.*: 11 4c 21 f6 F MUZ1 FX\.4,FX\.5,FX\.6
.*: 51 04 31 f6 FL MUZ1 FX\.6,FX\.4,FX\.2
.*: 31 89 00 f6 FD MUZS1 FX\.0,FX\.2,FX\.4
.*: 11 4d 21 f6 F MUZS1 FX\.4,FX\.5,FX\.6
.*: 51 05 31 f6 FL MUZS1 FX\.6,FX\.4,FX\.2
.*: 20 80 00 f7 FD RCP FX\.0,FX\.2
.*: 00 40 18 f7 F RCP FX\.3,FX\.1
.*: 40 00 31 f7 FL RCP FX\.6,FX\.4
.*: a0 80 00 f7 FDI RCP FX\.0,FX\.2
.*: 80 40 18 f7 FI RCP FX\.3,FX\.1
.*: c0 00 31 f7 FLI RCP FX\.6,FX\.4
.*: 20 84 00 f7 FDZ RCP FX\.0,FX\.2
.*: 00 44 18 f7 FZ RCP FX\.3,FX\.1
.*: 40 04 31 f7 FLZ RCP FX\.6,FX\.4
.*: a0 84 00 f7 FDIZ RCP FX\.0,FX\.2
.*: 80 44 18 f7 FIZ RCP FX\.3,FX\.1
.*: c0 04 31 f7 FLIZ RCP FX\.6,FX\.4
.*: 20 82 00 f7 FDQ RCP FX\.0,FX\.2
.*: 00 42 18 f7 FQ RCP FX\.3,FX\.1
.*: 40 02 31 f7 FLQ RCP FX\.6,FX\.4
.*: a0 82 00 f7 FDIQ RCP FX\.0,FX\.2
.*: 80 42 18 f7 FIQ RCP FX\.3,FX\.1
.*: c0 02 31 f7 FLIQ RCP FX\.6,FX\.4
.*: 20 81 00 f7 FD RSQ FX\.0,FX\.2
.*: 00 41 18 f7 F RSQ FX\.3,FX\.1
.*: 40 01 31 f7 FL RSQ FX\.6,FX\.4
.*: a0 81 00 f7 FDI RSQ FX\.0,FX\.2
.*: 80 41 18 f7 FI RSQ FX\.3,FX\.1
.*: c0 01 31 f7 FLI RSQ FX\.6,FX\.4
.*: 20 85 00 f7 FDZ RSQ FX\.0,FX\.2
.*: 00 45 18 f7 FZ RSQ FX\.3,FX\.1
.*: 40 05 31 f7 FLZ RSQ FX\.6,FX\.4
.*: a0 85 00 f7 FDIZ RSQ FX\.0,FX\.2
.*: 80 45 18 f7 FIZ RSQ FX\.3,FX\.1
.*: c0 05 31 f7 FLIZ RSQ FX\.6,FX\.4
.*: 20 83 00 f7 FDQ RSQ FX\.0,FX\.2
.*: 00 43 18 f7 FQ RSQ FX\.3,FX\.1
.*: 40 03 31 f7 FLQ RSQ FX\.6,FX\.4
.*: a0 83 00 f7 FDIQ RSQ FX\.0,FX\.2
.*: 80 43 18 f7 FIQ RSQ FX\.3,FX\.1
.*: c0 03 31 f7 FLIQ RSQ FX\.6,FX\.4
.*: 00 04 31 f4 FL ADDRE FX\.6,FX\.4,FX\.2
.*: 80 04 31 f4 FLI ADDRE FX\.6,FX\.4,FX\.2
.*: 01 04 31 f4 FL MULRE FX\.6,FX\.4,FX\.2
.*: 81 04 31 f4 FLI MULRE FX\.6,FX\.4,FX\.2
.*: 00 05 31 f4 FL SUBRE FX\.6,FX\.4,FX\.2
.*: 80 05 31 f4 FLI SUBRE FX\.6,FX\.4,FX\.2
.*: f00080a0 FD ABS FX\.0,FX\.2
.*: f0180080 F ABS FX\.3,FX\.0
.*: f03100c0 FL ABS FX\.6,FX\.4
.*: be002203 F MMOVD D1Re0,D1Ar1,D1\.7,FX\.0,FX\.1,FX\.2
.*: be020082 F MMOVD D0Re0,D0Ar6,FX\.8,FX\.9
.*: bf00a082 F MMOVL D0Re0,D0Ar6,D0\.7,FX\.2,FX\.4,FX\.6
.*: bf180083 F MMOVL D1Ar1,D1RtP,FX\.0,FX\.2
.*: ce002203 F MMOVD FX\.0,FX\.1,FX\.2,D1Re0,D1Ar1,D1\.7
.*: ce020082 F MMOVD FX\.8,FX\.9,D0Re0,D0Ar6
.*: cf00a082 F MMOVL FX\.2,FX\.4,FX\.6,D0Re0,D0Ar6,D0\.7
.*: cf180083 F MMOVL FX\.0,FX\.2,D1Ar1,D1RtP
.*: f0008020 FD MOV FX\.0,FX\.2
.*: f0180000 F MOV FX\.3,FX\.0
.*: f0310040 FL MOV FX\.6,FX\.4
.*: f007fffb FD MOV FX\.0,#0xffff
.*: f0180081 F MOV FX\.3,#0x10
.*: f0307805 FL MOV FX\.6,#0xf00
.*: f0008120 FD NEG FX\.0,FX\.2
.*: f0180100 F NEG FX\.3,FX\.0
.*: f0310140 FL NEG FX\.6,FX\.4
.*: f0305180 F PACK FX\.6,FX\.1,FX\.8
.*: f03001c0 FL SWAP FX\.6,FX\.0
.*: f3018020 FD CMP FX\.6,FX\.0
.*: f3018000 F CMP FX\.6,FX\.0
.*: f3018040 FL CMP FX\.6,FX\.0
.*: f3098020 FDA CMP FX\.6,FX\.0
.*: f3098000 FA CMP FX\.6,FX\.0
.*: f3098040 FLA CMP FX\.6,FX\.0
.*: f30180a0 FDQ CMP FX\.6,FX\.0
.*: f3018080 FQ CMP FX\.6,FX\.0
.*: f30180c0 FLQ CMP FX\.6,FX\.0
.*: f30980a0 FDAQ CMP FX\.6,FX\.0
.*: f3098080 FAQ CMP FX\.6,FX\.0
.*: f30980c0 FLAQ CMP FX\.6,FX\.0
.*: f3018120 FD CMP FX\.6,#0
.*: f3018100 F CMP FX\.6,#0
.*: f3018140 FL CMP FX\.6,#0
.*: f33004a1 FD MAX FX\.6,FX\.0,FX\.2
.*: f3190a81 F MAX FX\.3,FX\.4,FX\.5
.*: f3110cc1 FL MAX FX\.2,FX\.4,FX\.6
.*: f3300421 FD MIN FX\.6,FX\.0,FX\.2
.*: f3190a01 F MIN FX\.3,FX\.4,FX\.5
.*: f3110c41 FL MIN FX\.2,FX\.4,FX\.6
.*: f2304121 F DTOF FX\.6,FX\.1
.*: f2008101 F FTOD FX\.0,FX\.2
.*: f2300340 FL FTOH FX\.6,FX\.0
.*: f2194300 F FTOH FX\.3,FX\.5
.*: f2100320 F DTOH FX\.2,FX\.0
.*: f2307100 FZ FTOI FX\.6,FX\.1
.*: f2112100 F FTOI FX\.2,FX\.4
.*: f2202140 FL FTOI FX\.4,FX\.0
.*: f2197140 FLZ FTOI FX\.3,FX\.5
.*: f2306120 F DTOI FX\.6,FX\.1
.*: f2307120 FZ DTOI FX\.6,FX\.1
.*: f2112320 F DTOL FX\.2,FX\.4
.*: f2113320 FZ DTOL FX\.2,FX\.4
.*: f230c600 F FTOX FX\.6,FX\.3,#0x3
.*: f2200840 FL FTOX FX\.4,FX\.0,#0x4
.*: f2111020 F DTOX FX\.2,FX\.4,#0x8
.*: f21106a0 F DTOXL FX\.2,FX\.4,#0x6
.*: f2310321 F HTOD FX\.6,FX\.4
.*: f2308341 FL HTOF FX\.6,FX\.2
.*: f2110301 F HTOF FX\.2,FX\.4
.*: f2306101 F ITOF FX\.6,FX\.1
.*: f2202141 FL ITOF FX\.4,FX\.0
.*: f2112121 F ITOD FX\.2,FX\.4
.*: f2112321 F LTOD FX\.2,FX\.4
.*: f210c401 F XTOF FX\.2,FX\.3,#0x2
.*: f2300641 FL XTOF FX\.6,FX\.0,#0x3
.*: f2110821 F XTOD FX\.2,FX\.4,#0x4
.*: f21107a1 F XLTOD FX\.2,FX\.4,#0x7
.*: f1008821 FD ADD FX\.0,FX\.2,FX\.4
.*: f1184001 F ADD FX\.3,FX\.1,FX\.0
.*: f1310441 FL ADD FX\.6,FX\.4,FX\.2
.*: f10088a1 FDI ADD FX\.0,FX\.2,FX\.4
.*: f1184081 FI ADD FX\.3,FX\.1,FX\.0
.*: f13104c1 FLI ADD FX\.6,FX\.4,FX\.2
.*: f1008920 FD MUL FX\.0,FX\.2,FX\.4
.*: f1184100 F MUL FX\.3,FX\.1,FX\.0
.*: f1310540 FL MUL FX\.6,FX\.4,FX\.2
.*: f10089a0 FDI MUL FX\.0,FX\.2,FX\.4
.*: f1184180 FI MUL FX\.3,FX\.1,FX\.0
.*: f13105c0 FLI MUL FX\.6,FX\.4,FX\.2
.*: f1008921 FD SUB FX\.0,FX\.2,FX\.4
.*: f1184101 F SUB FX\.3,FX\.1,FX\.0
.*: f1310541 FL SUB FX\.6,FX\.4,FX\.2
.*: f10089a1 FDI SUB FX\.0,FX\.2,FX\.4
.*: f1184181 FI SUB FX\.3,FX\.1,FX\.0
.*: f13105c1 FLI SUB FX\.6,FX\.4,FX\.2
.*: f6008820 FD MAC ACF\.0,FX\.2,FX\.4
.*: f6004000 F MAC ACF\.0,FX\.1,FX\.0
.*: f6008824 FD MAR FX\.0,FX\.2,FX\.4
.*: f6184004 F MAR FX\.3,FX\.1,FX\.0
.*: f6008924 FD MARS FX\.0,FX\.2,FX\.4
.*: f6184104 F MARS FX\.3,FX\.1,FX\.0
.*: f6110c28 FD MAW FX\.2,FX\.4,FX\.6
.*: f6080c08 F MAW FX\.1,FX\.0,FX\.6
.*: f6110d28 FD MAWS FX\.2,FX\.4,FX\.6
.*: f6080d08 F MAWS FX\.1,FX\.0,FX\.6
.*: f6010c29 FD MAW1 FX\.4,FX\.6
.*: f6000c09 F MAW1 FX\.0,FX\.6
.*: f6010d29 FD MAWS1 FX\.4,FX\.6
.*: f6000d09 F MAWS1 FX\.0,FX\.6
.*: f5008820 FD MXA FX\.0,FX\.2,FX\.4
.*: f5184000 F MXA FX\.3,FX\.1,FX\.0
.*: f5310440 FL MXA FX\.6,FX\.4,FX\.2
.*: f50088a0 FDI MXA FX\.0,FX\.2,FX\.4
.*: f5184080 FI MXA FX\.3,FX\.1,FX\.0
.*: f53104c0 FLI MXA FX\.6,FX\.4,FX\.2
.*: f5008920 FD MXAS FX\.0,FX\.2,FX\.4
.*: f5184100 F MXAS FX\.3,FX\.1,FX\.0
.*: f5310540 FL MXAS FX\.6,FX\.4,FX\.2
.*: f50089a0 FDI MXAS FX\.0,FX\.2,FX\.4
.*: f5184180 FI MXAS FX\.3,FX\.1,FX\.0
.*: f53105c0 FLI MXAS FX\.6,FX\.4,FX\.2
.*: f5008821 FD MXA1 FX\.0,FX\.2,FX\.4
.*: f5184001 F MXA1 FX\.3,FX\.1,FX\.0
.*: f5310441 FL MXA1 FX\.6,FX\.4,FX\.2
.*: f50088a1 FDI MXA1 FX\.0,FX\.2,FX\.4
.*: f5184081 FI MXA1 FX\.3,FX\.1,FX\.0
.*: f53104c1 FLI MXA1 FX\.6,FX\.4,FX\.2
.*: f5008921 FD MXAS1 FX\.0,FX\.2,FX\.4
.*: f5184101 F MXAS1 FX\.3,FX\.1,FX\.0
.*: f5310541 FL MXAS1 FX\.6,FX\.4,FX\.2
.*: f50089a1 FDI MXAS1 FX\.0,FX\.2,FX\.4
.*: f5184181 FI MXAS1 FX\.3,FX\.1,FX\.0
.*: f53105c1 FLI MXAS1 FX\.6,FX\.4,FX\.2
.*: f6008830 FD MUZ FX\.0,FX\.2,FX\.4
.*: f6214c10 F MUZ FX\.4,FX\.5,FX\.6
.*: f6310450 FL MUZ FX\.6,FX\.4,FX\.2
.*: f60088b0 FDI MUZ FX\.0,FX\.2,FX\.4
.*: f6214c90 FI MUZ FX\.4,FX\.5,FX\.6
.*: f63104d0 FLI MUZ FX\.6,FX\.4,FX\.2
.*: f6008832 FDQ MUZ FX\.0,FX\.2,FX\.4
.*: f6214c12 FQ MUZ FX\.4,FX\.5,FX\.6
.*: f6310452 FLQ MUZ FX\.6,FX\.4,FX\.2
.*: f60088b2 FDIQ MUZ FX\.0,FX\.2,FX\.4
.*: f6214c92 FIQ MUZ FX\.4,FX\.5,FX\.6
.*: f63104d2 FLIQ MUZ FX\.6,FX\.4,FX\.2
.*: f6008930 FD MUZS FX\.0,FX\.2,FX\.4
.*: f6214d10 F MUZS FX\.4,FX\.5,FX\.6
.*: f6310550 FL MUZS FX\.6,FX\.4,FX\.2
.*: f6008831 FD MUZ1 FX\.0,FX\.2,FX\.4
.*: f6214c11 F MUZ1 FX\.4,FX\.5,FX\.6
.*: f6310451 FL MUZ1 FX\.6,FX\.4,FX\.2
.*: f6008931 FD MUZS1 FX\.0,FX\.2,FX\.4
.*: f6214d11 F MUZS1 FX\.4,FX\.5,FX\.6
.*: f6310551 FL MUZS1 FX\.6,FX\.4,FX\.2
.*: f7008020 FD RCP FX\.0,FX\.2
.*: f7184000 F RCP FX\.3,FX\.1
.*: f7310040 FL RCP FX\.6,FX\.4
.*: f70080a0 FDI RCP FX\.0,FX\.2
.*: f7184080 FI RCP FX\.3,FX\.1
.*: f73100c0 FLI RCP FX\.6,FX\.4
.*: f7008420 FDZ RCP FX\.0,FX\.2
.*: f7184400 FZ RCP FX\.3,FX\.1
.*: f7310440 FLZ RCP FX\.6,FX\.4
.*: f70084a0 FDIZ RCP FX\.0,FX\.2
.*: f7184480 FIZ RCP FX\.3,FX\.1
.*: f73104c0 FLIZ RCP FX\.6,FX\.4
.*: f7008220 FDQ RCP FX\.0,FX\.2
.*: f7184200 FQ RCP FX\.3,FX\.1
.*: f7310240 FLQ RCP FX\.6,FX\.4
.*: f70082a0 FDIQ RCP FX\.0,FX\.2
.*: f7184280 FIQ RCP FX\.3,FX\.1
.*: f73102c0 FLIQ RCP FX\.6,FX\.4
.*: f7008120 FD RSQ FX\.0,FX\.2
.*: f7184100 F RSQ FX\.3,FX\.1
.*: f7310140 FL RSQ FX\.6,FX\.4
.*: f70081a0 FDI RSQ FX\.0,FX\.2
.*: f7184180 FI RSQ FX\.3,FX\.1
.*: f73101c0 FLI RSQ FX\.6,FX\.4
.*: f7008520 FDZ RSQ FX\.0,FX\.2
.*: f7184500 FZ RSQ FX\.3,FX\.1
.*: f7310540 FLZ RSQ FX\.6,FX\.4
.*: f70085a0 FDIZ RSQ FX\.0,FX\.2
.*: f7184580 FIZ RSQ FX\.3,FX\.1
.*: f73105c0 FLIZ RSQ FX\.6,FX\.4
.*: f7008320 FDQ RSQ FX\.0,FX\.2
.*: f7184300 FQ RSQ FX\.3,FX\.1
.*: f7310340 FLQ RSQ FX\.6,FX\.4
.*: f70083a0 FDIQ RSQ FX\.0,FX\.2
.*: f7184380 FIQ RSQ FX\.3,FX\.1
.*: f73103c0 FLIQ RSQ FX\.6,FX\.4
.*: f4310400 FL ADDRE FX\.6,FX\.4,FX\.2
.*: f4310480 FLI ADDRE FX\.6,FX\.4,FX\.2
.*: f4310401 FL MULRE FX\.6,FX\.4,FX\.2
.*: f4310481 FLI MULRE FX\.6,FX\.4,FX\.2
.*: f4310500 FL SUBRE FX\.6,FX\.4,FX\.2
.*: f4310580 FLI SUBRE FX\.6,FX\.4,FX\.2

18
gas/testsuite/gas/metag/tls.d
View File

@ -6,21 +6,21 @@
Disassembly of section \.text:
00000000 <.text>:
0: 00 00 18 03 ADD D1Ar1,D1Ar1,#0
0: 03180000 ADD D1Ar1,D1Ar1,#0
0: R_METAG_TLS_GD _a
4: 00 00 18 03 ADD D1Ar1,D1Ar1,#0
4: 03180000 ADD D1Ar1,D1Ar1,#0
4: R_METAG_TLS_LDM _b
8: 01 00 00 02 ADDT D0Re0,D0Re0,#0
8: 02000001 ADDT D0Re0,D0Re0,#0
8: R_METAG_TLS_LDO_HI16 _b
c: 00 00 00 02 ADD D0Re0,D0Re0,#0
c: 02000000 ADD D0Re0,D0Re0,#0
c: R_METAG_TLS_LDO_LO16 _b
10: 0d 00 20 a7 GETD D0FrT,\[A1LbP\]
10: a720000d GETD D0FrT,\[A1LbP\]
10: R_METAG_TLS_IE _b
14: 05 00 00 02 MOVT D0Re0,#0
14: 02000005 MOVT D0Re0,#0
14: R_METAG_TLS_IENONPIC_HI16 _b
18: 00 00 00 02 ADD D0Re0,D0Re0,#0
18: 02000000 ADD D0Re0,D0Re0,#0
18: R_METAG_TLS_IENONPIC_LO16 _b
1c: 01 00 00 02 ADDT D0Re0,D0Re0,#0
1c: 02000001 ADDT D0Re0,D0Re0,#0
1c: R_METAG_TLS_LE_HI16 _b
20: 00 00 00 02 ADD D0Re0,D0Re0,#0
20: 02000000 ADD D0Re0,D0Re0,#0
20: R_METAG_TLS_LE_LO16 _b

10
ld/testsuite/ChangeLog
View File

@ -1,3 +1,13 @@
2013-02-15 Markos Chandras <markos.chandras@imgtec.com>
* ld-metag/pcrel.d: Fix the expected disassembler
output to be in little endian format
* ld-metag/shared.d: likewise
* ld-metag/stub.d: likewise
* ld-metag/stub_pic_app.d: likewise
* ld-metag/stub_pic_shared.d: likewise
* ld-metag/stub_shared.d: likewise
2013-02-13 Richard Sandiford <rdsandiford@googlemail.com>
* ld-mips-elf/mips16-pic-2.dd,

12
ld/testsuite/ld-metag/pcrel.d
View File

@ -4,15 +4,15 @@
Disassembly of section .text:
.* <_start>:
.*: a8 00 00 ab CALLR D0Re0,10005068 <external>
.*: 48 00 00 ab CALLR D0Re0,10005060 <global>
.*: 48 00 00 ab CALLR D0Re0,10005064 <local>
.*: ab0000a8 CALLR D0Re0,10005068 <external>
.*: ab000048 CALLR D0Re0,10005060 <global>
.*: ab000048 CALLR D0Re0,10005064 <local>
.* <global>:
.*: fe ff ff a0 NOP
.*: a0fffffe NOP
.* <local>:
.*: fe ff ff a0 NOP
.*: a0fffffe NOP
.* <external>:
.*: fe ff ff a0 NOP
.*: a0fffffe NOP

56
ld/testsuite/ld-metag/shared.d
View File

@ -7,35 +7,35 @@ start address 0x.*
Disassembly of section .plt:
.* <.*>:
.*: 01 00 90 82 ADDT A0.2,CPC0,#0
.*: 60 08 12 82 ADD A0.2,A0.2,#0x410c
.*: 20 0c 10 a3 MOV D0Re0,A0.2
.*: e3 01 00 b7 SETL \[A0StP\+\+\],D0Re0,D1Re0
.*: 2a 01 00 c6 GETD PC,\[D0Re0\+#4\]
.*: 82900001 ADDT A0.2,CPC0,#0
.*: 82120860 ADD A0.2,A0.2,#0x410c
.*: a3100c20 MOV D0Re0,A0.2
.*: b70001e3 SETL \[A0StP\+\+\],D0Re0,D1Re0
.*: c600012a GETD PC,\[D0Re0\+#4\]
.* <app_func2@plt>:
.*: 01 00 90 82 ADDT A0.2,CPC0,#0
.*: 80 07 12 82 ADD A0.2,A0.2,#0x40f0
.*: 6a 80 00 c6 GETD PC,\[A0.2\]
.*: 04 00 00 03 MOV D1Re0,#0
.*: e0 fe ff a0 B 184 <app_func2@plt-0x14>
.*: 82900001 ADDT A0.2,CPC0,#0
.*: 82120780 ADD A0.2,A0.2,#0x40f0
.*: c600806a GETD PC,\[A0.2\]
.*: 03000004 MOV D1Re0,#0
.*: a0fffee0 B 184 <app_func2@plt-0x14>
Disassembly of section .text:
.* <lib_func1>:
.*: 05 32 20 00 MOV D0FrT,A0FrP
.*: 26 00 08 86 ADD A0FrP,A0StP,#0
.*: e3 01 20 b7 SETL \[A0StP\+\+\],D0FrT,D1RtP
.*: e9 02 08 b6 SETD \[A0StP\+#8\+\+\],A1LbP
.*: 40 00 00 82 ADD A0StP,A0StP,#0x8
.*: 01 00 88 83 ADDT A1LbP,CPC1,#0
.*: 60 06 0b 83 ADD A1LbP,A1LbP,#0x60cc
.*: 94 fe ff ab CALLR D1RtP,198 <app_func2@plt>
.*: 8d 01 0c a7 GETD D0Ar6,\[A1LbP\+#-8180\]
.*: 00 02 00 00 ADD D0Re0,D0Re0,D0Ar6
.*: 05 02 00 01 MOV D1Re0,A1LbP
.*: f9 ff 07 03 ADDT D1Re0,D1Re0,#0xffff
.*: c0 ff 06 03 ADD D1Re0,D1Re0,#0xdff8
.*: 64 fe 0f a7 GETD A1LbP,\[A0StP\+#-16\]
.*: e3 41 20 c7 GETL D0FrT,D1RtP,\[A0FrP\+\+\]
.*: 26 42 00 8e SUB A0StP,A0FrP,#0x8
.*: 05 18 08 80 MOV A0FrP,D0FrT
.*: a0 08 20 a3 MOV PC,D1RtP
.*: 00203205 MOV D0FrT,A0FrP
.*: 86080026 ADD A0FrP,A0StP,#0
.*: b72001e3 SETL \[A0StP\+\+\],D0FrT,D1RtP
.*: b60802e9 SETD \[A0StP\+#8\+\+\],A1LbP
.*: 82000040 ADD A0StP,A0StP,#0x8
.*: 83880001 ADDT A1LbP,CPC1,#0
.*: 830b0660 ADD A1LbP,A1LbP,#0x60cc
.*: abfffe94 CALLR D1RtP,198 <app_func2@plt>
.*: a70c018d GETD D0Ar6,\[A1LbP\+#-8180\]
.*: 00000200 ADD D0Re0,D0Re0,D0Ar6
.*: 01000205 MOV D1Re0,A1LbP
.*: 0307fff9 ADDT D1Re0,D1Re0,#0xffff
.*: 0306ffc0 ADD D1Re0,D1Re0,#0xdff8
.*: a70ffe64 GETD A1LbP,\[A0StP\+#-16\]
.*: c72041e3 GETL D0FrT,D1RtP,\[A0FrP\+\+\]
.*: 8e004226 SUB A0StP,A0FrP,#0x8
.*: 80081805 MOV A0FrP,D0FrT
.*: a32008a0 MOV PC,D1RtP

8
ld/testsuite/ld-metag/stub.d
View File

@ -5,10 +5,10 @@ start address 0x.*
Disassembly of section .text:
.* <__start-0x8>:
.*: 05 81 18 82 MOVT A0.3,#0x1020
.*: 03 83 1a ac JUMP A0.3,#0x5060
.*: 82188105 MOVT A0.3,#0x1020
.*: ac1a8303 JUMP A0.3,#0x5060
.* <__start>:
.*: d4 ff ff ab CALLR D1RtP,.* <__start-0x8>
.*: abffffd4 CALLR D1RtP,.* <__start-0x8>
\.\.\.
.* <_far>:
.*: fe ff ff a0 NOP
.*: a0fffffe NOP

38
ld/testsuite/ld-metag/stub_pic_app.d
View File

@ -6,29 +6,29 @@ start address 0x.*
Disassembly of section .plt:
.* <.*>:
.*: 05 81 00 02 MOVT D0Re0,#0x1020
.*: 20 97 04 02 ADD D0Re0,D0Re0,#0x92e4
.*: e3 01 00 b7 SETL \[A0StP\+\+\],D0Re0,D1Re0
.*: 2a 01 00 c6 GETD PC,\[D0Re0\+#4\]
.*: fe ff ff a0 NOP
.*: 02008105 MOVT D0Re0,#0x1020
.*: 02049720 ADD D0Re0,D0Re0,#0x92e4
.*: b70001e3 SETL \[A0StP\+\+\],D0Re0,D1Re0
.*: c600012a GETD PC,\[D0Re0\+#4\]
.*: a0fffffe NOP
.* <_lib_func@plt>:
.*: 05 81 10 82 MOVT A0.2,#0x1020
.*: e0 96 14 82 ADD A0.2,A0.2,#0x92dc
.*: 6a 80 00 c6 GETD PC,\[A0.2\]
.*: 04 00 00 03 MOV D1Re0,#0
.*: e0 fe ff a0 B .* <_lib_func@plt-0x14>
.*: 82108105 MOVT A0.2,#0x1020
.*: 821496e0 ADD A0.2,A0.2,#0x92dc
.*: c600806a GETD PC,\[A0.2\]
.*: 03000004 MOV D1Re0,#0
.*: a0fffee0 B .* <_lib_func@plt-0x14>
Disassembly of section .text:
.* <__start-0x10>:
.*: 05 81 18 82 MOVT A0.3,#0x1020
.*: a3 91 1a ac JUMP A0.3,#0x5234
.*: 05 81 18 82 MOVT A0.3,#0x1020
.*: 83 91 1a ac JUMP A0.3,#0x5230
.*: 82188105 MOVT A0.3,#0x1020
.*: ac1a91a3 JUMP A0.3,#0x5234
.*: 82188105 MOVT A0.3,#0x1020
.*: ac1a9183 JUMP A0.3,#0x5230
.* <__start>:
.*: 94 ff ff ab CALLR D1RtP,.* <_lib_func@plt\+0x14>
.*: d4 fe ff ab CALLR D1RtP,.* <_lib_func@plt>
.*: 94 ff ff ab CALLR D1RtP,.* <_lib_func@plt\+0x1c>
.*: abffff94 CALLR D1RtP,.* <_lib_func@plt\+0x14>
.*: abfffed4 CALLR D1RtP,.* <_lib_func@plt>
.*: abffff94 CALLR D1RtP,.* <_lib_func@plt\+0x1c>
\.\.\.
.* <_far2>:
.*: fe ff ff a0 NOP
.*: a0fffffe NOP
.* <_far>:
.*: f4 ff ff ab CALLR D1RtP,.* <_far2>
.*: abfffff4 CALLR D1RtP,.* <_far2>

38
ld/testsuite/ld-metag/stub_pic_shared.d
View File

@ -6,30 +6,30 @@ start address 0x.*
Disassembly of section .plt:
.* <.*>:
.*: 01 01 90 82 ADDT A0.2,CPC0,#0x20
.*: 60 06 12 82 ADD A0.2,A0.2,#0x40cc
.*: 20 0c 10 a3 MOV D0Re0,A0.2
.*: e3 01 00 b7 SETL \[A0StP\+\+\],D0Re0,D1Re0
.*: 2a 01 00 c6 GETD PC,\[D0Re0\+#4\]
.*: 82900101 ADDT A0.2,CPC0,#0x20
.*: 82120660 ADD A0.2,A0.2,#0x40cc
.*: a3100c20 MOV D0Re0,A0.2
.*: b70001e3 SETL \[A0StP\+\+\],D0Re0,D1Re0
.*: c600012a GETD PC,\[D0Re0\+#4\]
.* <_far2@plt>:
.*: 01 01 90 82 ADDT A0.2,CPC0,#0x20
.*: 80 05 12 82 ADD A0.2,A0.2,#0x40b0
.*: 6a 80 00 c6 GETD PC,\[A0.2\]
.*: 04 00 00 03 MOV D1Re0,#0
.*: e0 fe ff a0 B .* <_far2@plt-0x14>
.*: 82900101 ADDT A0.2,CPC0,#0x20
.*: 82120580 ADD A0.2,A0.2,#0x40b0
.*: c600806a GETD PC,\[A0.2\]
.*: 03000004 MOV D1Re0,#0
.*: a0fffee0 B .* <_far2@plt-0x14>
Disassembly of section .text:
.* <__start-0xc>:
.*: 01 01 98 82 ADDT A0.3,CPC0,#0x20
.*: 00 01 18 82 ADD A0.3,A0.3,#0x20
.*: a0 0c 18 a3 MOV PC,A0.3
.*: 82980101 ADDT A0.3,CPC0,#0x20
.*: 82180100 ADD A0.3,A0.3,#0x20
.*: a3180ca0 MOV PC,A0.3
.* <__start>:
.*: b4 ff ff ab CALLR D1RtP,.* <_far2@plt\+0x14>
.*: abffffb4 CALLR D1RtP,.* <_far2@plt\+0x14>
\.\.\.
.* <pad_end>:
.*: f9 fe 9f 82 ADDT A0.3,CPC0,#0xffdf
.*: e0 fe 1f 82 ADD A0.3,A0.3,#0xffdc
.*: a0 0c 18 a3 MOV PC,A0.3
.*: 829ffef9 ADDT A0.3,CPC0,#0xffdf
.*: 821ffee0 ADD A0.3,A0.3,#0xffdc
.*: a3180ca0 MOV PC,A0.3
.* <_far2>:
.*: fe ff ff a0 NOP
.*: a0fffffe NOP
.* <_far>:
.*: 94 ff ff ab CALLR D1RtP,.* <pad_end>
.*: abffff94 CALLR D1RtP,.* <pad_end>

46
ld/testsuite/ld-metag/stub_shared.d
View File

@ -7,30 +7,30 @@ start address 0x.*
Disassembly of section .plt:
.* <.*>:
.*: 01 00 90 82 ADDT A0.2,CPC0,#0
.*: 00 07 12 82 ADD A0.2,A0.2,#0x40e0
.*: 20 0c 10 a3 MOV D0Re0,A0.2
.*: e3 01 00 b7 SETL \[A0StP\+\+\],D0Re0,D1Re0
.*: 2a 01 00 c6 GETD PC,\[D0Re0\+#4\]
.*: 82900001 ADDT A0.2,CPC0,#0
.*: 82120700 ADD A0.2,A0.2,#0x40e0
.*: a3100c20 MOV D0Re0,A0.2
.*: b70001e3 SETL \[A0StP\+\+\],D0Re0,D1Re0
.*: c600012a GETD PC,\[D0Re0\+#4\]
.* <_far2@plt>:
.*: 01 00 90 82 ADDT A0.2,CPC0,#0
.*: 20 06 12 82 ADD A0.2,A0.2,#0x40c4
.*: 6a 80 00 c6 GETD PC,\[A0.2\]
.*: 04 00 00 03 MOV D1Re0,#0
.*: e0 fe ff a0 B .* <_far2@plt-0x14>
.*: 82900001 ADDT A0.2,CPC0,#0
.*: 82120620 ADD A0.2,A0.2,#0x40c4
.*: c600806a GETD PC,\[A0.2\]
.*: 03000004 MOV D1Re0,#0
.*: a0fffee0 B .* <_far2@plt-0x14>
Disassembly of section .text:
.* <_lib_func>:
.*: 05 32 20 00 MOV D0FrT,A0FrP
.*: 26 00 08 86 ADD A0FrP,A0StP,#0
.*: e3 01 20 b7 SETL \[A0StP\+\+\],D0FrT,D1RtP
.*: e9 02 08 b6 SETD \[A0StP\+#8\+\+\],A1LbP
.*: 40 00 00 82 ADD A0StP,A0StP,#0x8
.*: 01 00 88 83 ADDT A1LbP,CPC1,#0
.*: 00 05 0b 83 ADD A1LbP,A1LbP,#0x60a0
.*: 94 fe ff ab CALLR D1RtP,.* <_far2@plt>
.*: 64 fe 0f a7 GETD A1LbP,\[A0StP\+#-16\]
.*: e3 41 20 c7 GETL D0FrT,D1RtP,\[A0FrP\+\+\]
.*: 26 42 00 8e SUB A0StP,A0FrP,#0x8
.*: 05 18 08 80 MOV A0FrP,D0FrT
.*: a0 08 20 a3 MOV PC,D1RtP
.*: 00203205 MOV D0FrT,A0FrP
.*: 86080026 ADD A0FrP,A0StP,#0
.*: b72001e3 SETL \[A0StP\+\+\],D0FrT,D1RtP
.*: b60802e9 SETD \[A0StP\+#8\+\+\],A1LbP
.*: 82000040 ADD A0StP,A0StP,#0x8
.*: 83880001 ADDT A1LbP,CPC1,#0
.*: 830b0500 ADD A1LbP,A1LbP,#0x60a0
.*: abfffe94 CALLR D1RtP,.* <_far2@plt>
.*: a70ffe64 GETD A1LbP,\[A0StP\+#-16\]
.*: c72041e3 GETL D0FrT,D1RtP,\[A0FrP\+\+\]
.*: 8e004226 SUB A0StP,A0FrP,#0x8
.*: 80081805 MOV A0FrP,D0FrT
.*: a32008a0 MOV PC,D1RtP

6
opcodes/ChangeLog
View File

@ -1,3 +1,9 @@
2013-02-15 Markos Chandras <markos.chandras@imgtec.com>
* metag-dis.c: Initialize outf->bytes_per_chunk to 4
which also makes the disassembler output be in little
endian like it should be.
2013-02-14 Yufeng Zhang <yufeng.zhang@arm.com>
* aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'

1
opcodes/metag-dis.c
View File

@ -3360,6 +3360,7 @@ print_insn_metag (bfd_vma pc, disassemble_info *outf)
bfd_byte buf[4];
unsigned int insn_word;
size_t i;
outf->bytes_per_chunk = 4;
(*outf->read_memory_func) (pc & ~0x03, buf, 4, outf);
insn_word = bfd_getl32 (buf);

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