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@ -2,7 +2,7 @@ |
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THIS FILE IS MACHINE GENERATED WITH CGEN. |
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Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc. |
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Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. |
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This file is part of the GNU Binutils and/or GDB, the GNU debugger. |
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@ -346,6 +346,21 @@ const CGEN_IFLD fr30_cgen_ifld_table[] = |
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#undef A |
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/* multi ifield declarations */ |
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const CGEN_MAYBE_MULTI_IFLD FR30_F_I20_MULTI_IFIELD []; |
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/* multi ifield definitions */ |
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const CGEN_MAYBE_MULTI_IFLD FR30_F_I20_MULTI_IFIELD [] = |
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{ |
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{ 0, &(fr30_cgen_ifld_table[23]) }, |
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{ 0, &(fr30_cgen_ifld_table[24]) }, |
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{0,0} |
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}; |
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/* The operand table. */ |
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#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) |
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@ -363,150 +378,199 @@ const CGEN_OPERAND fr30_cgen_operand_table[] = |
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{ |
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/* pc: program counter */ |
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{ "pc", FR30_OPERAND_PC, HW_H_PC, 0, 0, |
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{ 0, &(fr30_cgen_ifld_table[0]) }, |
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{ 0|A(SEM_ONLY), { (1<<MACH_BASE) } } }, |
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/* Ri: destination register */ |
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{ "Ri", FR30_OPERAND_RI, HW_H_GR, 12, 4, |
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{ 0, &(fr30_cgen_ifld_table[10]) }, |
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{ 0, { (1<<MACH_BASE) } } }, |
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/* Rj: source register */ |
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{ "Rj", FR30_OPERAND_RJ, HW_H_GR, 8, 4, |
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{ 0, &(fr30_cgen_ifld_table[9]) }, |
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{ 0, { (1<<MACH_BASE) } } }, |
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/* Ric: target register coproc insn */ |
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{ "Ric", FR30_OPERAND_RIC, HW_H_GR, 12, 4, |
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{ 0, &(fr30_cgen_ifld_table[14]) }, |
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{ 0, { (1<<MACH_BASE) } } }, |
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/* Rjc: source register coproc insn */ |
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{ "Rjc", FR30_OPERAND_RJC, HW_H_GR, 8, 4, |
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{ 0, &(fr30_cgen_ifld_table[13]) }, |
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{ 0, { (1<<MACH_BASE) } } }, |
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/* CRi: coprocessor register */ |
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{ "CRi", FR30_OPERAND_CRI, HW_H_CR, 12, 4, |
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{ 0, &(fr30_cgen_ifld_table[16]) }, |
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{ 0, { (1<<MACH_BASE) } } }, |
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/* CRj: coprocessor register */ |
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{ "CRj", FR30_OPERAND_CRJ, HW_H_CR, 8, 4, |
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{ 0, &(fr30_cgen_ifld_table[15]) }, |
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{ 0, { (1<<MACH_BASE) } } }, |
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/* Rs1: dedicated register */ |
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{ "Rs1", FR30_OPERAND_RS1, HW_H_DR, 8, 4, |
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{ 0, &(fr30_cgen_ifld_table[11]) }, |
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{ 0, { (1<<MACH_BASE) } } }, |
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/* Rs2: dedicated register */ |
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{ "Rs2", FR30_OPERAND_RS2, HW_H_DR, 12, 4, |
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{ 0, &(fr30_cgen_ifld_table[12]) }, |
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{ 0, { (1<<MACH_BASE) } } }, |
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/* R13: General Register 13 */ |
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{ "R13", FR30_OPERAND_R13, HW_H_R13, 0, 0, |
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{ 0, 0 }, |
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{ 0, { (1<<MACH_BASE) } } }, |
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/* R14: General Register 14 */ |
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{ "R14", FR30_OPERAND_R14, HW_H_R14, 0, 0, |
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{ 0, 0 }, |
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{ 0, { (1<<MACH_BASE) } } }, |
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/* R15: General Register 15 */ |
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{ "R15", FR30_OPERAND_R15, HW_H_R15, 0, 0, |
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{ 0, 0 }, |
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{ 0, { (1<<MACH_BASE) } } }, |
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/* ps: Program Status register */ |
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{ "ps", FR30_OPERAND_PS, HW_H_PS, 0, 0, |
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{ 0, 0 }, |
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{ 0, { (1<<MACH_BASE) } } }, |
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/* u4: 4 bit unsigned immediate */ |
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{ "u4", FR30_OPERAND_U4, HW_H_UINT, 8, 4, |
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{ 0, &(fr30_cgen_ifld_table[17]) }, |
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{ 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } }, |
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/* u4c: 4 bit unsigned immediate */ |
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{ "u4c", FR30_OPERAND_U4C, HW_H_UINT, 12, 4, |
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{ 0, &(fr30_cgen_ifld_table[18]) }, |
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{ 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } }, |
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/* u8: 8 bit unsigned immediate */ |
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{ "u8", FR30_OPERAND_U8, HW_H_UINT, 8, 8, |
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{ 0, &(fr30_cgen_ifld_table[21]) }, |
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{ 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } }, |
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/* i8: 8 bit unsigned immediate */ |
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{ "i8", FR30_OPERAND_I8, HW_H_UINT, 4, 8, |
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{ 0, &(fr30_cgen_ifld_table[22]) }, |
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{ 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } }, |
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/* udisp6: 6 bit unsigned immediate */ |
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{ "udisp6", FR30_OPERAND_UDISP6, HW_H_UINT, 8, 4, |
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{ 0, &(fr30_cgen_ifld_table[26]) }, |
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{ 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } }, |
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/* disp8: 8 bit signed immediate */ |
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{ "disp8", FR30_OPERAND_DISP8, HW_H_SINT, 4, 8, |
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{ 0, &(fr30_cgen_ifld_table[27]) }, |
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{ 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } }, |
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/* disp9: 9 bit signed immediate */ |
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{ "disp9", FR30_OPERAND_DISP9, HW_H_SINT, 4, 8, |
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{ 0, &(fr30_cgen_ifld_table[28]) }, |
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{ 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } }, |
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/* disp10: 10 bit signed immediate */ |
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{ "disp10", FR30_OPERAND_DISP10, HW_H_SINT, 4, 8, |
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{ 0, &(fr30_cgen_ifld_table[29]) }, |
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{ 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } }, |
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/* s10: 10 bit signed immediate */ |
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{ "s10", FR30_OPERAND_S10, HW_H_SINT, 8, 8, |
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{ 0, &(fr30_cgen_ifld_table[30]) }, |
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{ 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } }, |
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/* u10: 10 bit unsigned immediate */ |
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{ "u10", FR30_OPERAND_U10, HW_H_UINT, 8, 8, |
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{ 0, &(fr30_cgen_ifld_table[31]) }, |
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{ 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } }, |
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/* i32: 32 bit immediate */ |
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{ "i32", FR30_OPERAND_I32, HW_H_UINT, 0, 32, |
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{ 0, &(fr30_cgen_ifld_table[25]) }, |
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{ 0|A(HASH_PREFIX)|A(SIGN_OPT), { (1<<MACH_BASE) } } }, |
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/* m4: 4 bit negative immediate */ |
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{ "m4", FR30_OPERAND_M4, HW_H_SINT, 8, 4, |
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{ 0, &(fr30_cgen_ifld_table[20]) }, |
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{ 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } }, |
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/* i20: 20 bit immediate */ |
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{ "i20", FR30_OPERAND_I20, HW_H_UINT, 0, 20, |
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{ 2, &(FR30_F_I20_MULTI_IFIELD[0]) }, |
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{ 0|A(HASH_PREFIX)|A(VIRTUAL), { (1<<MACH_BASE) } } }, |
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/* dir8: 8 bit direct address */ |
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{ "dir8", FR30_OPERAND_DIR8, HW_H_UINT, 8, 8, |
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{ 0, &(fr30_cgen_ifld_table[33]) }, |
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{ 0, { (1<<MACH_BASE) } } }, |
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/* dir9: 9 bit direct address */ |
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{ "dir9", FR30_OPERAND_DIR9, HW_H_UINT, 8, 8, |
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{ 0, &(fr30_cgen_ifld_table[34]) }, |
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{ 0, { (1<<MACH_BASE) } } }, |
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/* dir10: 10 bit direct address */ |
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{ "dir10", FR30_OPERAND_DIR10, HW_H_UINT, 8, 8, |
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{ 0, &(fr30_cgen_ifld_table[35]) }, |
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{ 0, { (1<<MACH_BASE) } } }, |
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/* label9: 9 bit pc relative address */ |
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{ "label9", FR30_OPERAND_LABEL9, HW_H_IADDR, 8, 8, |
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{ 0, &(fr30_cgen_ifld_table[32]) }, |
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{ 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } }, |
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/* label12: 12 bit pc relative address */ |
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{ "label12", FR30_OPERAND_LABEL12, HW_H_IADDR, 5, 11, |
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{ 0, &(fr30_cgen_ifld_table[36]) }, |
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{ 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } }, |
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/* reglist_low_ld: 8 bit low register mask for ldm */ |
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{ "reglist_low_ld", FR30_OPERAND_REGLIST_LOW_LD, HW_H_UINT, 8, 8, |
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{ 0, &(fr30_cgen_ifld_table[40]) }, |
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{ 0, { (1<<MACH_BASE) } } }, |
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/* reglist_hi_ld: 8 bit high register mask for ldm */ |
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{ "reglist_hi_ld", FR30_OPERAND_REGLIST_HI_LD, HW_H_UINT, 8, 8, |
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{ 0, &(fr30_cgen_ifld_table[39]) }, |
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{ 0, { (1<<MACH_BASE) } } }, |
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/* reglist_low_st: 8 bit low register mask for stm */ |
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{ "reglist_low_st", FR30_OPERAND_REGLIST_LOW_ST, HW_H_UINT, 8, 8, |
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{ 0, &(fr30_cgen_ifld_table[38]) }, |
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{ 0, { (1<<MACH_BASE) } } }, |
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/* reglist_hi_st: 8 bit high register mask for stm */ |
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{ "reglist_hi_st", FR30_OPERAND_REGLIST_HI_ST, HW_H_UINT, 8, 8, |
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{ 0, &(fr30_cgen_ifld_table[37]) }, |
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{ 0, { (1<<MACH_BASE) } } }, |
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/* cc: condition codes */ |
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{ "cc", FR30_OPERAND_CC, HW_H_UINT, 4, 4, |
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{ 0, &(fr30_cgen_ifld_table[7]) }, |
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{ 0, { (1<<MACH_BASE) } } }, |
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/* ccc: coprocessor calc */ |
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{ "ccc", FR30_OPERAND_CCC, HW_H_UINT, 0, 8, |
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{ 0, &(fr30_cgen_ifld_table[8]) }, |
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{ 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } }, |
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/* nbit: negative bit */ |
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{ "nbit", FR30_OPERAND_NBIT, HW_H_NBIT, 0, 0, |
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{ 0, 0 }, |
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{ 0|A(SEM_ONLY), { (1<<MACH_BASE) } } }, |
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/* vbit: overflow bit */ |
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{ "vbit", FR30_OPERAND_VBIT, HW_H_VBIT, 0, 0, |
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{ 0, 0 }, |
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{ 0|A(SEM_ONLY), { (1<<MACH_BASE) } } }, |
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/* zbit: zero bit */ |
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{ "zbit", FR30_OPERAND_ZBIT, HW_H_ZBIT, 0, 0, |
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{ 0, 0 }, |
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{ 0|A(SEM_ONLY), { (1<<MACH_BASE) } } }, |
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/* cbit: carry bit */ |
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{ "cbit", FR30_OPERAND_CBIT, HW_H_CBIT, 0, 0, |
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{ 0, 0 }, |
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{ 0|A(SEM_ONLY), { (1<<MACH_BASE) } } }, |
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/* ibit: interrupt bit */ |
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{ "ibit", FR30_OPERAND_IBIT, HW_H_IBIT, 0, 0, |
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{ 0, 0 }, |
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{ 0|A(SEM_ONLY), { (1<<MACH_BASE) } } }, |
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/* sbit: stack bit */ |
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{ "sbit", FR30_OPERAND_SBIT, HW_H_SBIT, 0, 0, |
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{ 0, 0 }, |
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{ 0|A(SEM_ONLY), { (1<<MACH_BASE) } } }, |
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/* tbit: trace trap bit */ |
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{ "tbit", FR30_OPERAND_TBIT, HW_H_TBIT, 0, 0, |
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{ 0, 0 }, |
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{ 0|A(SEM_ONLY), { (1<<MACH_BASE) } } }, |
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/* d0bit: division 0 bit */ |
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{ "d0bit", FR30_OPERAND_D0BIT, HW_H_D0BIT, 0, 0, |
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{ 0, 0 }, |
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{ 0|A(SEM_ONLY), { (1<<MACH_BASE) } } }, |
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/* d1bit: division 1 bit */ |
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{ "d1bit", FR30_OPERAND_D1BIT, HW_H_D1BIT, 0, 0, |
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{ 0, 0 }, |
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{ 0|A(SEM_ONLY), { (1<<MACH_BASE) } } }, |
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/* ccr: condition code bits */ |
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{ "ccr", FR30_OPERAND_CCR, HW_H_CCR, 0, 0, |
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{ 0, 0 }, |
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{ 0|A(SEM_ONLY), { (1<<MACH_BASE) } } }, |
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/* scr: system condition bits */ |
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{ "scr", FR30_OPERAND_SCR, HW_H_SCR, 0, 0, |
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{ 0, 0 }, |
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{ 0|A(SEM_ONLY), { (1<<MACH_BASE) } } }, |
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/* ilm: interrupt level mask */ |
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{ "ilm", FR30_OPERAND_ILM, HW_H_ILM, 0, 0, |
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{ 0, 0 }, |
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{ 0|A(SEM_ONLY), { (1<<MACH_BASE) } } }, |
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{ 0, 0, 0, 0, 0, {0, {0}} } |
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}; |
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@ -1501,8 +1565,8 @@ fr30_cgen_rebuild_tables (cd) |
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{ |
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const CGEN_ISA *isa = & fr30_cgen_isa_table[i]; |
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/* Default insn sizes of all selected isas must be equal or we set
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the result to 0, meaning "unknown". */ |
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/* Default insn sizes of all selected isas must be
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equal or we set the result to 0, meaning "unknown". */ |
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if (cd->default_insn_bitsize == UNSET) |
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cd->default_insn_bitsize = isa->default_insn_bitsize; |
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else if (isa->default_insn_bitsize == cd->default_insn_bitsize) |
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@ -1510,8 +1574,8 @@ fr30_cgen_rebuild_tables (cd) |
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else |
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cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN; |
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/* Base insn sizes of all selected isas must be equal or we set
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the result to 0, meaning "unknown". */ |
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/* Base insn sizes of all selected isas must be equal
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or we set the result to 0, meaning "unknown". */ |
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if (cd->base_insn_bitsize == UNSET) |
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cd->base_insn_bitsize = isa->base_insn_bitsize; |
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else if (isa->base_insn_bitsize == cd->base_insn_bitsize) |
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Graydon Hoare
25 years ago