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@ -3491,6 +3491,55 @@ parse_cond (char **str) |
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return c->value; |
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} |
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/* Parse the operands of a table branch instruction. Similar to a memory
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operand. */ |
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static int |
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parse_tb (char **str) |
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{ |
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char * p = *str; |
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int reg; |
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if (skip_past_char (&p, '[') == FAIL) |
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return FAIL; |
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if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL) |
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{ |
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inst.error = _(reg_expected_msgs[REG_TYPE_RN]); |
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return FAIL; |
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} |
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inst.operands[0].reg = reg; |
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if (skip_past_comma (&p) == FAIL) |
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return FAIL; |
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if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL) |
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{ |
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inst.error = _(reg_expected_msgs[REG_TYPE_RN]); |
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return FAIL; |
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} |
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inst.operands[0].imm = reg; |
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if (skip_past_comma (&p) == SUCCESS) |
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{ |
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if (parse_shift (&p, 0, SHIFT_LSL_IMMEDIATE) == FAIL) |
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return FAIL; |
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if (inst.reloc.exp.X_add_number != 1) |
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{ |
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inst.error = _("invalid shift"); |
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return FAIL; |
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} |
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inst.operands[0].shifted = 1; |
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} |
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if (skip_past_char (&p, ']') == FAIL) |
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{ |
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inst.error = _("']' expected"); |
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return FAIL; |
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} |
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*str = p; |
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return SUCCESS; |
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} |
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/* Matcher codes for parse_operands. */ |
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enum operand_parse_code |
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{ |
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@ -3546,6 +3595,7 @@ enum operand_parse_code |
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OP_ENDI, /* Endianness specifier */ |
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OP_PSR, /* CPSR/SPSR mask for msr */ |
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OP_COND, /* conditional code */ |
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OP_TB, /* Table branch. */ |
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OP_RRnpc_I0, /* ARM register or literal 0 */ |
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OP_RR_EXr, /* ARM register or expression with opt. reloc suff. */ |
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@ -3787,6 +3837,10 @@ parse_operands (char *str, const unsigned char *pattern) |
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case OP_PSR: val = parse_psr (&str); break; |
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case OP_COND: val = parse_cond (&str); break; |
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case OP_TB: |
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po_misc_or_fail (parse_tb (&str)); |
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break; |
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/* Register lists */ |
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case OP_REGLST: |
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val = parse_reg_list (&str); |
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@ -5774,6 +5828,20 @@ static const unsigned int thumb_op32[] = { T16_32_TAB }; |
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/* Thumb instruction encoders, in alphabetical order. */ |
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/* ADDW or SUBW. */ |
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static void |
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do_t_add_sub_w (void) |
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{ |
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int Rd, Rn; |
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Rd = inst.operands[0].reg; |
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Rn = inst.operands[1].reg; |
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constraint (Rd == 15, _("PC not allowed as destination")); |
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inst.instruction |= (Rn << 16) | (Rd << 8); |
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inst.reloc.type = BFD_RELOC_ARM_T32_IMM12; |
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} |
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/* Parse an add or subtract instruction. We get here with inst.instruction
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equalling any of THUMB_OPCODE_add, adds, sub, or subs. */ |
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@ -7223,6 +7291,21 @@ do_t_swi (void) |
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inst.reloc.type = BFD_RELOC_ARM_SWI; |
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} |
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static void |
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do_t_tb (void) |
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{ |
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int half; |
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half = (inst.instruction & 0x10) != 0; |
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constraint (inst.operands[0].imm == 15, |
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_("PC is not a valid index register")); |
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constraint (!half && inst.operands[0].shifted, |
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_("instruction does not allow shifted index")); |
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constraint (half && !inst.operands[0].shifted, |
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_("instruction requires shifted index")); |
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inst.instruction |= (inst.operands[0].reg << 16) | inst.operands[0].imm; |
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} |
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static void |
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do_t_usat (void) |
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{ |
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@ -8464,6 +8547,15 @@ static const struct asm_opcode insns[] = |
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TUE(ittee, 0, bf09, 1, (COND), it, t_it), |
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TUE(iteee, 0, bf01, 1, (COND), it, t_it), |
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/* Thumb2 only instructions. */ |
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#undef ARM_VARIANT |
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#define ARM_VARIANT 0 |
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TCE(addw, 0, f2000000, 3, (RR, RR, EXPi), 0, t_add_sub_w), |
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TCE(subw, 0, f2a00000, 3, (RR, RR, EXPi), 0, t_add_sub_w), |
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TCE(tbb, 0, e8d0f000, 1, (TB), 0, t_tb), |
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TCE(tbh, 0, e8d0f010, 1, (TB), 0, t_tb), |
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#undef ARM_VARIANT |
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#define ARM_VARIANT FPU_FPA_EXT_V1 /* Core FPA instruction set (V1). */ |
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CE(wfs, e200110, 1, (RR), rd), |
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@ -10439,6 +10531,7 @@ md_apply_fix (fixS * fixP, |
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break; |
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case BFD_RELOC_ARM_T32_IMMEDIATE: |
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case BFD_RELOC_ARM_T32_IMM12: |
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/* We claim that this fixup has been processed here,
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even if in fact we generate an error because we do |
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not have a reloc for it, so tc_gen_reloc will reject it. */ |
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@ -10457,7 +10550,15 @@ md_apply_fix (fixS * fixP, |
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newval <<= 16; |
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newval |= md_chars_to_number (buf+2, THUMB_SIZE); |
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newimm = encode_thumb32_immediate (value); |
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if (fixP->fx_r_type == BFD_RELOC_ARM_T32_IMM12) |
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{ |
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if (value > 0xfff) |
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newimm = (unsigned int) FAIL; |
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else |
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newimm = value; |
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} |
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else |
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newimm = encode_thumb32_immediate (value); |
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/* FUTURE: Implement analogue of negate_data_op for T32. */ |
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if (newimm == (unsigned int)FAIL) |
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Paul Brook
21 years ago