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@ -226,6 +226,7 @@ static const arm_feature_set fpu_vfp_ext_d32 = |
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static const arm_feature_set fpu_neon_ext_v1 = ARM_FEATURE (0, FPU_NEON_EXT_V1); |
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static const arm_feature_set fpu_vfp_v3_or_neon_ext = |
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ARM_FEATURE (0, FPU_NEON_EXT_V1 | FPU_VFP_EXT_V3); |
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static const arm_feature_set fpu_neon_fp16 = ARM_FEATURE (0, FPU_NEON_FP16); |
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static int mfloat_abi_opt = -1; |
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/* Record user cpu selection for object attributes. */ |
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@ -10682,36 +10683,37 @@ static struct neon_shape_info neon_shape_tab[] = |
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enum neon_type_mask |
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{ |
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N_S8 = 0x000001, |
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N_S16 = 0x000002, |
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N_S32 = 0x000004, |
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N_S64 = 0x000008, |
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N_U8 = 0x000010, |
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N_U16 = 0x000020, |
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N_U32 = 0x000040, |
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N_U64 = 0x000080, |
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N_I8 = 0x000100, |
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N_I16 = 0x000200, |
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N_I32 = 0x000400, |
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N_I64 = 0x000800, |
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N_8 = 0x001000, |
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N_16 = 0x002000, |
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N_32 = 0x004000, |
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N_64 = 0x008000, |
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N_P8 = 0x010000, |
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N_P16 = 0x020000, |
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N_F32 = 0x040000, |
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N_F64 = 0x080000, |
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N_KEY = 0x100000, /* key element (main type specifier). */ |
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N_EQK = 0x200000, /* given operand has the same type & size as the key. */ |
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N_VFP = 0x400000, /* VFP mode: operand size must match register width. */ |
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N_DBL = 0x000001, /* if N_EQK, this operand is twice the size. */ |
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N_HLF = 0x000002, /* if N_EQK, this operand is half the size. */ |
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N_SGN = 0x000004, /* if N_EQK, this operand is forced to be signed. */ |
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N_UNS = 0x000008, /* if N_EQK, this operand is forced to be unsigned. */ |
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N_INT = 0x000010, /* if N_EQK, this operand is forced to be integer. */ |
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N_FLT = 0x000020, /* if N_EQK, this operand is forced to be float. */ |
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N_SIZ = 0x000040, /* if N_EQK, this operand is forced to be size-only. */ |
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N_S8 = 0x0000001, |
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N_S16 = 0x0000002, |
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N_S32 = 0x0000004, |
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N_S64 = 0x0000008, |
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N_U8 = 0x0000010, |
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N_U16 = 0x0000020, |
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N_U32 = 0x0000040, |
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N_U64 = 0x0000080, |
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N_I8 = 0x0000100, |
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N_I16 = 0x0000200, |
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N_I32 = 0x0000400, |
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N_I64 = 0x0000800, |
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N_8 = 0x0001000, |
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N_16 = 0x0002000, |
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N_32 = 0x0004000, |
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N_64 = 0x0008000, |
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N_P8 = 0x0010000, |
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N_P16 = 0x0020000, |
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N_F16 = 0x0040000, |
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N_F32 = 0x0080000, |
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N_F64 = 0x0100000, |
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N_KEY = 0x1000000, /* key element (main type specifier). */ |
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N_EQK = 0x2000000, /* given operand has the same type & size as the key. */ |
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N_VFP = 0x4000000, /* VFP mode: operand size must match register width. */ |
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N_DBL = 0x0000001, /* if N_EQK, this operand is twice the size. */ |
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N_HLF = 0x0000002, /* if N_EQK, this operand is half the size. */ |
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N_SGN = 0x0000004, /* if N_EQK, this operand is forced to be signed. */ |
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N_UNS = 0x0000008, /* if N_EQK, this operand is forced to be unsigned. */ |
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N_INT = 0x0000010, /* if N_EQK, this operand is forced to be integer. */ |
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N_FLT = 0x0000020, /* if N_EQK, this operand is forced to be float. */ |
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N_SIZ = 0x0000040, /* if N_EQK, this operand is forced to be size-only. */ |
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N_UTYP = 0, |
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N_MAX_NONSPECIAL = N_F64 |
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}; |
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@ -10905,6 +10907,7 @@ type_chk_of_el_type (enum neon_el_type type, unsigned size) |
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case NT_float: |
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switch (size) |
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{ |
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case 16: return N_F16; |
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case 32: return N_F32; |
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case 64: return N_F64; |
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default: ; |
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@ -12598,25 +12601,28 @@ neon_cvt_flavour (enum neon_shape rs) |
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CVT_VAR (1, N_U32, N_F32); |
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CVT_VAR (2, N_F32, N_S32); |
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CVT_VAR (3, N_F32, N_U32); |
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/* Half-precision conversions. */ |
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CVT_VAR (4, N_F32, N_F16); |
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CVT_VAR (5, N_F16, N_F32); |
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whole_reg = N_VFP; |
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/* VFP instructions. */ |
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CVT_VAR (4, N_F32, N_F64); |
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CVT_VAR (5, N_F64, N_F32); |
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CVT_VAR (6, N_S32, N_F64 | key); |
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CVT_VAR (7, N_U32, N_F64 | key); |
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CVT_VAR (8, N_F64 | key, N_S32); |
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CVT_VAR (9, N_F64 | key, N_U32); |
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CVT_VAR (6, N_F32, N_F64); |
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CVT_VAR (7, N_F64, N_F32); |
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CVT_VAR (8, N_S32, N_F64 | key); |
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CVT_VAR (9, N_U32, N_F64 | key); |
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CVT_VAR (10, N_F64 | key, N_S32); |
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CVT_VAR (11, N_F64 | key, N_U32); |
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/* VFP instructions with bitshift. */ |
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CVT_VAR (10, N_F32 | key, N_S16); |
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CVT_VAR (11, N_F32 | key, N_U16); |
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CVT_VAR (12, N_F64 | key, N_S16); |
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CVT_VAR (13, N_F64 | key, N_U16); |
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CVT_VAR (14, N_S16, N_F32 | key); |
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CVT_VAR (15, N_U16, N_F32 | key); |
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CVT_VAR (16, N_S16, N_F64 | key); |
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CVT_VAR (17, N_U16, N_F64 | key); |
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CVT_VAR (12, N_F32 | key, N_S16); |
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CVT_VAR (13, N_F32 | key, N_U16); |
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CVT_VAR (14, N_F64 | key, N_S16); |
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CVT_VAR (15, N_F64 | key, N_U16); |
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CVT_VAR (16, N_S16, N_F32 | key); |
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CVT_VAR (17, N_U16, N_F32 | key); |
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CVT_VAR (18, N_S16, N_F64 | key); |
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CVT_VAR (19, N_U16, N_F64 | key); |
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return -1; |
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#undef CVT_VAR |
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@ -12640,6 +12646,8 @@ do_vfp_nsyn_cvt (enum neon_shape rs, int flavour) |
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"fultos", |
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NULL, |
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NULL, |
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NULL, |
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NULL, |
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"ftosld", |
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"ftould", |
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"fsltod", |
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@ -12672,6 +12680,8 @@ do_vfp_nsyn_cvt (enum neon_shape rs, int flavour) |
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"ftouis", |
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"fsitos", |
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"fuitos", |
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"NULL", |
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"NULL", |
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"fcvtsd", |
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"fcvtds", |
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"ftosid", |
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@ -12701,6 +12711,8 @@ do_vfp_nsyn_cvtz (void) |
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NULL, |
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NULL, |
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NULL, |
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NULL, |
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NULL, |
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"ftosizd", |
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"ftouizd" |
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}; |
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@ -12708,16 +12720,15 @@ do_vfp_nsyn_cvtz (void) |
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if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc) && enc[flavour]) |
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do_vfp_nsyn_opcode (enc[flavour]); |
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} |
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static void |
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do_neon_cvt (void) |
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{ |
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enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_FFI, NS_DD, NS_QQ, |
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NS_FD, NS_DF, NS_FF, NS_NULL); |
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NS_FD, NS_DF, NS_FF, NS_QD, NS_DQ, NS_NULL); |
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int flavour = neon_cvt_flavour (rs); |
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/* VFP rather than Neon conversions. */ |
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if (flavour >= 4) |
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if (flavour >= 6) |
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{ |
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do_vfp_nsyn_cvt (rs, flavour); |
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return; |
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@ -12779,12 +12790,70 @@ do_neon_cvt (void) |
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} |
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break; |
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/* Half-precision conversions for Advanced SIMD -- neon. */ |
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case NS_QD: |
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case NS_DQ: |
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if ((rs == NS_DQ) |
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&& (inst.vectype.el[0].size != 16 || inst.vectype.el[1].size != 32)) |
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{ |
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as_bad (_("operand size must match register width")); |
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break; |
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} |
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if ((rs == NS_QD) |
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&& ((inst.vectype.el[0].size != 32 || inst.vectype.el[1].size != 16))) |
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{ |
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as_bad (_("operand size must match register width")); |
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break; |
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} |
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if (rs == NS_DQ) |
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inst.instruction = 0x3b60600; |
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else |
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inst.instruction = 0x3b60700; |
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inst.instruction |= LOW4 (inst.operands[0].reg) << 12; |
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inst.instruction |= HI1 (inst.operands[0].reg) << 22; |
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inst.instruction |= LOW4 (inst.operands[1].reg); |
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inst.instruction |= HI1 (inst.operands[1].reg) << 5; |
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inst.instruction = neon_dp_fixup (inst.instruction); |
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break; |
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default: |
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/* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */ |
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do_vfp_nsyn_cvt (rs, flavour); |
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} |
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} |
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static void |
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do_neon_cvtb (void) |
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{ |
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inst.instruction = 0xeb20a40; |
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/* The sizes are attached to the mnemonic. */ |
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if (inst.vectype.el[0].type != NT_invtype |
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&& inst.vectype.el[0].size == 16) |
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inst.instruction |= 0x00010000; |
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/* Programmer's syntax: the sizes are attached to the operands. */ |
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else if (inst.operands[0].vectype.type != NT_invtype |
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&& inst.operands[0].vectype.size == 16) |
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inst.instruction |= 0x00010000; |
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encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd); |
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encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm); |
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do_vfp_cond_or_thumb (); |
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} |
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static void |
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do_neon_cvtt (void) |
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{ |
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do_neon_cvtb (); |
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inst.instruction |= 0x80; |
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} |
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static void |
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neon_move_immediate (void) |
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{ |
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@ -15950,6 +16019,9 @@ static const struct asm_opcode insns[] = |
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NCE(vstr, d000b00, 2, (RVSD, ADDRGLDC), neon_ldr_str), |
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nCEF(vcvt, vcvt, 3, (RNSDQ, RNSDQ, oI32b), neon_cvt), |
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nCEF(vcvtb, vcvt, 2, (RVS, RVS), neon_cvtb), |
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nCEF(vcvtt, vcvt, 2, (RVS, RVS), neon_cvtt), |
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/* NOTE: All VMOV encoding is special-cased! */ |
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NCE(vmov, 0, 1, (VMOV), neon_mov), |
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@ -20258,6 +20330,7 @@ static const struct arm_option_cpu_value_table arm_fpus[] = |
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{"arm1136jf-s", FPU_ARCH_VFP_V2}, |
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{"maverick", FPU_ARCH_MAVERICK}, |
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{"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1}, |
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{"neon-fp16", FPU_ARCH_NEON_FP16}, |
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{NULL, ARM_ARCH_NONE} |
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}; |
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@ -20731,9 +20804,11 @@ aeabi_set_public_attributes (void) |
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|| ARM_CPU_HAS_FEATURE (arm_arch_used, arm_cext_iwmmxt)) |
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bfd_elf_add_proc_attr_int (stdoutput, 11, 1); |
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/* Tag_NEON_arch. */ |
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if (ARM_CPU_HAS_FEATURE (thumb_arch_used, fpu_neon_ext_v1) |
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|| ARM_CPU_HAS_FEATURE (arm_arch_used, fpu_neon_ext_v1)) |
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if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_v1)) |
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bfd_elf_add_proc_attr_int (stdoutput, 12, 1); |
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/* Tag_NEON_FP16_arch. */ |
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if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_fp16)) |
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bfd_elf_add_proc_attr_int (stdoutput, 36, 1); |
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} |
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/* Add the default contents for the .ARM.attributes section. */ |
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Catherine Moore
18 years ago