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* sim-main.h: Delete inclusion of config.h, include sim-basics.h

before cgen-types.h.
	* tconfig.in: Guard against multiple inclusion.
	* cpu.h: Delete decls moved to genmloop.sh.
	* cpux.h: Ditto.
gdb-4_18-branch
Doug Evans 28 years ago
parent
commit
8de434bf89
  1. 10
      sim/m32r/ChangeLog
  2. 719
      sim/m32r/cpu.h
  3. 716
      sim/m32r/cpux.h
  4. 46
      sim/m32r/tconfig.in

10
sim/m32r/ChangeLog

@ -1,3 +1,13 @@
Wed Nov 4 23:55:37 1998 Doug Evans <devans@seba.cygnus.com>
* sim-main.h: Delete inclusion of config.h, include sim-basics.h
before cgen-types.h.
* tconfig.in: Guard against multiple inclusion.
* cpu.h: Delete decls moved to genmloop.sh.
start-sanitize-m32rx
* cpux.h: Ditto.
end-sanitize-m32rx
Mon Oct 19 14:13:05 1998 Doug Evans <devans@seba.cygnus.com>
* sim-main.h: #include cpu-opc.h.

719
sim/m32r/cpu.h

File diff suppressed because it is too large

716
sim/m32r/cpux.h

File diff suppressed because it is too large

46
sim/m32r/tconfig.in

@ -1,5 +1,8 @@
/* M32R target configuration file. -*- C -*- */
#ifndef M32R_TCONFIG_H
#define M32R_TCONFIG_H
/* Define this if the simulator can vary the size of memory.
See the xxx simulator for an example.
This enables the `-m size' option.
@ -7,29 +10,38 @@
/* Not used for M32R since we use the memory module. */
/* #define SIM_HAVE_MEM_SIZE */
/* See sim-hload.c. We properly handle LMA. */
#define SIM_HANDLES_LMA 1
/* For MSPR support. FIXME: revisit. */
#define WITH_DEVICES 1
/* The semantic code should probably always use a switch().
However, in case that's not possible in some circumstance, we allow
the target to choose. Perhaps this can be autoconf'd on whether the
switch is too big? I can't (yet) think of a reason for allowing the
user to choose, though the developer may certainly wish to. */
#ifdef WANT_CPU_M32R
#define WITH_FAST 1
#define WITH_SEM_SWITCH_FULL 0
#define WITH_SEM_SWITCH_FAST 1
/* FIXME: Revisit. */
#ifdef HAVE_DV_SOCKSER
MODULE_INSTALL_FN dv_sockser_install;
#define MODULE_LIST dv_sockser_install,
#endif
#ifdef WANT_CPU_M32RX
#define HAVE_PARALLEL_EXEC
#define WITH_FAST 0
#define WITH_SEM_SWITCH_FULL 1
#define WITH_SEM_SWITCH_FAST 0
/* The m32rx currently never uses the scache. So hardcode this off. */
#undef WITH_SCACHE
#define WITH_SCACHE 0
#if 0
/* Enable watchpoints. */
#define WITH_WATCHPOINTS 1
#endif
/* ??? Temporary hack until model support unified. */
#define SIM_HAVE_MODEL
/* Define this to enable the intrinsic breakpoint mechanism. */
/* FIXME: may be able to remove SIM_HAVE_BREAKPOINT since it essentially
duplicates ifdef SIM_BREAKPOINT (right?) */
#if 0
#define SIM_HAVE_BREAKPOINTS
#define SIM_BREAKPOINT { 0x10, 0xf1 }
#define SIM_BREAKPOINT_SIZE 2
#endif
/* This is a global setting. Different cpu families can't mix-n-match -scache
and -bb. However some cpu families may use -simple while others use
one of -scache/-bb. */
#define WITH_SCACHE_PBB 1
#endif /* M32R_TCONFIG_H */

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