Michael Meissner
31 years ago
7 changed files with 978 additions and 32 deletions
@ -0,0 +1,904 @@ |
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/* This file is part of the program psim.
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Copyright (C) 1994-1995, Andrew Cagney <cagney@highland.com.au> |
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This program is free software; you can redistribute it and/or modify |
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it under the terms of the GNU General Public License as published by |
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the Free Software Foundation; either version 2 of the License, or |
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(at your option) any later version. |
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This program is distributed in the hope that it will be useful, |
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but WITHOUT ANY WARRANTY; without even the implied warranty of |
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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GNU General Public License for more details. |
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You should have received a copy of the GNU General Public License |
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along with this program; if not, write to the Free Software |
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Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. |
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*/ |
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#ifndef _PSIM_C_ |
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#define _PSIM_C_ |
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#include "config.h" |
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#include "ppc-config.h" |
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#include "inline.h" |
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#ifndef STATIC_INLINE_PSIM |
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#define STATIC_INLINE_PSIM STATIC_INLINE |
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#endif |
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#include <string.h> |
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#include <setjmp.h> |
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#include "cpu.h" /* includes psim.h */ |
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#include "idecode.h" |
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#include "inline.c" |
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/* system structure, actual size of processor array determined at
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runtime */ |
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struct _psim { |
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event_queue *events; |
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device_node *devices; |
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core *memory; |
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/* escape routine for inner functions */ |
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void *path_to_halt; |
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void *path_to_restart; |
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/* status from last halt */ |
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psim_status halt_status; |
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/* the processes proper */ |
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int nr_cpus; |
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int last_cpu; /* CPU that last (tried to) execute an instruction */ |
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cpu *processors[0]; |
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}; |
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int current_target_byte_order; |
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int current_host_byte_order; |
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int current_environment; |
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int current_alignment; |
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INLINE_PSIM psim * |
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psim_create(const char *file_name, |
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int nr_processors) |
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{ |
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int cpu_nr; |
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psim *system; |
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/* sanity check */ |
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if (nr_processors <= 0 |
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|| (!WITH_SMP && nr_processors != 1)) |
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error("psim_create() invalid number of cpus\n"); |
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/* create things */ |
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system = (psim*)zalloc(sizeof(psim) |
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+ sizeof(cpu*) * (nr_processors + 1)); |
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system->nr_cpus = nr_processors; |
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system->events = event_queue_create(); |
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system->devices = device_tree_create(file_name); |
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system->memory = core_create(system->devices, 0); |
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for (cpu_nr = 0; cpu_nr < nr_processors; cpu_nr++) { |
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system->processors[cpu_nr] = cpu_create(system, |
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system->memory, |
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system->events, |
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cpu_nr); |
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} |
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/* fill in the missing endian information */ |
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current_target_byte_order |
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= (device_tree_find_boolean(system->devices, "/options/little-endian?") |
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? LITTLE_ENDIAN |
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: BIG_ENDIAN); |
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if (WITH_TARGET_BYTE_ORDER |
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&& WITH_TARGET_BYTE_ORDER != current_target_byte_order) |
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error("target byte order conflict\n"); |
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current_host_byte_order = 1; |
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current_host_byte_order = (*(char*)(¤t_host_byte_order) |
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? LITTLE_ENDIAN |
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: BIG_ENDIAN); |
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if (WITH_HOST_BYTE_ORDER |
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&& WITH_HOST_BYTE_ORDER != current_host_byte_order) |
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error("host byte order conflict\n"); |
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/* fill in the missing OEA/VEA information */ |
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current_environment = (device_tree_find_boolean(system->devices, |
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"/options/vea?") |
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? VIRTUAL_ENVIRONMENT |
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: OPERATING_ENVIRONMENT); |
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/* fill in the missing ALLIGNMENT information */ |
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current_alignment = (device_tree_find_boolean(system->devices, |
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"/options/aligned?") |
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? STRICT_ALIGNMENT |
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: NONSTRICT_ALIGNMENT); |
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if (WITH_ALIGNMENT |
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&& CURRENT_ALIGNMENT != WITH_ALIGNMENT) |
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error("target alignment support conflict\n"); |
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return system; |
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} |
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/* allow the simulation to stop/restart abnormaly */ |
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STATIC_INLINE_PSIM void |
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psim_set_halt_and_restart(psim *system, |
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void *halt_jmp_buf, |
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void *restart_jmp_buf) |
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{ |
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system->path_to_halt = halt_jmp_buf; |
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system->path_to_restart = restart_jmp_buf; |
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} |
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STATIC_INLINE_PSIM void |
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psim_clear_halt_and_restart(psim *system) |
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{ |
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system->path_to_halt = NULL; |
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system->path_to_restart = NULL; |
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} |
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INLINE_PSIM void |
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psim_restart(psim *system, |
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int current_cpu) |
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{ |
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system->last_cpu = current_cpu; |
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longjmp(*(jmp_buf*)(system->path_to_restart), current_cpu + 1); |
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} |
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INLINE_PSIM void |
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psim_halt(psim *system, |
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int current_cpu, |
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unsigned_word cia, |
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stop_reason reason, |
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int signal) |
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{ |
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system->last_cpu = current_cpu; |
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system->halt_status.cpu_nr = current_cpu; |
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system->halt_status.reason = reason; |
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system->halt_status.signal = signal; |
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system->halt_status.program_counter = cia; |
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longjmp(*(jmp_buf*)(system->path_to_halt), current_cpu + 1); |
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} |
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INLINE_PSIM psim_status |
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psim_get_status(psim *system) |
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{ |
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return system->halt_status; |
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} |
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cpu * |
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psim_cpu(psim *system, |
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int cpu_nr) |
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{ |
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if (cpu_nr < 0 || cpu_nr >= system->nr_cpus) |
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return NULL; |
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else |
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return system->processors[cpu_nr]; |
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} |
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STATIC_INLINE_PSIM int |
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sizeof_argument_strings(char **arg) |
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{ |
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int sizeof_strings = 0; |
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/* robust */ |
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if (arg == NULL) |
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return 0; |
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/* add up all the string sizes (padding as we go) */ |
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for (; *arg != NULL; arg++) { |
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int len = strlen(*arg) + 1; |
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sizeof_strings += ALIGN_8(len); |
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} |
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return sizeof_strings; |
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} |
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STATIC_INLINE_PSIM int |
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number_of_arguments(char **arg) |
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{ |
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int nr; |
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if (arg == NULL) |
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return 0; |
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for (nr = 0; *arg != NULL; arg++, nr++); |
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return nr; |
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} |
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STATIC_INLINE_PSIM int |
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sizeof_arguments(char **arg) |
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{ |
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return ALIGN_8((number_of_arguments(arg) + 1) * sizeof(unsigned_word)); |
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} |
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STATIC_INLINE_PSIM void |
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write_stack_arguments(psim *system, |
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char **arg, |
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unsigned_word start_block, |
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unsigned_word start_arg) |
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{ |
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TRACE(trace_create_stack, |
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("write_stack_arguments() - %s=0x%x %s=0x%x %s=0x%x %s=0x%x\n", |
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"system", system, "arg", arg, |
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"start_block", start_block, "start_arg", start_arg)); |
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if (arg == NULL) |
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error("write_arguments: character array NULL\n"); |
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/* only copy in arguments, memory is already zero */ |
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for (; *arg != NULL; arg++) { |
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int len = strlen(*arg)+1; |
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TRACE(trace_create_stack, |
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("write_stack_arguments - write %s=%s at %s=0x%x %s=0x%x %s=0x%x\n", |
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"**arg", *arg, "start_block", start_block, |
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"len", len, "start_arg", start_arg)); |
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if (psim_write_memory(system, 0, *arg, |
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start_block, len, |
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raw_transfer, 0) != len) |
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error("write_arguments() - write of **arg (%s) at 0x%x failed\n", |
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*arg, start_block); |
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if (psim_write_memory(system, 0, &start_block, |
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start_arg, sizeof(start_block), |
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cooked_transfer, 0) != sizeof(start_block)) |
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error("write_arguments() - write of *arg failed\n"); |
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start_block += ALIGN_8(len); |
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start_arg += sizeof(start_block); |
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} |
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} |
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STATIC_INLINE_PSIM void |
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create_elf_stack_frame(psim *system, |
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unsigned_word bottom_of_stack, |
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char **argv, |
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char **envp) |
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{ |
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/* fixme - this is over aligned */ |
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/* information block */ |
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const unsigned sizeof_envp_block = sizeof_argument_strings(envp); |
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const unsigned_word start_envp_block = bottom_of_stack - sizeof_envp_block; |
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const unsigned sizeof_argv_block = sizeof_argument_strings(argv); |
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const unsigned_word start_argv_block = start_envp_block - sizeof_argv_block; |
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/* auxiliary vector - contains only one entry */ |
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const unsigned sizeof_aux_entry = 2*sizeof(unsigned_word); /* magic */ |
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const unsigned_word start_aux = start_argv_block - ALIGN_8(sizeof_aux_entry); |
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/* environment points (including null sentinal) */ |
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const unsigned sizeof_envp = sizeof_arguments(envp); |
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const unsigned_word start_envp = start_aux - sizeof_envp; |
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/* argument pointers (including null sentinal) */ |
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const int argc = number_of_arguments(argv); |
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const unsigned sizeof_argv = sizeof_arguments(argv); |
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const unsigned_word start_argv = start_envp - sizeof_argv; |
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/* link register save address - alligned to a 16byte boundary */ |
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const unsigned_word top_of_stack = ((start_argv |
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- 2 * sizeof(unsigned_word)) |
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& ~0xf); |
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/* force some stack space */ |
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if (CURRENT_ENVIRONMENT == VIRTUAL_ENVIRONMENT |
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&& core_stack_lower_bound(system->memory) > top_of_stack) { |
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unsigned_word extra_stack_space = (core_stack_lower_bound(system->memory) |
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- FLOOR_PAGE(top_of_stack)); |
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TRACE(trace_create_stack, |
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("create_elf_stack_frame() - growing stack by 0x%x\n", |
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extra_stack_space)); |
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core_add_stack(system->memory, extra_stack_space); |
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} |
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/* install arguments on stack */ |
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write_stack_arguments(system, envp, start_envp_block, start_envp); |
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write_stack_arguments(system, argv, start_argv_block, start_argv); |
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/* set up the registers */ |
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psim_write_register(system, -1, |
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&top_of_stack, "r1", cooked_transfer); |
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psim_write_register(system, -1, |
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&argc, "r3", cooked_transfer); |
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psim_write_register(system, -1, |
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&start_argv, "r4", cooked_transfer); |
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psim_write_register(system, -1, |
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&start_envp, "r5", cooked_transfer); |
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psim_write_register(system, -1, |
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&start_aux, "r6", cooked_transfer); |
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} |
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STATIC_INLINE_PSIM void |
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create_aix_stack_frame(psim *system, |
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unsigned_word bottom_of_stack, |
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char **argv, |
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char **envp) |
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{ |
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unsigned_word core_envp; |
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unsigned_word core_argv; |
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unsigned_word core_argc; |
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unsigned_word core_aux; |
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unsigned_word top_of_stack; |
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/* cheat - create an elf stack frame */ |
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create_elf_stack_frame(system, bottom_of_stack, argv, envp); |
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/* extract argument addresses from registers */ |
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psim_read_register(system, 0, &top_of_stack, "r1", cooked_transfer); |
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psim_read_register(system, 0, &core_argc, "r3", cooked_transfer); |
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psim_read_register(system, 0, &core_argv, "r4", cooked_transfer); |
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psim_read_register(system, 0, &core_envp, "r5", cooked_transfer); |
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psim_read_register(system, 0, &core_aux, "r6", cooked_transfer); |
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/* check stack fits at least this much */ |
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if (CURRENT_ENVIRONMENT == VIRTUAL_ENVIRONMENT |
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&& core_stack_lower_bound(system->memory) > top_of_stack) { |
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unsigned_word extra_stack_space = (core_stack_lower_bound(system->memory) |
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- FLOOR_PAGE(top_of_stack)); |
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TRACE(trace_create_stack, |
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("create_aix_stack_frame() - growing stack by 0x%x\n", |
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extra_stack_space)); |
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core_add_stack(system->memory, extra_stack_space); |
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} |
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/* extract arguments from registers */ |
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error("create_aix_stack_frame() - what happens next?\n"); |
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} |
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INLINE_PSIM void |
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psim_load(psim *system) |
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{ |
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unsigned_word program_counter; |
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msreg msr; |
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/* load in core data */ |
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core_init(system->memory); |
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/* set up all processor entry points (to same thing). Maybe
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someday, the device tree could include information specifying the |
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entry point for each processor, one day */ |
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TRACE(trace_tbd, |
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("TBD - device tree specifying entry point of each processor\n")); |
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program_counter = device_tree_find_int(system->devices, |
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"/options/program-counter"); |
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psim_write_register(system, -1, |
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&program_counter, |
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"pc", cooked_transfer); |
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system->last_cpu = system->nr_cpus - 1; /* force loop to restart */ |
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/* set up the MSR for at least be/le mode */ |
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msr = (device_tree_find_boolean(system->devices, |
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"/options/little-endian?") |
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? msr_little_endian_mode |
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: 0); |
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psim_write_register(system, -1, |
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&msr, |
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"msr", cooked_transfer); |
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} |
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INLINE_PSIM void |
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psim_stack(psim *system, |
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char **argv, |
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char **envp) |
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{ |
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unsigned_word stack_pointer = device_tree_find_int(system->devices, |
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"/options/stack-pointer"); |
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if (device_tree_find_boolean(system->devices, |
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"/options/elf?")) |
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create_elf_stack_frame(system, stack_pointer, argv, envp); |
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else |
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create_aix_stack_frame(system, stack_pointer, argv, envp); |
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} |
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/* EXECUTE REAL CODE:
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Unfortunatly, there are multiple cases to consider vis: |
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<icache> X <smp> X <events> X <keep-running-flag> X ... |
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Consequently this function is written in multiple different ways */ |
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STATIC_INLINE_PSIM void |
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run_until_stop(psim *system, |
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volatile int *keep_running) |
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{ |
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#if (WITH_IDECODE_CACHE == 0 && WITH_SMP == 0) |
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/* CASE 1: No instruction cache and no SMP.
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In this case, we can take advantage of the fact that the current |
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instruction address does not need to be returned to the cpu |
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object after every execution of an instruction. Instead it only |
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needs to be saved when either A. the main loop exits or B. a |
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cpu-{halt,restart} call forces the loop to be re-entered. The |
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later functions always save the current cpu instruction |
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address. */ |
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jmp_buf halt; |
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jmp_buf restart; |
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psim_set_halt_and_restart(system, &halt, &restart); |
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if (!setjmp(halt)) { |
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do { |
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if (!setjmp(restart)) { |
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cpu *const processor = system->processors[0]; |
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unsigned_word cia = cpu_get_program_counter(processor); |
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do { |
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if (WITH_EVENTS) { |
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if (event_queue_tick(system->events)) { |
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cpu_set_program_counter(processor, cia); |
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event_queue_process(system->events); |
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cia = cpu_get_program_counter(processor); |
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} |
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} |
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{ |
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instruction_word const instruction |
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= vm_instruction_map_read(cpu_instruction_map(processor), |
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processor, cia); |
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cia = idecode_issue(processor, instruction, cia); |
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} |
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} while (keep_running == NULL || *keep_running); |
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cpu_set_program_counter(processor, cia); |
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} |
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} while(keep_running == NULL || *keep_running); |
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} |
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psim_clear_halt_and_restart(system); |
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#endif |
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#if (WITH_IDECODE_CACHE > 0 && WITH_SMP == 0) |
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/* CASE 2: Instruction case but no SMP
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Here, the additional complexity comes from there being two |
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different cache implementations. A simple function address cache |
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or a full cracked instruction cache */ |
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jmp_buf halt; |
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jmp_buf restart; |
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psim_set_halt_and_restart(system, &halt, &restart); |
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if (!setjmp(halt)) { |
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do { |
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if (!setjmp(restart)) { |
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cpu *const processor = system->processors[0]; |
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unsigned_word cia = cpu_get_program_counter(processor); |
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do { |
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if (WITH_EVENTS) |
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if (event_queue_tick(system->events)) { |
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cpu_set_program_counter(processor, cia); |
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event_queue_process(system->events); |
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cia = cpu_get_program_counter(processor); |
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} |
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{ |
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idecode_cache *const cache_entry |
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= cpu_icache(processor) + (cia / 4 % IDECODE_CACHE_SIZE); |
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if (cache_entry->address == cia) { |
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idecode_semantic *const semantic = cache_entry->semantic; |
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#if WITH_IDECODE_CACHE == 1 |
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cia = semantic(processor, cache_entry->instruction, cia); |
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#else |
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cia = semantic(processor, cache_entry, cia); |
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#endif |
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} |
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else { |
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instruction_word const instruction |
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= vm_instruction_map_read(cpu_instruction_map(processor), |
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processor, |
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cia); |
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#if WITH_IDECODE_CACHE == 1 |
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idecode_semantic *const semantic = idecode(processor, |
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instruction, |
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cia); |
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#else |
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idecode_semantic *const semantic = idecode(processor, |
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instruction, |
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cia, |
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cache_entry); |
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#endif |
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cache_entry->address = cia; |
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cache_entry->semantic = semantic; |
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#if WITH_IDECODE_CACHE == 1 |
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cache_entry->instruction = instruction; |
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cia = semantic(processor, instruction, cia); |
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#else |
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cia = semantic(processor, cache_entry, cia); |
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#endif |
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} |
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} |
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} while (keep_running == NULL || *keep_running); |
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cpu_set_program_counter(processor, cia); |
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} |
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} while(keep_running == NULL || *keep_running); |
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} |
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psim_clear_halt_and_restart(system); |
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#endif |
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#if (WITH_IDECODE_CACHE == 0 && WITH_SMP > 0) |
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/* CASE 3: No ICACHE but SMP
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The complexity here comes from needing to correctly restart the |
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system when it is aborted. In particular if cpu0 requests a |
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restart, the next cpu is still cpu1. Cpu0 being restarted after |
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all the other CPU's and the event queue have been processed */ |
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jmp_buf halt; |
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jmp_buf restart; |
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psim_set_halt_and_restart(system, &halt, &restart); |
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if (!setjmp(halt)) { |
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int first_cpu = setjmp(restart); |
|||
if (first_cpu == 0) |
|||
first_cpu = system->last_cpu + 1; |
|||
do { |
|||
int current_cpu; |
|||
for (current_cpu = first_cpu, first_cpu = 0; |
|||
current_cpu < system->nr_cpus + (WITH_EVENTS ? 1 : 0); |
|||
current_cpu++) { |
|||
if (WITH_EVENTS && current_cpu == system->nr_cpus) { |
|||
if (event_queue_tick(system->events)) |
|||
event_queue_process(system->events); |
|||
} |
|||
else { |
|||
cpu *const processor = system->processors[current_cpu]; |
|||
unsigned_word const cia = cpu_get_program_counter(processor); |
|||
instruction_word instruction = |
|||
vm_instruction_map_read(cpu_instruction_map(processor), |
|||
processor, |
|||
cia); |
|||
cpu_set_program_counter(processor, |
|||
idecode_issue(processor, instruction, cia)); |
|||
} |
|||
if (!(keep_running == NULL || *keep_running)) { |
|||
system->last_cpu = current_cpu; |
|||
break; |
|||
} |
|||
} |
|||
} while (keep_running == NULL || *keep_running); |
|||
} |
|||
psim_clear_halt_and_restart(system); |
|||
#endif |
|||
|
|||
#if (WITH_IDECODE_CACHE > 0 && WITH_SMP > 0) |
|||
|
|||
/* CASE 4: ICACHE and SMP ...
|
|||
|
|||
This time, everything goes wrong. Need to restart loops |
|||
correctly, need to save the program counter and finally need to |
|||
keep track of each processors current address! */ |
|||
|
|||
jmp_buf halt; |
|||
jmp_buf restart; |
|||
psim_set_halt_and_restart(system, &halt, &restart); |
|||
|
|||
if (!setjmp(halt)) { |
|||
int first_cpu = setjmp(restart); |
|||
if (!first_cpu) |
|||
first_cpu = system->last_cpu + 1; |
|||
do { |
|||
int current_cpu; |
|||
for (current_cpu = first_cpu, first_cpu = 0; |
|||
current_cpu < system->nr_cpus + (WITH_EVENTS ? 1 : 0); |
|||
current_cpu++) { |
|||
if (WITH_EVENTS && current_cpu == system->nr_cpus) { |
|||
if (event_queue_tick(system->events)) |
|||
event_queue_process(system->events); |
|||
} |
|||
else { |
|||
cpu *processor = system->processors[current_cpu]; |
|||
unsigned_word const cia = cpu_get_program_counter(processor); |
|||
idecode_cache *cache_entry |
|||
= (cpu_icache(processor) + (cia / 4 % IDECODE_CACHE_SIZE)); |
|||
if (cache_entry->address == cia) { |
|||
idecode_semantic *semantic = cache_entry->semantic; |
|||
#if WITH_IDECODE_CACHE == 1 |
|||
cpu_set_program_counter(processor, |
|||
semantic(processor, |
|||
cache_entry->instruction, |
|||
cia); |
|||
#else |
|||
cpu_set_program_counter(processor, |
|||
semantic(processor, |
|||
cache_entry, |
|||
cia); |
|||
#endif |
|||
} |
|||
else { |
|||
instruction_word instruction = |
|||
vm_instruction_map_read(cpu_instruction_map(processor), |
|||
processor, |
|||
cia); |
|||
#if WITH_IDECODE_CACHE == 1 |
|||
idecode_semantic *semantic = idecode(processor, |
|||
instruction, |
|||
cia); |
|||
#else |
|||
idecode_semantic *semantic = idecode(processor, |
|||
instruction, |
|||
cia, |
|||
cache_entry); |
|||
#endif |
|||
cache_entry->address = cia; |
|||
cache_entry->semantic = semantic; |
|||
#if WITH_IDECODE_CACHE == 1 |
|||
cache_entry->instruction = instruction; |
|||
cpu_set_program_counter(processor, |
|||
semantic(processor, instruction, cia)); |
|||
#else |
|||
cpu_set_program_counter(processor, |
|||
semantic(processor, cache_entry, cia); |
|||
#endif |
|||
} |
|||
} |
|||
if (!(keep_running == NULL || *keep_running)) |
|||
break; |
|||
} |
|||
} while (keep_running == NULL || *keep_running); |
|||
} |
|||
psim_clear_halt_and_restart(system); |
|||
#endif |
|||
} |
|||
|
|||
|
|||
/* SIMULATE INSTRUCTIONS, various different ways of achieving the same
|
|||
thing */ |
|||
|
|||
INLINE_PSIM void |
|||
psim_step(psim *system) |
|||
{ |
|||
volatile int keep_running = 0; |
|||
psim_run_until_stop(system, &keep_running); |
|||
} |
|||
|
|||
INLINE_PSIM void |
|||
psim_run(psim *system) |
|||
{ |
|||
run_until_stop(system, NULL); |
|||
} |
|||
|
|||
INLINE_PSIM void |
|||
psim_run_until_stop(psim *system, |
|||
volatile int *keep_running) |
|||
{ |
|||
run_until_stop(system, keep_running); |
|||
} |
|||
|
|||
|
|||
|
|||
/* storage manipulation functions */ |
|||
|
|||
INLINE_PSIM void |
|||
psim_read_register(psim *system, |
|||
int which_cpu, |
|||
void *buf, |
|||
const char reg[], |
|||
transfer_mode mode) |
|||
{ |
|||
register_descriptions description; |
|||
char cooked_buf[sizeof(natural_word)]; |
|||
cpu *processor; |
|||
|
|||
/* find our processor */ |
|||
if (which_cpu < 0 || which_cpu > system->nr_cpus) |
|||
error("psim_read_register() - invalid processor %d\n", which_cpu); |
|||
if (which_cpu == system->nr_cpus) |
|||
which_cpu = system->last_cpu; |
|||
processor = system->processors[which_cpu]; |
|||
|
|||
/* find the register description */ |
|||
description = register_description(reg); |
|||
if (description.type == reg_invalid) |
|||
error("psim_read_register() invalid register name `%s'\n", reg); |
|||
|
|||
/* get the cooked value */ |
|||
switch (description.type) { |
|||
|
|||
case reg_gpr: |
|||
*(gpreg*)cooked_buf = cpu_registers(processor)->gpr[description.index]; |
|||
break; |
|||
|
|||
case reg_spr: |
|||
*(spreg*)cooked_buf = cpu_registers(processor)->spr[description.index]; |
|||
break; |
|||
|
|||
case reg_sr: |
|||
*(sreg*)cooked_buf = cpu_registers(processor)->sr[description.index]; |
|||
break; |
|||
|
|||
case reg_fpr: |
|||
*(fpreg*)cooked_buf = cpu_registers(processor)->fpr[description.index]; |
|||
break; |
|||
|
|||
case reg_pc: |
|||
*(unsigned_word*)cooked_buf = cpu_get_program_counter(processor); |
|||
break; |
|||
|
|||
case reg_cr: |
|||
*(creg*)cooked_buf = cpu_registers(processor)->cr; |
|||
break; |
|||
|
|||
case reg_msr: |
|||
*(msreg*)cooked_buf = cpu_registers(processor)->msr; |
|||
break; |
|||
|
|||
default: |
|||
printf_filtered("psim_read_register(processor=0x%x,buf=0x%x,reg=%s) %s\n", |
|||
processor, buf, reg, |
|||
"read of this register unimplemented"); |
|||
break; |
|||
|
|||
} |
|||
|
|||
/* the PSIM internal values are in host order. To fetch raw data,
|
|||
they need to be converted into target order and then returned */ |
|||
if (mode == raw_transfer) { |
|||
/* FIXME - assumes that all registers are simple integers */ |
|||
switch (description.size) { |
|||
case 1: |
|||
*(unsigned_1*)buf = H2T_1(*(unsigned_1*)cooked_buf); |
|||
break; |
|||
case 2: |
|||
*(unsigned_2*)buf = H2T_2(*(unsigned_2*)cooked_buf); |
|||
break; |
|||
case 4: |
|||
*(unsigned_4*)buf = H2T_4(*(unsigned_4*)cooked_buf); |
|||
break; |
|||
case 8: |
|||
*(unsigned_8*)buf = H2T_8(*(unsigned_8*)cooked_buf); |
|||
break; |
|||
} |
|||
} |
|||
else { |
|||
bcopy(cooked_buf, buf, description.size); |
|||
} |
|||
|
|||
} |
|||
|
|||
|
|||
|
|||
INLINE_PSIM void |
|||
psim_write_register(psim *system, |
|||
int which_cpu, |
|||
const void *buf, |
|||
const char reg[], |
|||
transfer_mode mode) |
|||
{ |
|||
cpu *processor; |
|||
register_descriptions description; |
|||
char cooked_buf[sizeof(natural_word)]; |
|||
|
|||
/* find our processor */ |
|||
if (which_cpu == -1) { |
|||
int i; |
|||
for (i = 0; i < system->nr_cpus; i++) |
|||
psim_write_register(system, i, buf, reg, mode); |
|||
return; |
|||
} |
|||
else if (which_cpu == system->nr_cpus) { |
|||
which_cpu = system->last_cpu; |
|||
} |
|||
else if (which_cpu < 0 || which_cpu >= system->nr_cpus) { |
|||
error("psim_read_register() - invalid processor %d\n", which_cpu); |
|||
} |
|||
|
|||
processor = system->processors[which_cpu]; |
|||
|
|||
/* find the description of the register */ |
|||
description = register_description(reg); |
|||
if (description.type == reg_invalid) |
|||
error("psim_write_register() invalid register name %s\n", reg); |
|||
|
|||
/* If the data is comming in raw (target order), need to cook it
|
|||
into host order before putting it into PSIM's internal structures */ |
|||
if (mode == raw_transfer) { |
|||
switch (description.size) { |
|||
case 1: |
|||
*(unsigned_1*)cooked_buf = T2H_1(*(unsigned_1*)buf); |
|||
break; |
|||
case 2: |
|||
*(unsigned_2*)cooked_buf = T2H_2(*(unsigned_2*)buf); |
|||
break; |
|||
case 4: |
|||
*(unsigned_4*)cooked_buf = T2H_4(*(unsigned_4*)buf); |
|||
break; |
|||
case 8: |
|||
*(unsigned_8*)cooked_buf = T2H_8(*(unsigned_8*)buf); |
|||
break; |
|||
} |
|||
} |
|||
else { |
|||
bcopy(buf, cooked_buf, description.size); |
|||
} |
|||
|
|||
/* put the cooked value into the register */ |
|||
switch (description.type) { |
|||
|
|||
case reg_gpr: |
|||
cpu_registers(processor)->gpr[description.index] = *(gpreg*)cooked_buf; |
|||
break; |
|||
|
|||
case reg_fpr: |
|||
cpu_registers(processor)->fpr[description.index] = *(fpreg*)cooked_buf; |
|||
break; |
|||
|
|||
case reg_pc: |
|||
cpu_set_program_counter(processor, *(unsigned_word*)cooked_buf); |
|||
break; |
|||
|
|||
case reg_spr: |
|||
cpu_registers(processor)->spr[description.index] = *(spreg*)cooked_buf; |
|||
break; |
|||
|
|||
case reg_sr: |
|||
cpu_registers(processor)->sr[description.index] = *(sreg*)cooked_buf; |
|||
break; |
|||
|
|||
case reg_cr: |
|||
cpu_registers(processor)->cr = *(creg*)cooked_buf; |
|||
break; |
|||
|
|||
case reg_msr: |
|||
cpu_registers(processor)->msr = *(msreg*)cooked_buf; |
|||
break; |
|||
|
|||
default: |
|||
printf_filtered("psim_write_register(processor=0x%x,cooked_buf=0x%x,reg=%s) %s\n", |
|||
processor, cooked_buf, reg, |
|||
"read of this register unimplemented"); |
|||
break; |
|||
|
|||
} |
|||
|
|||
} |
|||
|
|||
|
|||
|
|||
INLINE_PSIM unsigned |
|||
psim_read_memory(psim *system, |
|||
int which_cpu, |
|||
void *buffer, |
|||
unsigned_word vaddr, |
|||
unsigned len, |
|||
transfer_mode mode) |
|||
{ |
|||
cpu *processor; |
|||
if (which_cpu < 0 || which_cpu > system->nr_cpus) |
|||
error("psim_read_memory() invalid cpu\n"); |
|||
if (which_cpu == system->nr_cpus) |
|||
which_cpu = system->last_cpu; |
|||
processor = system->processors[which_cpu]; |
|||
return vm_data_map_read_buffer(cpu_data_map(processor), |
|||
buffer, vaddr, len, mode); |
|||
} |
|||
|
|||
|
|||
INLINE_PSIM unsigned |
|||
psim_write_memory(psim *system, |
|||
int which_cpu, |
|||
const void *buffer, |
|||
unsigned_word vaddr, |
|||
unsigned len, |
|||
transfer_mode mode, |
|||
int violate_read_only_section) |
|||
{ |
|||
cpu *processor; |
|||
if (which_cpu < 0 || which_cpu > system->nr_cpus) |
|||
error("psim_read_memory() invalid cpu\n"); |
|||
if (which_cpu == system->nr_cpus) |
|||
which_cpu = system->last_cpu; |
|||
processor = system->processors[which_cpu]; |
|||
return vm_data_map_write_buffer(cpu_data_map(processor), |
|||
buffer, vaddr, len, mode, 1); |
|||
} |
|||
|
|||
|
|||
#endif /* _PSIM_C_ */ |
|||
Loading…
Reference in new issue