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@ -1,37 +1,37 @@ |
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/* Assemble V850 instructions.
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Copyright 1996, 1997, 1998, 2000, 2001 Free Software Foundation, Inc. |
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Copyright 1996, 1997, 1998, 2000, 2001, 2003 Free Software Foundation, Inc. |
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This program is free software; you can redistribute it and/or modify |
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it under the terms of the GNU General Public License as published by |
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the Free Software Foundation; either version 2 of the License, or |
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(at your option) any later version. |
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This program is free software; you can redistribute it and/or modify |
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it under the terms of the GNU General Public License as published by |
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the Free Software Foundation; either version 2 of the License, or |
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(at your option) any later version. |
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This program is distributed in the hope that it will be useful, |
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but WITHOUT ANY WARRANTY; without even the implied warranty of |
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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GNU General Public License for more details. |
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This program is distributed in the hope that it will be useful, |
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but WITHOUT ANY WARRANTY; without even the implied warranty of |
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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GNU General Public License for more details. |
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You should have received a copy of the GNU General Public License |
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along with this program; if not, write to the Free Software |
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Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ |
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You should have received a copy of the GNU General Public License |
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along with this program; if not, write to the Free Software |
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Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ |
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#include "sysdep.h" |
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#include "opcode/v850.h" |
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#include <stdio.h> |
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#include "opintl.h" |
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/* regular opcode */ |
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/* Regular opcodes. */ |
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#define OP(x) ((x & 0x3f) << 5) |
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#define OP_MASK OP (0x3f) |
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/* conditional branch opcode */ |
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/* Conditional branch opcodes. */ |
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#define BOP(x) ((0x0b << 7) | (x & 0x0f)) |
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#define BOP_MASK ((0x0f << 7) | 0x0f) |
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/* one-word opcodes */ |
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/* One-word opcodes. */ |
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#define one(x) ((unsigned int) (x)) |
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/* two-word opcodes */ |
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/* Two-word opcodes. */ |
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#define two(x,y) ((unsigned int) (x) | ((unsigned int) (y) << 16)) |
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static long unsigned insert_d9 PARAMS ((long unsigned, long, const char **)); |
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@ -402,15 +402,15 @@ const struct v850_operand v850_operands[] = |
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#define UNUSED 0 |
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{ 0, 0, NULL, NULL, 0 }, |
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/* The R1 field in a format 1, 6, 7, or 9 insn. */ |
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/* The R1 field in a format 1, 6, 7, or 9 insn. */ |
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#define R1 (UNUSED + 1) |
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{ 5, 0, NULL, NULL, V850_OPERAND_REG }, |
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/* As above, but register 0 is not allowed. */ |
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#define R1_NOTR0 (R1 + 1) |
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{ 5, 0, NULL, NULL, V850_OPERAND_REG | V850_NOT_R0 }, |
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{ 5, 0, NULL, NULL, V850_OPERAND_REG | V850_NOT_R0 }, |
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/* The R2 field in a format 1, 2, 4, 5, 6, 7, 9 insn. */ |
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/* The R2 field in a format 1, 2, 4, 5, 6, 7, 9 insn. */ |
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#define R2 (R1_NOTR0 + 1) |
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{ 5, 11, NULL, NULL, V850_OPERAND_REG }, |
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@ -418,23 +418,23 @@ const struct v850_operand v850_operands[] = |
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#define R2_NOTR0 (R2 + 1) |
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{ 5, 11, NULL, NULL, V850_OPERAND_REG | V850_NOT_R0 }, |
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/* The imm5 field in a format 2 insn. */ |
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/* The imm5 field in a format 2 insn. */ |
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#define I5 (R2_NOTR0 + 1) |
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{ 5, 0, NULL, NULL, V850_OPERAND_SIGNED }, |
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/* The unsigned imm5 field in a format 2 insn. */ |
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/* The unsigned imm5 field in a format 2 insn. */ |
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#define I5U (I5 + 1) |
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{ 5, 0, NULL, NULL, 0 }, |
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/* The imm16 field in a format 6 insn. */ |
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/* The imm16 field in a format 6 insn. */ |
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#define I16 (I5U + 1) |
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{ 16, 16, NULL, NULL, V850_OPERAND_SIGNED }, |
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/* The signed disp7 field in a format 4 insn. */ |
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/* The signed disp7 field in a format 4 insn. */ |
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#define D7 (I16 + 1) |
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{ 7, 0, NULL, NULL, 0}, |
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/* The disp16 field in a format 6 insn. */ |
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/* The disp16 field in a format 6 insn. */ |
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#define D16_15 (D7 + 1) |
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{ 15, 17, insert_d16_15, extract_d16_15, V850_OPERAND_SIGNED }, |
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@ -446,11 +446,11 @@ const struct v850_operand v850_operands[] = |
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#define CCCC (B3 + 1) |
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{ 4, 0, NULL, NULL, V850_OPERAND_CC }, |
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/* The unsigned DISP8 field in a format 4 insn. */ |
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/* The unsigned DISP8 field in a format 4 insn. */ |
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#define D8_7 (CCCC + 1) |
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{ 7, 0, insert_d8_7, extract_d8_7, 0 }, |
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/* The unsigned DISP8 field in a format 4 insn. */ |
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/* The unsigned DISP8 field in a format 4 insn. */ |
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#define D8_6 (D8_7 + 1) |
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{ 6, 1, insert_d8_6, extract_d8_6, 0 }, |
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@ -462,7 +462,7 @@ const struct v850_operand v850_operands[] = |
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#define EP (SR1 + 1) |
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{ 0, 0, NULL, NULL, V850_OPERAND_EP }, |
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/* The imm16 field (unsigned) in a format 6 insn. */ |
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/* The imm16 field (unsigned) in a format 6 insn. */ |
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#define I16U (EP + 1) |
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{ 16, 16, NULL, NULL, 0}, |
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@ -470,11 +470,11 @@ const struct v850_operand v850_operands[] = |
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#define SR2 (I16U + 1) |
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{ 5, 11, NULL, NULL, V850_OPERAND_SRG }, |
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/* The disp16 field in a format 8 insn. */ |
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/* The disp16 field in a format 8 insn. */ |
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#define D16 (SR2 + 1) |
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{ 16, 16, NULL, NULL, V850_OPERAND_SIGNED }, |
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/* The DISP9 field in a format 3 insn, relaxable. */ |
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/* The DISP9 field in a format 3 insn, relaxable. */ |
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#define D9_RELAX (D16 + 1) |
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{ 9, 0, insert_d9, extract_d9, V850_OPERAND_RELAX | V850_OPERAND_SIGNED | V850_OPERAND_DISP }, |
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@ -484,19 +484,19 @@ const struct v850_operand v850_operands[] = |
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#define D22 (D9_RELAX + 1) |
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{ 22, 0, insert_d22, extract_d22, V850_OPERAND_SIGNED | V850_OPERAND_DISP }, |
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/* The signed disp4 field in a format 4 insn. */ |
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/* The signed disp4 field in a format 4 insn. */ |
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#define D4 (D22 + 1) |
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{ 4, 0, NULL, NULL, 0}, |
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/* The unsigned disp5 field in a format 4 insn. */ |
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/* The unsigned disp5 field in a format 4 insn. */ |
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#define D5_4 (D4 + 1) |
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{ 4, 0, insert_d5_4, extract_d5_4, 0 }, |
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/* The disp16 field in an format 7 unsigned byte load insn. */ |
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/* The disp16 field in an format 7 unsigned byte load insn. */ |
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#define D16_16 (D5_4 + 1) |
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{ -1, 0xfffe0020, insert_d16_16, extract_d16_16, 0 }, |
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/* Third register in conditional moves. */ |
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/* Third register in conditional moves. */ |
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#define R3 (D16_16 + 1) |
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{ 5, 27, NULL, NULL, V850_OPERAND_REG }, |
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@ -504,11 +504,11 @@ const struct v850_operand v850_operands[] = |
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#define MOVCC (R3 + 1) |
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{ 4, 17, NULL, NULL, V850_OPERAND_CC }, |
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/* The imm9 field in a multiply word. */ |
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/* The imm9 field in a multiply word. */ |
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#define I9 (MOVCC + 1) |
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{ 9, 0, insert_i9, extract_i9, V850_OPERAND_SIGNED }, |
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/* The unsigned imm9 field in a multiply word. */ |
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/* The unsigned imm9 field in a multiply word. */ |
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#define U9 (I9 + 1) |
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{ 9, 0, insert_u9, extract_u9, 0 }, |
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@ -516,7 +516,7 @@ const struct v850_operand v850_operands[] = |
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#define LIST12 (U9 + 1) |
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{ -1, 0xffe00001, NULL, NULL, V850E_PUSH_POP }, |
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/* The IMM6 field in a call instruction. */ |
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/* The IMM6 field in a call instruction. */ |
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#define I6 (LIST12 + 1) |
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{ 6, 0, NULL, NULL, 0 }, |
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@ -528,19 +528,19 @@ const struct v850_operand v850_operands[] = |
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#define IMM32 (IMM16 + 1) |
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{ 0, 0, NULL, NULL, V850E_IMMEDIATE32 }, |
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/* The imm5 field in a push/pop instruction. */ |
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/* The imm5 field in a push/pop instruction. */ |
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#define IMM5 (IMM32 + 1) |
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{ 5, 1, NULL, NULL, 0 }, |
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/* Reg2 in dispose instruction. */ |
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/* Reg2 in dispose instruction. */ |
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#define R2DISPOSE (IMM5 + 1) |
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{ 5, 16, NULL, NULL, V850_OPERAND_REG | V850_NOT_R0 }, |
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/* Stack pointer in prepare instruction. */ |
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/* Stack pointer in prepare instruction. */ |
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#define SP (R2DISPOSE + 1) |
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{ 2, 19, insert_spe, extract_spe, V850_OPERAND_REG }, |
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/* The IMM5 field in a divide N step instruction. */ |
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/* The IMM5 field in a divide N step instruction. */ |
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#define I5DIV (SP + 1) |
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{ 9, 0, insert_i5div, extract_i5div, V850_OPERAND_SIGNED }, |
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@ -550,23 +550,24 @@ const struct v850_operand v850_operands[] = |
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/* The list of registers in a PUSHML/POPML instruction. */ |
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#define LIST18_L (LIST18_H + 1) |
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{ -1, 0xfff8001f, NULL, NULL, V850E_PUSH_POP }, /* The setting of the 4th bit is a flag to disassmble() in v850-dis.c */ |
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/* The setting of the 4th bit is a flag to disassmble() in v850-dis.c. */ |
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{ -1, 0xfff8001f, NULL, NULL, V850E_PUSH_POP }, |
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} ; |
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/* reg-reg instruction format (Format I) */ |
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/* Reg - Reg instruction format (Format I). */ |
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#define IF1 {R1, R2} |
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/* imm-reg instruction format (Format II) */ |
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/* Imm - Reg instruction format (Format II). */ |
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#define IF2 {I5, R2} |
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/* conditional branch instruction format (Format III) */ |
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/* Conditional branch instruction format (Format III). */ |
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#define IF3 {D9_RELAX} |
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/* 3 operand instruction (Format VI) */ |
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/* 3 operand instruction (Format VI). */ |
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#define IF6 {I16, R1, R2} |
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/* 3 operand instruction (Format VI) */ |
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/* 3 operand instruction (Format VI). */ |
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#define IF6U {I16U, R1, R2} |
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@ -604,17 +605,22 @@ const struct v850_operand v850_operands[] = |
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const struct v850_opcode v850_opcodes[] = |
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{ |
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{ "breakpoint", 0xffff, 0xffff, {UNUSED}, 0, PROCESSOR_ALL }, |
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{ "dbtrap", one (0xf840), one (0xffff), {UNUSED}, 0, PROCESSOR_V850E1 }, |
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{ "jmp", one (0x0060), one (0xffe0), {R1}, 1, PROCESSOR_ALL }, |
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/* load/store instructions */ |
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/* Load/store instructions. */ |
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{ "sld.bu", one (0x0060), one (0x07f0), {D4, EP, R2_NOTR0}, 1, PROCESSOR_V850E1 }, |
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{ "sld.bu", one (0x0060), one (0x07f0), {D4, EP, R2_NOTR0}, 1, PROCESSOR_V850E }, |
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{ "sld.hu", one (0x0070), one (0x07f0), {D5_4, EP, R2_NOTR0}, 1, PROCESSOR_V850E1 }, |
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{ "sld.hu", one (0x0070), one (0x07f0), {D5_4, EP, R2_NOTR0}, 1, PROCESSOR_V850E }, |
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{ "sld.b", one (0x0300), one (0x0780), {D7, EP, R2}, 1, PROCESSOR_V850E1 }, |
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{ "sld.b", one (0x0300), one (0x0780), {D7, EP, R2}, 1, PROCESSOR_V850E }, |
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{ "sld.b", one (0x0300), one (0x0780), {D7, EP, R2}, 1, PROCESSOR_V850 }, |
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{ "sld.h", one (0x0400), one (0x0780), {D8_7, EP, R2}, 1, PROCESSOR_V850E1 }, |
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{ "sld.h", one (0x0400), one (0x0780), {D8_7, EP, R2}, 1, PROCESSOR_V850E }, |
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{ "sld.h", one (0x0400), one (0x0780), {D8_7, EP, R2}, 1, PROCESSOR_V850 }, |
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{ "sld.w", one (0x0500), one (0x0781), {D8_6, EP, R2}, 1, PROCESSOR_ALL }, |
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@ -639,7 +645,7 @@ const struct v850_opcode v850_opcodes[] = |
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{ "st.h", two (0x0760, 0x0000), two (0x07e0, 0x0001), {R2, D16_15, R1}, 2, PROCESSOR_ALL }, |
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{ "st.w", two (0x0760, 0x0001), two (0x07e0, 0x0001), {R2, D16_15, R1}, 2, PROCESSOR_ALL }, |
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/* byte swap/extend instructions */ |
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/* Byte swap/extend instructions. */ |
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{ "zxb", one (0x0080), one (0xffe0), {R1_NOTR0}, 0, PROCESSOR_NOT_V850 }, |
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{ "zxh", one (0x00c0), one (0xffe0), {R1_NOTR0}, 0, PROCESSOR_NOT_V850 }, |
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{ "sxb", one (0x00a0), one (0xffe0), {R1_NOTR0}, 0, PROCESSOR_NOT_V850 }, |
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@ -648,12 +654,12 @@ const struct v850_opcode v850_opcodes[] = |
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{ "bsw", two (0x07e0, 0x0340), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_NOT_V850 }, |
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{ "hsw", two (0x07e0, 0x0344), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_NOT_V850 }, |
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/* jump table instructions */ |
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/* Jump table instructions. */ |
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{ "switch", one (0x0040), one (0xffe0), {R1}, 1, PROCESSOR_NOT_V850 }, |
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{ "callt", one (0x0200), one (0xffc0), {I6}, 0, PROCESSOR_NOT_V850 }, |
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{ "ctret", two (0x07e0, 0x0144), two (0xffff, 0xffff), {0}, 0, PROCESSOR_NOT_V850 }, |
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/* arithmetic operation instructions */ |
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/* Arithmetic operation instructions. */ |
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{ "setf", two (0x07e0, 0x0000), two (0x07f0, 0xffff), {CCCC, R2}, 0, PROCESSOR_ALL }, |
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{ "cmov", two (0x07e0, 0x0320), two (0x07e0, 0x07e1), {MOVCC, R1, R2, R3}, 0, PROCESSOR_NOT_V850 }, |
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{ "cmov", two (0x07e0, 0x0300), two (0x07e0, 0x07e1), {MOVCC, I5, R2, R3}, 0, PROCESSOR_NOT_V850 }, |
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@ -686,14 +692,14 @@ const struct v850_opcode v850_opcodes[] = |
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{ "cmp", OP (0x0f), OP_MASK, IF1, 0, PROCESSOR_ALL }, |
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{ "cmp", OP (0x13), OP_MASK, IF2, 0, PROCESSOR_ALL }, |
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/* saturated operation instructions */ |
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/* Saturated operation instructions. */ |
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{ "satadd", OP (0x11), OP_MASK, {I5, R2_NOTR0}, 0, PROCESSOR_ALL }, |
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{ "satadd", OP (0x06), OP_MASK, {R1, R2_NOTR0}, 0, PROCESSOR_ALL }, |
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{ "satsub", OP (0x05), OP_MASK, {R1, R2_NOTR0}, 0, PROCESSOR_ALL }, |
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{ "satsubi", OP (0x33), OP_MASK, {I16, R1, R2_NOTR0}, 0, PROCESSOR_ALL }, |
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{ "satsubr", OP (0x04), OP_MASK, {R1, R2_NOTR0}, 0, PROCESSOR_ALL }, |
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/* logical operation instructions */ |
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/* Logical operation instructions. */ |
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{ "tst", OP (0x0b), OP_MASK, IF1, 0, PROCESSOR_ALL }, |
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{ "or", OP (0x08), OP_MASK, IF1, 0, PROCESSOR_ALL }, |
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{ "ori", OP (0x34), OP_MASK, IF6U, 0, PROCESSOR_ALL }, |
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@ -710,21 +716,21 @@ const struct v850_opcode v850_opcodes[] = |
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{ "shr", two (0x07e0, 0x0080), two (0x07e0, 0xffff), {R1, R2}, 0, PROCESSOR_ALL }, |
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{ "sasf", two (0x07e0, 0x0200), two (0x07f0, 0xffff), {CCCC, R2}, 0, PROCESSOR_NOT_V850 }, |
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/* branch instructions */ |
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/* signed integer */ |
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/* Branch instructions. */ |
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/* Signed integer. */ |
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{ "bgt", BOP (0xf), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
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{ "bge", BOP (0xe), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
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{ "blt", BOP (0x6), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
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{ "ble", BOP (0x7), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
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/* unsigned integer */ |
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/* Unsigned integer. */ |
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{ "bh", BOP (0xb), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
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{ "bnh", BOP (0x3), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
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{ "bl", BOP (0x1), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
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{ "bnl", BOP (0x9), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
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/* common */ |
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/* Common. */ |
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{ "be", BOP (0x2), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
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{ "bne", BOP (0xa), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
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/* others */ |
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/* Others. */ |
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{ "bv", BOP (0x0), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
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{ "bnv", BOP (0x8), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
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{ "bn", BOP (0x4), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
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@ -741,20 +747,20 @@ const struct v850_opcode v850_opcodes[] = |
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We use the short form in the opcode/mask fields. The assembler |
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will twiddle bits as necessary if the long form is needed. */ |
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/* signed integer */ |
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/* Signed integer. */ |
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{ "jgt", BOP (0xf), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
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{ "jge", BOP (0xe), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
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{ "jlt", BOP (0x6), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
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{ "jle", BOP (0x7), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
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/* unsigned integer */ |
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/* Unsigned integer. */ |
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{ "jh", BOP (0xb), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
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{ "jnh", BOP (0x3), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
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{ "jl", BOP (0x1), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
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{ "jnl", BOP (0x9), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
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/* common */ |
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/* Common. */ |
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{ "je", BOP (0x2), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
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{ "jne", BOP (0xa), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
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/* others */ |
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/* Others. */ |
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{ "jv", BOP (0x0), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
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{ "jnv", BOP (0x8), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
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{ "jn", BOP (0x4), BOP_MASK, IF3, 0, PROCESSOR_ALL }, |
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@ -769,7 +775,7 @@ const struct v850_opcode v850_opcodes[] = |
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{ "jr", one (0x0780), two (0xffc0, 0x0001), {D22}, 0, PROCESSOR_ALL }, |
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{ "jarl", one (0x0780), two (0x07c0, 0x0001), {D22, R2}, 0, PROCESSOR_ALL}, |
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/* bit manipulation instructions */ |
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/* Bit manipulation instructions. */ |
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{ "set1", two (0x07c0, 0x0000), two (0xc7e0, 0x0000), {B3, D16, R1}, 2, PROCESSOR_ALL }, |
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{ "set1", two (0x07e0, 0x00e0), two (0x07e0, 0xffff), {R2, R1}, 2, PROCESSOR_NOT_V850 }, |
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{ "not1", two (0x47c0, 0x0000), two (0xc7e0, 0x0000), {B3, D16, R1}, 2, PROCESSOR_ALL }, |
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@ -779,7 +785,7 @@ const struct v850_opcode v850_opcodes[] = |
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{ "tst1", two (0xc7c0, 0x0000), two (0xc7e0, 0x0000), {B3, D16, R1}, 2, PROCESSOR_ALL }, |
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{ "tst1", two (0x07e0, 0x00e6), two (0x07e0, 0xffff), {R2, R1}, 2, PROCESSOR_NOT_V850 }, |
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/* special instructions */ |
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/* Special instructions. */ |
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{ "di", two (0x07e0, 0x0160), two (0xffff, 0xffff), {0}, 0, PROCESSOR_ALL }, |
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{ "ei", two (0x87e0, 0x0160), two (0xffff, 0xffff), {0}, 0, PROCESSOR_ALL }, |
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{ "halt", two (0x07e0, 0x0120), two (0xffff, 0xffff), {0}, 0, PROCESSOR_ALL }, |
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@ -787,10 +793,10 @@ const struct v850_opcode v850_opcodes[] = |
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{ "trap", two (0x07e0, 0x0100), two (0xffe0, 0xffff), {I5U}, 0, PROCESSOR_ALL }, |
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{ "ldsr", two (0x07e0, 0x0020), two (0x07e0, 0xffff), {R1, SR2}, 0, PROCESSOR_ALL }, |
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{ "stsr", two (0x07e0, 0x0040), two (0x07e0, 0xffff), {SR1, R2}, 0, PROCESSOR_ALL }, |
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{ "dbret", two (0x07e0, 0x0146), two (0xffff, 0xffff), {UNUSED}, 0, PROCESSOR_V850E1 }, |
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{ 0, 0, 0, {0}, 0, 0 }, |
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} ; |
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const int v850_num_opcodes = |
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sizeof (v850_opcodes) / sizeof (v850_opcodes[0]); |
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Nick Clifton
23 years ago