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aarch64: Add FEAT_SPECRES2 support 

This patch add supports for FEAT_SPECRES2 "Enhanced speculation
restriction instructions" adding the "cosp" instruction.

This is mandatory v8.9-a/v9.4-a and optional v8.0-a+/v9.0-a+.  It is
enabled by the +predres2 march flag.
binutils-2_42-branch
Andrea Corallo 3 years ago
parent
25bb95ea6d
commit
88b5a8ae13
11 changed files with 2112 additions and 2075 deletions
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  1. 1
      gas/config/tc-aarch64.c
  2. 2
      gas/doc/c-aarch64.texi
  3. 3
      gas/testsuite/gas/aarch64/illegal-predres2-1.d
  4. 5
      gas/testsuite/gas/aarch64/illegal-predres2-1.l
  5. 10
      gas/testsuite/gas/aarch64/predres2.d
  6. 4
      gas/testsuite/gas/aarch64/predres2.s
  7. 5
      include/opcode/aarch64.h
  8. 177
      opcodes/aarch64-asm-2.c
  9. 3957
      opcodes/aarch64-dis-2.c
  10. 16
      opcodes/aarch64-opc-2.c
  11. 7
      opcodes/aarch64-tbl.h

1
gas/config/tc-aarch64.c
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@ -10259,6 +10259,7 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
{"sha2", AARCH64_FEATURE (SHA2), AARCH64_FEATURE (FP)},
{"sb", AARCH64_FEATURE (SB), AARCH64_NO_FEATURES},
{"predres", AARCH64_FEATURE (PREDRES), AARCH64_NO_FEATURES},
{"predres2", AARCH64_FEATURE (PREDRES2), AARCH64_FEATURE (PREDRES)},
{"aes", AARCH64_FEATURE (AES), AARCH64_FEATURE (SIMD)},
{"sm4", AARCH64_FEATURE (SM4), AARCH64_FEATURE (SIMD)},
{"sha3", AARCH64_FEATURE (SHA3), AARCH64_FEATURE (SHA2)},

2
gas/doc/c-aarch64.texi
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@ -270,6 +270,8 @@ automatically cause those extensions to be disabled.
@tab Enable the 128-bit Atomic Instructions extension. This implies @code{lse}.
@item @code{rasv2} @tab N/A @tab Armv9.4-A or later
@tab Enable the Reliability, Availability and Serviceability extension v2.
@item @code{predres2} @tab ARMv8-A/Armv9-A @tab ARMv8.9-A/Armv9.4-A or later
@tab Enable Prediction instructions.
@end multitable
@node AArch64 Syntax

3
gas/testsuite/gas/aarch64/illegal-predres2-1.d
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@ -0,0 +1,3 @@
#as: -march=armv8-a
#source: predres2.s
#error_output: illegal-predres2-1.l

5
gas/testsuite/gas/aarch64/illegal-predres2-1.l
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@ -0,0 +1,5 @@
[^:]*: Assembler messages:
[^:]*:[0-9]+: Error: selected processor does not support system register name 'rctx'
[^:]*:[0-9]+: Error: selected processor does not support `cosp rctx,x1'
[^:]*:[0-9]+: Error: selected processor does not support system register name 'rctx'
[^:]*:[0-9]+: Error: selected processor does not support `cfp rctx,x1'

10
gas/testsuite/gas/aarch64/predres2.d
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@ -0,0 +1,10 @@
#as: -march=armv8-a+predres2
#objdump: -dr
.*: file format .*
Disassembly of section \.text:
0+ <.*>:
.*: d50b73c1 cosp rctx, x1
.*: d50b7381 cfp rctx, x1

4
gas/testsuite/gas/aarch64/predres2.s
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@ -0,0 +1,4 @@
/* File to test the +predres2 option. */
func:
cosp rctx, x1
cfp rctx, x1

5
include/opcode/aarch64.h
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@ -197,6 +197,8 @@ enum aarch64_feature_bit {
AARCH64_FEATURE_S2POE,
/* Extension to Translation Control Registers. */
AARCH64_FEATURE_TCR2,
/* Speculation Prediction Restriction instructions. */
AARCH64_FEATURE_PREDRES2,
AARCH64_NUM_FEATURES
};
@ -276,7 +278,8 @@ enum aarch64_feature_bit {
#define AARCH64_ARCH_V9_1A_FEATURES(X) AARCH64_ARCH_V8_6A_FEATURES (X)
#define AARCH64_ARCH_V9_2A_FEATURES(X) AARCH64_ARCH_V8_7A_FEATURES (X)
#define AARCH64_ARCH_V9_3A_FEATURES(X) AARCH64_ARCH_V8_8A_FEATURES (X)
#define AARCH64_ARCH_V9_4A_FEATURES(X) AARCH64_ARCH_V8_9A_FEATURES (X)
#define AARCH64_ARCH_V9_4A_FEATURES(X) (AARCH64_ARCH_V8_9A_FEATURES (X) \
| AARCH64_FEATBIT (X, PREDRES2))
/* Architectures are the sum of the base and extensions. */
#define AARCH64_ARCH_V8A(X) (AARCH64_FEATBIT (X, V8) \

177
opcodes/aarch64-asm-2.c
View File

@ -426,14 +426,14 @@ aarch64_find_real_opcode (const aarch64_opcode *opcode)
case 1200: /* movz */
value = 1200; /* --> movz. */
break;
case 1275: /* autibsp */
case 1274: /* autibz */
case 1273: /* autiasp */
case 1272: /* autiaz */
case 1271: /* pacibsp */
case 1270: /* pacibz */
case 1269: /* paciasp */
case 1268: /* paciaz */
case 1276: /* autibsp */
case 1275: /* autibz */
case 1274: /* autiasp */
case 1273: /* autiaz */
case 1272: /* pacibsp */
case 1271: /* pacibz */
case 1270: /* paciasp */
case 1269: /* paciaz */
case 1253: /* gcsb */
case 1233: /* clearbhb */
case 1232: /* tsb */
@ -464,6 +464,7 @@ aarch64_find_real_opcode (const aarch64_opcode *opcode)
case 1236: /* dsb */
value = 1236; /* --> dsb. */
break;
case 1264: /* cosp */
case 1263: /* cpp */
case 1262: /* dvp */
case 1261: /* cfp */
@ -480,126 +481,126 @@ aarch64_find_real_opcode (const aarch64_opcode *opcode)
case 1260: /* wfit */
value = 1260; /* --> wfit. */
break;
case 2077: /* bic */
case 1324: /* and */
value = 1324; /* --> and. */
case 2078: /* bic */
case 1325: /* and */
value = 1325; /* --> and. */
break;
case 1307: /* mov */
case 1326: /* and */
value = 1326; /* --> and. */
break;
case 1311: /* movs */
case 1327: /* ands */
value = 1327; /* --> ands. */
case 1308: /* mov */
case 1327: /* and */
value = 1327; /* --> and. */
break;
case 2078: /* cmple */
case 1362: /* cmpge */
value = 1362; /* --> cmpge. */
case 1312: /* movs */
case 1328: /* ands */
value = 1328; /* --> ands. */
break;
case 2081: /* cmplt */
case 1365: /* cmpgt */
value = 1365; /* --> cmpgt. */
case 2079: /* cmple */
case 1363: /* cmpge */
value = 1363; /* --> cmpge. */
break;
case 2079: /* cmplo */
case 1367: /* cmphi */
value = 1367; /* --> cmphi. */
case 2082: /* cmplt */
case 1366: /* cmpgt */
value = 1366; /* --> cmpgt. */
break;
case 2080: /* cmpls */
case 1370: /* cmphs */
value = 1370; /* --> cmphs. */
case 2080: /* cmplo */
case 1368: /* cmphi */
value = 1368; /* --> cmphi. */
break;
case 1304: /* mov */
case 1392: /* cpy */
value = 1392; /* --> cpy. */
case 2081: /* cmpls */
case 1371: /* cmphs */
value = 1371; /* --> cmphs. */
break;
case 1306: /* mov */
case 1305: /* mov */
case 1393: /* cpy */
value = 1393; /* --> cpy. */
break;
case 2088: /* fmov */
case 1309: /* mov */
case 1307: /* mov */
case 1394: /* cpy */
value = 1394; /* --> cpy. */
break;
case 1298: /* mov */
case 1406: /* dup */
value = 1406; /* --> dup. */
case 2089: /* fmov */
case 1310: /* mov */
case 1395: /* cpy */
value = 1395; /* --> cpy. */
break;
case 1301: /* mov */
case 1297: /* mov */
case 1299: /* mov */
case 1407: /* dup */
value = 1407; /* --> dup. */
break;
case 2087: /* fmov */
case 1303: /* mov */
case 1302: /* mov */
case 1298: /* mov */
case 1408: /* dup */
value = 1408; /* --> dup. */
break;
case 1302: /* mov */
case 1409: /* dupm */
value = 1409; /* --> dupm. */
case 2088: /* fmov */
case 1304: /* mov */
case 1409: /* dup */
value = 1409; /* --> dup. */
break;
case 2082: /* eon */
case 1411: /* eor */
value = 1411; /* --> eor. */
case 1303: /* mov */
case 1410: /* dupm */
value = 1410; /* --> dupm. */
break;
case 1312: /* not */
case 1413: /* eor */
value = 1413; /* --> eor. */
case 2083: /* eon */
case 1412: /* eor */
value = 1412; /* --> eor. */
break;
case 1313: /* nots */
case 1414: /* eors */
value = 1414; /* --> eors. */
case 1313: /* not */
case 1414: /* eor */
value = 1414; /* --> eor. */
break;
case 2083: /* facle */
case 1419: /* facge */
value = 1419; /* --> facge. */
case 1314: /* nots */
case 1415: /* eors */
value = 1415; /* --> eors. */
break;
case 2084: /* faclt */
case 1420: /* facgt */
value = 1420; /* --> facgt. */
case 2084: /* facle */
case 1420: /* facge */
value = 1420; /* --> facge. */
break;
case 2085: /* fcmle */
case 1433: /* fcmge */
value = 1433; /* --> fcmge. */
case 2085: /* faclt */
case 1421: /* facgt */
value = 1421; /* --> facgt. */
break;
case 2086: /* fcmlt */
case 1435: /* fcmgt */
value = 1435; /* --> fcmgt. */
case 2086: /* fcmle */
case 1434: /* fcmge */
value = 1434; /* --> fcmge. */
break;
case 1295: /* fmov */
case 1441: /* fcpy */
value = 1441; /* --> fcpy. */
case 2087: /* fcmlt */
case 1436: /* fcmgt */
value = 1436; /* --> fcmgt. */
break;
case 1294: /* fmov */
case 1464: /* fdup */
value = 1464; /* --> fdup. */
case 1296: /* fmov */
case 1442: /* fcpy */
value = 1442; /* --> fcpy. */
break;
case 1296: /* mov */
case 1796: /* orr */
value = 1796; /* --> orr. */
case 1295: /* fmov */
case 1465: /* fdup */
value = 1465; /* --> fdup. */
break;
case 2089: /* orn */
case 1297: /* mov */
case 1797: /* orr */
value = 1797; /* --> orr. */
break;
case 1300: /* mov */
case 1299: /* mov */
case 1799: /* orr */
value = 1799; /* --> orr. */
case 2090: /* orn */
case 1798: /* orr */
value = 1798; /* --> orr. */
break;
case 1310: /* movs */
case 1800: /* orrs */
value = 1800; /* --> orrs. */
case 1301: /* mov */
case 1300: /* mov */
case 1800: /* orr */
value = 1800; /* --> orr. */
break;
case 1305: /* mov */
case 1863: /* sel */
value = 1863; /* --> sel. */
case 1311: /* movs */
case 1801: /* orrs */
value = 1801; /* --> orrs. */
break;
case 1308: /* mov */
case 1306: /* mov */
case 1864: /* sel */
value = 1864; /* --> sel. */
break;
case 1309: /* mov */
case 1865: /* sel */
value = 1865; /* --> sel. */
break;
default: return NULL;
}

3957
opcodes/aarch64-dis-2.c
View File

File diff suppressed because it is too large

16
opcodes/aarch64-opc-2.c
View File

@ -383,18 +383,18 @@ static const unsigned op_enum_table [] =
391,
413,
415,
1299,
1300,
1305,
1297,
1296,
1301,
1308,
1310,
1306,
1298,
1297,
1302,
1309,
1311,
1307,
1313,
1312,
1308,
1314,
1313,
131,
};

7
opcodes/aarch64-tbl.h
View File

@ -2518,6 +2518,8 @@ static const aarch64_feature_set aarch64_feature_sb =
AARCH64_FEATURE (SB);
static const aarch64_feature_set aarch64_feature_predres =
AARCH64_FEATURE (PREDRES);
static const aarch64_feature_set aarch64_feature_predres2 =
AARCH64_FEATURES (2, PREDRES, PREDRES2);
static const aarch64_feature_set aarch64_feature_memtag =
AARCH64_FEATURE (MEMTAG);
static const aarch64_feature_set aarch64_feature_bfloat16 =
@ -2608,6 +2610,7 @@ static const aarch64_feature_set aarch64_feature_gcs =
#define FRINTTS &aarch64_feature_frintts
#define SB &aarch64_feature_sb
#define PREDRES &aarch64_feature_predres
#define PREDRES2 &aarch64_feature_predres2
#define MEMTAG &aarch64_feature_memtag
#define TME &aarch64_feature_tme
#define SVE2 &aarch64_feature_sve2
@ -2841,6 +2844,9 @@ static const aarch64_feature_set aarch64_feature_gcs =
MOPS_SET_OP1_OP2_INSN (NAME, "n", OPCODE | 0x2000, MASK, ISA), \
MOPS_SET_OP1_OP2_INSN (NAME, "tn", OPCODE | 0x3000, MASK, ISA)
#define PREDRES2_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
{ NAME, OPCODE, MASK, CLASS, 0, PREDRES2, OPS, QUALS, FLAGS, 0, 0, NULL }
const struct aarch64_opcode aarch64_opcode_table[] =
{
/* Add/subtract (with carry). */
@ -4185,6 +4191,7 @@ const struct aarch64_opcode aarch64_opcode_table[] =
PREDRES_INSN ("cfp", 0xd50b7380, 0xffffffe0, ic_system, OP2 (SYSREG_SR, Rt), QL_SRC_X, F_ALIAS),
PREDRES_INSN ("dvp", 0xd50b73a0, 0xffffffe0, ic_system, OP2 (SYSREG_SR, Rt), QL_SRC_X, F_ALIAS),
PREDRES_INSN ("cpp", 0xd50b73e0, 0xffffffe0, ic_system, OP2 (SYSREG_SR, Rt), QL_SRC_X, F_ALIAS),
PREDRES2_INSN ("cosp", 0xd50b73c0, 0xffffffe0, ic_system, OP2 (SYSREG_SR, Rt), QL_SRC_X, F_ALIAS),
/* Armv8.4-a flag setting instruction, However this encoding has an encoding clash with the msr
below it. Usually we can resolve this by setting an alias condition on the flags, however that
depends on the disassembly masks to be able to quickly find the alias. The problem is the

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