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include/ * elf/common.h: Add PRU ELF. * elf/pru.h: New file. * opcode/pru.h: New file. * dis-asm.h (print_insn_pru): Declare. bfd/ * archures.c: Add bfd_arch_pru. * Makefile.am: Add PRU target. * config.bfd: Ditto. * configure.ac: Ditto. * elf-bfd.h (enum elf_target_id): Add PRU_ELF_DATA. * targets.c: Add pru_elf32_vec. * reloc.c: Add PRU relocations. * cpu-pru.c: New file. * elf32-pru.c: New file. * Makefile.in: Regenerate. * configure: Regenerate. * po/SRC-POTFILES.in: Regenerate. * bfd-in2.h: Regenerate * libbfd.h: Regenerate. Signed-off-by: Dimitar Dimitrov <dimitar@dinux.eu>gdb-8.0-branch
Dimitar Dimitrov
9 years ago
committed by
Alan Modra
Alan Modra
20 changed files with 2129 additions and 1 deletions
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/* BFD support for the TI PRU microprocessor.
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Copyright (C) 2014-2016 Free Software Foundation, Inc. |
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Contributed by Dimitar Dimitrov <dimitar@dinux.eu> |
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This file is part of BFD, the Binary File Descriptor library. |
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This program is free software; you can redistribute it and/or modify |
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it under the terms of the GNU General Public License as published by |
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the Free Software Foundation; either version 3 of the License, or |
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(at your option) any later version. |
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|
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This program is distributed in the hope that it will be useful, |
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but WITHOUT ANY WARRANTY; without even the implied warranty of |
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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GNU General Public License for more details. |
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|
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You should have received a copy of the GNU General Public License |
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along with this program; if not, write to the Free Software |
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Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, |
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MA 02110-1301, USA. */ |
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#include "sysdep.h" |
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#include "bfd.h" |
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#include "libbfd.h" |
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#define N(BITS_WORD, BITS_ADDR, NUMBER, PRINT, DEFAULT, NEXT) \ |
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{ \ |
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BITS_WORD, /* bits in a word */ \ |
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BITS_ADDR, /* bits in an address */ \ |
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8, /* 8 bits in a byte */ \ |
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bfd_arch_pru, \ |
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NUMBER, \ |
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"pru", \ |
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PRINT, \ |
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3, \ |
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DEFAULT, \ |
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bfd_default_compatible, \ |
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bfd_default_scan, \ |
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bfd_arch_default_fill, \ |
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NEXT \ |
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} |
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const bfd_arch_info_type bfd_pru_arch = N (32, 32, 0, "pru", TRUE, NULL); |
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File diff suppressed because it is too large
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/* TI PRU ELF support for BFD.
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Copyright (C) 2014-2016 Free Software Foundation, Inc. |
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Contributed by Dimitar Dimitrov <dimitar@dinux.eu> |
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This file is part of BFD, the Binary File Descriptor library. |
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This program is free software; you can redistribute it and/or modify |
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it under the terms of the GNU General Public License as published by |
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the Free Software Foundation; either version 3 of the License, or |
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(at your option) any later version. |
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|
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This program is distributed in the hope that it will be useful, |
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but WITHOUT ANY WARRANTY; without even the implied warranty of |
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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GNU General Public License for more details. |
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|
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You should have received a copy of the GNU General Public License |
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along with this program; if not, write to the Free Software |
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Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, |
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MA 02110-1301, USA. */ |
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/* This file holds definitions specific to the TI PRU ELF ABI. Note
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that most of this is not actually implemented by BFD. */ |
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#ifndef _ELF_PRU_H |
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#define _ELF_PRU_H |
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#include "elf/reloc-macros.h" |
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START_RELOC_NUMBERS (elf_pru_reloc_type) |
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RELOC_NUMBER (R_PRU_NONE, 0) |
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RELOC_NUMBER (R_PRU_16_PMEM, 5) |
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RELOC_NUMBER (R_PRU_U16_PMEMIMM, 6) |
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RELOC_NUMBER (R_PRU_BFD_RELOC_16, 8) |
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RELOC_NUMBER (R_PRU_U16, 9) |
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RELOC_NUMBER (R_PRU_32_PMEM, 10) |
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RELOC_NUMBER (R_PRU_BFD_RELOC_32, 11) |
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RELOC_NUMBER (R_PRU_S10_PCREL, 14) |
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RELOC_NUMBER (R_PRU_U8_PCREL, 15) |
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RELOC_NUMBER (R_PRU_LDI32, 18) |
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/* Extensions required by GCC, or simply nice to have. */ |
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RELOC_NUMBER (R_PRU_GNU_BFD_RELOC_8, 64) |
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RELOC_NUMBER (R_PRU_GNU_DIFF8, 65) |
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RELOC_NUMBER (R_PRU_GNU_DIFF16, 66) |
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RELOC_NUMBER (R_PRU_GNU_DIFF32, 67) |
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RELOC_NUMBER (R_PRU_GNU_DIFF16_PMEM, 68) |
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RELOC_NUMBER (R_PRU_GNU_DIFF32_PMEM, 69) |
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RELOC_NUMBER (R_PRU_ILLEGAL, 70) |
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END_RELOC_NUMBERS (R_PRU_maxext) |
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/* Processor-specific section flags. */ |
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#endif /* _ELF_PRU_H */ |
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/* TI PRU opcode list for GAS, the GNU assembler.
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Copyright (C) 2014-2016 Free Software Foundation, Inc. |
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Contributed by Dimitar Dimitrov <dimitar@dinux.eu> |
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This file is part of GAS, the GNU Assembler, and GDB, the GNU disassembler. |
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GAS/GDB is free software; you can redistribute it and/or modify |
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it under the terms of the GNU General Public License as published by |
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the Free Software Foundation; either version 3, or (at your option) |
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any later version. |
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|
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GAS/GDB is distributed in the hope that it will be useful, |
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but WITHOUT ANY WARRANTY; without even the implied warranty of |
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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GNU General Public License for more details. |
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|
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You should have received a copy of the GNU General Public License |
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along with GAS or GDB; see the file COPYING3. If not, write to |
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the Free Software Foundation, 51 Franklin Street - Fifth Floor, |
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Boston, MA 02110-1301, USA. */ |
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#ifndef _PRU_H_ |
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#define _PRU_H_ |
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#include "bfd.h" |
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/****************************************************************************
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* This file contains structures, bit masks and shift counts used |
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* by the GNU toolchain to define the PRU instruction set and |
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* access various opcode fields. |
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****************************************************************************/ |
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/* Identify different overflow situations for error messages. */ |
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enum overflow_type |
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{ |
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call_target_overflow = 0, |
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qbranch_target_overflow, |
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address_offset_overflow, |
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signed_immed16_overflow, |
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unsigned_immed32_overflow, |
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unsigned_immed16_overflow, |
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unsigned_immed8_overflow, |
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unsigned_immed5_overflow, |
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no_overflow |
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}; |
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enum opcode_format_type { |
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opcode_format1, |
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opcode_format2ab, |
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opcode_format2abl, |
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opcode_format2c, |
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opcode_format2de, |
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opcode_format45, |
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opcode_format6 |
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}; |
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/* Opcode ID listing. Used for indexing by the simulator. */ |
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enum pru_instr_type { |
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prui_add, prui_adc, prui_sub, prui_suc, prui_lsl, prui_lsr, prui_rsb, |
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prui_rsc, prui_and, prui_or, prui_xor, prui_min, prui_max, prui_clr, |
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prui_set, prui_not, prui_jmp, prui_jal, prui_ldi, prui_halt, prui_slp, |
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prui_xin, prui_xout, prui_xchg, prui_sxin, prui_sxout, prui_sxchg, |
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prui_loop, prui_iloop, prui_qbgt, prui_qbge, prui_qblt, prui_qble, |
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prui_qbeq, prui_qbne, prui_qba, prui_qbbs, prui_qbbc, prui_lbbo, |
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prui_sbbo, prui_lbco, prui_sbco |
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}; |
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/* This structure holds information for a particular instruction.
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The args field is a string describing the operands. The following |
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letters can appear in the args: |
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b - a 5.3-bit right source register index OR 8-bit unsigned immediate |
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B - same as 'b', but for LOOP instruction where IMM is decremented |
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c - a 5 bit unsigned immediate for constant table offset |
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d - a 5.3-bit destination register index |
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D - a 5.2-bit destination register index |
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E - for internal GAS self-tests only |
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i - a 32-bit immediate or label |
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j - a 5.3-bit right source register index OR 18-bit PC address |
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l - burst length (unsigned 7-bit immediate or r0.b[0-3]) for xLBCO |
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n - burst length (unsigned 7-bit immediate or r0.b[0-3]) for XFR |
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o - a 10-bit signed PC-relative offset |
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O - an 8-bit unsigned PC-relative offset for LOOP termination point |
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R - a 5-bit destination register index |
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s - a 5.3-bit left source register index |
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S - a 5-bit left source register index |
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w - a single bit for "WakeOnStatus" |
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W - a 16-bit unsigned immediate with IO=0 field (LDI) |
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x - an 8-bit XFR wide-bus address immediate |
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Literal ',' character may also appear in the args as delimiter. |
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Most of the macro names are from [1]. |
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The pinfo field is INSN_MACRO for a macro. Otherwise, it is a collection |
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of bits describing the instruction, notably any relevant hazard |
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information. |
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When assembling, the match field contains the opcode template, which |
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is modified by the arguments to produce the actual opcode |
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that is emitted. If pinfo is INSN_MACRO, then this is 0. |
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If pinfo is INSN_MACRO, the mask field stores the macro identifier. |
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Otherwise this is a bit mask for the relevant portions of the opcode |
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when disassembling. If the actual opcode anded with the match field |
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equals the opcode field, then we have found the correct instruction. |
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[1] http://processors.wiki.ti.com/index.php/Programmable_Realtime_Unit */
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struct pru_opcode |
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{ |
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const char *name; /* The name of the instruction. */ |
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enum pru_instr_type type; /* Instruction type. Used for fast indexing
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by the simulator. */ |
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const char *args; /* A string describing the arguments for this
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instruction. */ |
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unsigned long match; /* The basic opcode for the instruction. */ |
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unsigned long mask; /* Mask for the opcode field of the
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instruction. */ |
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unsigned long pinfo; /* Is this a real instruction or instruction
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macro? */ |
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enum overflow_type overflow_msg; /* Used to generate informative
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message when fixup overflows. */ |
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}; |
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/* This value is used in the pru_opcode.pinfo field to indicate that the
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instruction is a macro or pseudo-op. This requires special treatment by |
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the assembler, and is used by the disassembler to determine whether to |
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check for a nop. */ |
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#define PRU_INSN_MACRO 0x80000000 |
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/* This macro is specially handled throughout the code because it is
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the only insn to output 2 words (64 bits). */ |
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#define PRU_INSN_LDI32 0x40000000 |
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/* Associates a register name with a 5-bit index and 3-bit regsel. */ |
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struct pru_reg |
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{ |
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const char *name; /* Name, e.g. "r10". */ |
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const unsigned int index; /* Index, e.g. 10. */ |
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const unsigned int regsel; /* Register field selector, .e.g RSEL_31_0. */ |
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}; |
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/* Macros for getting and setting an instruction field. */ |
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#define GET_INSN_FIELD(X, i) \ |
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(((i) & OP_MASK_##X) >> OP_SH_##X) |
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#define SET_INSN_FIELD(X, i, v) \ |
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((i) = (((i) & ~OP_MASK_##X) | (((v) << OP_SH_##X) & OP_MASK_##X))) |
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#define CHECK_INSN_FIELD(X, i) \ |
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(((i) & OP_MASK_##X) == OP_MATCH_##X) |
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/* Masks, values, shifts and macros for accessing the various opcode fields. */ |
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#define OP_SH_FMT1_OP 29 |
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#define OP_MASK_FMT1_OP (0x7u << 29) |
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#define OP_MATCH_FMT1_OP (0x0u << 29) |
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#define OP_SH_FMT2_OP 29 |
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#define OP_MASK_FMT2_OP (0x7u << 29) |
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#define OP_MATCH_FMT2_OP (0x1u << 29) |
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#define OP_SH_FMT4_OP 30 |
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#define OP_MASK_FMT4_OP (0x3u << 30) |
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#define OP_MATCH_FMT4_OP (0x1u << 30) |
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#define OP_SH_FMT5_OP 29 |
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#define OP_MASK_FMT5_OP (0x7u << 29) |
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#define OP_MATCH_FMT5_OP (0x6u << 29) |
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#define OP_SH_FMT6AB_OP 29 |
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#define OP_MASK_FMT6AB_OP (0x7u << 29) |
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#define OP_MATCH_FMT6AB_OP (0x7u << 29) |
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#define OP_SH_FMT6CD_OP 29 |
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#define OP_MASK_FMT6CD_OP (0x7u << 29) |
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#define OP_MATCH_FMT6CD_OP (0x4u << 29) |
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/* Generic fields. */ |
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#define OP_SH_SUBOP 25 |
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#define OP_MASK_SUBOP (0xfu << 25) |
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#define OP_SH_IO 24 |
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#define OP_MASK_IO (0x1u << 24) |
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#define OP_SH_RS2SEL 21 |
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#define OP_MASK_RS2SEL (0x7u << 21) |
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#define OP_SH_RS2 16 |
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#define OP_MASK_RS2 (0x1fu << 16) |
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#define OP_SH_RS1SEL 13 |
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#define OP_MASK_RS1SEL (0x7u << 13) |
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#define OP_SH_RS1 8 |
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#define OP_MASK_RS1 (0x1fu << 8) |
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#define OP_SH_RDSEL 5 |
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#define OP_MASK_RDSEL (0x7u << 5) |
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#define OP_SH_RD 0 |
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#define OP_MASK_RD (0x1fu << 0) |
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#define OP_SH_IMM8 16 |
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#define OP_MASK_IMM8 (0xffu << 16) |
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#define OP_SH_IMM16 8 |
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#define OP_MASK_IMM16 (0xffffu << 8) |
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#define RSEL_7_0 0u |
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#define RSEL_15_8 1u |
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#define RSEL_23_16 2u |
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#define RSEL_31_24 3u |
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#define RSEL_15_0 4u |
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#define RSEL_23_8 5u |
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#define RSEL_31_16 6u |
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#define RSEL_31_0 7u |
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#define RSEL_NUM_ITEMS 8u |
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/* Format 1 specific fields. */ |
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#define SUBOP_ADD 0u |
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#define SUBOP_ADC 1u |
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#define SUBOP_SUB 2u |
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#define SUBOP_SUC 3u |
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#define SUBOP_LSL 4u |
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#define SUBOP_LSR 5u |
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#define SUBOP_RSB 6u |
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#define SUBOP_RSC 7u |
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#define SUBOP_AND 8u |
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#define SUBOP_OR 9u |
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#define SUBOP_XOR 10u |
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#define SUBOP_NOT 11u |
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#define SUBOP_MIN 12u |
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#define SUBOP_MAX 13u |
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#define SUBOP_CLR 14u |
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#define SUBOP_SET 15u |
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/* Format 2 specific fields. */ |
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#define SUBOP_JMP 0u |
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#define SUBOP_JAL 1u |
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#define SUBOP_LDI 2u |
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#define SUBOP_LMBD 3u |
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#define SUBOP_SCAN 4u |
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#define SUBOP_HALT 5u |
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#define SUBOP_RSVD_FOR_MVIx 6u |
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#define SUBOP_XFR 7u |
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#define SUBOP_LOOP 8u |
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#define SUBOP_RSVD_FOR_RFI 14u |
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#define SUBOP_SLP 15u |
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#define OP_SH_WAKEONSTATUS 23 |
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#define OP_MASK_WAKEONSTATUS (0x1u << 23) |
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/* Format 2 XFR specific fields. */ |
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#define OP_SH_SUBOP_XFR 23 |
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#define OP_MASK_SUBOP_XFR (3u << 23) |
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#define OP_SH_XFR_WBA 15 |
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#define OP_MASK_XFR_WBA (0xffu << 15) |
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#define OP_SH_XFR_S 14 |
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#define OP_MASK_XFR_S (1u << 14) |
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#define OP_SH_XFR_LENGTH 7 |
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#define OP_MASK_XFR_LENGTH (0x7fu << 7) |
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#define SUBOP_XFR_XIN 1u |
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#define SUBOP_XFR_XOUT 2u |
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#define SUBOP_XFR_XCHG 3u |
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/* Format 2 LOOP specific fields. */ |
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#define OP_SH_LOOP_INTERRUPTIBLE 15 |
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#define OP_MASK_LOOP_INTERRUPTIBLE (1u << 15) |
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#define OP_SH_LOOP_JMPOFFS 0 |
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#define OP_MASK_LOOP_JMPOFFS (0xffu << 0) |
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/* Format 4 specific fields. */ |
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#define OP_SH_BROFF98 25 |
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#define OP_MASK_BROFF98 (0x3u << 25) |
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#define OP_SH_BROFF70 0 |
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#define OP_MASK_BROFF70 (0xffu << 0) |
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#define OP_SH_GT 29 |
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#define OP_MASK_GT (0x1u << 29) |
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#define OP_SH_EQ 28 |
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#define OP_MASK_EQ (0x1u << 28) |
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#define OP_SH_LT 27 |
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#define OP_MASK_LT (0x1u << 27) |
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#define OP_MASK_CMP (OP_MASK_GT | OP_MASK_EQ | OP_MASK_LT) |
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/* Format 5 specific fields. */ |
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#define OP_SH_BS 28 |
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#define OP_MASK_BS (0x1u << 28) |
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#define OP_SH_BC 27 |
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#define OP_MASK_BC (0x1u << 27) |
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#define OP_MASK_BCMP (OP_MASK_BS | OP_MASK_BC) |
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|
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/* Format 6 specific fields. */ |
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#define OP_SH_LOADSTORE 28 |
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#define OP_MASK_LOADSTORE (0x1u << 28) |
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#define OP_SH_BURSTLEN64 25 |
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#define OP_MASK_BURSTLEN64 (0x7u << 25) |
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#define OP_SH_BURSTLEN31 13 |
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#define OP_MASK_BURSTLEN31 (0x7u << 13) |
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#define OP_SH_CB 8 |
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#define OP_MASK_CB (0x1fu << 8) |
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#define OP_SH_BURSTLEN0 7 |
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#define OP_MASK_BURSTLEN0 (0x1u << 7) |
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#define OP_SH_RDB 5 |
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#define OP_MASK_RDB (0x3u << 5) |
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#define LSSBBO_BYTECOUNT_R0_BITS7_0 124u |
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#define LSBBO_BYTECOUNT_R0_BITS15_8 125u |
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#define LSBBO_BYTECOUNT_R0_BITS23_16 126u |
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#define LSBBO_BYTECOUNT_R0_BITS31_24 127u |
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/* The following macros define the opcode matches for each
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instruction code & OP_MASK_INST == OP_MATCH_INST. */ |
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#define OP_MATCH_ADD (OP_MATCH_FMT1_OP | (SUBOP_ADD << OP_SH_SUBOP)) |
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#define OP_MATCH_ADC (OP_MATCH_FMT1_OP | (SUBOP_ADC << OP_SH_SUBOP)) |
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#define OP_MATCH_SUB (OP_MATCH_FMT1_OP | (SUBOP_SUB << OP_SH_SUBOP)) |
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#define OP_MATCH_SUC (OP_MATCH_FMT1_OP | (SUBOP_SUC << OP_SH_SUBOP)) |
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#define OP_MATCH_LSL (OP_MATCH_FMT1_OP | (SUBOP_LSL << OP_SH_SUBOP)) |
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#define OP_MATCH_LSR (OP_MATCH_FMT1_OP | (SUBOP_LSR << OP_SH_SUBOP)) |
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#define OP_MATCH_RSB (OP_MATCH_FMT1_OP | (SUBOP_RSB << OP_SH_SUBOP)) |
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#define OP_MATCH_RSC (OP_MATCH_FMT1_OP | (SUBOP_RSC << OP_SH_SUBOP)) |
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#define OP_MATCH_AND (OP_MATCH_FMT1_OP | (SUBOP_AND << OP_SH_SUBOP)) |
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#define OP_MATCH_OR (OP_MATCH_FMT1_OP | (SUBOP_OR << OP_SH_SUBOP)) |
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#define OP_MATCH_XOR (OP_MATCH_FMT1_OP | (SUBOP_XOR << OP_SH_SUBOP)) |
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#define OP_MATCH_NOT (OP_MATCH_FMT1_OP | (SUBOP_NOT << OP_SH_SUBOP)) |
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#define OP_MATCH_MIN (OP_MATCH_FMT1_OP | (SUBOP_MIN << OP_SH_SUBOP)) |
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#define OP_MATCH_MAX (OP_MATCH_FMT1_OP | (SUBOP_MAX << OP_SH_SUBOP)) |
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#define OP_MATCH_CLR (OP_MATCH_FMT1_OP | (SUBOP_CLR << OP_SH_SUBOP)) |
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#define OP_MATCH_SET (OP_MATCH_FMT1_OP | (SUBOP_SET << OP_SH_SUBOP)) |
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#define OP_MATCH_JMP (OP_MATCH_FMT2_OP | (SUBOP_JMP << OP_SH_SUBOP)) |
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#define OP_MATCH_JAL (OP_MATCH_FMT2_OP | (SUBOP_JAL << OP_SH_SUBOP)) |
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#define OP_MATCH_LDI (OP_MATCH_FMT2_OP | (SUBOP_LDI << OP_SH_SUBOP)) |
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#define OP_MATCH_LMBD (OP_MATCH_FMT2_OP | (SUBOP_LMBD << OP_SH_SUBOP)) |
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#define OP_MATCH_SCAN (OP_MATCH_FMT2_OP | (SUBOP_SCAN << OP_SH_SUBOP)) |
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#define OP_MATCH_HALT (OP_MATCH_FMT2_OP | (SUBOP_HALT << OP_SH_SUBOP)) |
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#define OP_MATCH_SLP (OP_MATCH_FMT2_OP | (SUBOP_SLP << OP_SH_SUBOP)) |
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#define OP_MATCH_XFR (OP_MATCH_FMT2_OP | (SUBOP_XFR << OP_SH_SUBOP)) |
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#define OP_MATCH_SXFR (OP_MATCH_XFR | OP_MASK_XFR_S) |
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#define OP_MATCH_XIN (OP_MATCH_XFR | (SUBOP_XFR_XIN << OP_SH_SUBOP_XFR)) |
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#define OP_MATCH_XOUT (OP_MATCH_XFR | (SUBOP_XFR_XOUT << OP_SH_SUBOP_XFR)) |
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#define OP_MATCH_XCHG (OP_MATCH_XFR | (SUBOP_XFR_XCHG << OP_SH_SUBOP_XFR)) |
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#define OP_MATCH_SXIN (OP_MATCH_SXFR | (SUBOP_XFR_XIN << OP_SH_SUBOP_XFR)) |
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#define OP_MATCH_SXOUT (OP_MATCH_SXFR | (SUBOP_XFR_XOUT << OP_SH_SUBOP_XFR)) |
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#define OP_MATCH_SXCHG (OP_MATCH_SXFR | (SUBOP_XFR_XCHG << OP_SH_SUBOP_XFR)) |
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#define OP_MATCH_LOOP (OP_MATCH_FMT2_OP | (SUBOP_LOOP << OP_SH_SUBOP)) |
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#define OP_MATCH_ILOOP (OP_MATCH_FMT2_OP | (SUBOP_LOOP << OP_SH_SUBOP) \ |
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| OP_MASK_LOOP_INTERRUPTIBLE) |
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|
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#define OP_MATCH_QBGT (OP_MATCH_FMT4_OP | OP_MASK_GT) |
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#define OP_MATCH_QBGE (OP_MATCH_FMT4_OP | OP_MASK_GT | OP_MASK_EQ) |
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#define OP_MATCH_QBLT (OP_MATCH_FMT4_OP | OP_MASK_LT) |
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#define OP_MATCH_QBLE (OP_MATCH_FMT4_OP | OP_MASK_LT | OP_MASK_EQ) |
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#define OP_MATCH_QBEQ (OP_MATCH_FMT4_OP | OP_MASK_EQ) |
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#define OP_MATCH_QBNE (OP_MATCH_FMT4_OP | OP_MASK_GT | OP_MASK_LT) |
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#define OP_MATCH_QBA (OP_MATCH_FMT4_OP | OP_MASK_GT | OP_MASK_LT \ |
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| OP_MASK_EQ) |
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|
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#define OP_MATCH_QBBS (OP_MATCH_FMT5_OP | OP_MASK_BS) |
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#define OP_MATCH_QBBC (OP_MATCH_FMT5_OP | OP_MASK_BC) |
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|
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#define OP_MATCH_LBBO (OP_MATCH_FMT6AB_OP | OP_MASK_LOADSTORE) |
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#define OP_MATCH_SBBO (OP_MATCH_FMT6AB_OP) |
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#define OP_MATCH_LBCO (OP_MATCH_FMT6CD_OP | OP_MASK_LOADSTORE) |
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#define OP_MATCH_SBCO (OP_MATCH_FMT6CD_OP) |
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|
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/* Some special extractions. */ |
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#define OP_MASK_BROFF (OP_MASK_BROFF98 | OP_MASK_BROFF70) |
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|
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#define GET_BROFF_URAW(i) \ |
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((GET_INSN_FIELD (BROFF98, i) << 8) | (GET_INSN_FIELD (BROFF70, i) << 0)) |
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|
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#define GET_BROFF_SIGNED(i) \ |
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((long)(GET_BROFF_URAW (i) - (!!(GET_BROFF_URAW (i) & (1 << 9)) << 10))) |
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|
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#define SET_BROFF_URAW(i, v) \ |
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do { \ |
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SET_INSN_FIELD (BROFF98, (i), (v) >> 8); \ |
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SET_INSN_FIELD (BROFF70, (i), (v) & 0xff); \ |
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} while (0) |
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|
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#define GET_BURSTLEN(i) \ |
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( (GET_INSN_FIELD (BURSTLEN64, (i)) << 4) | \ |
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(GET_INSN_FIELD (BURSTLEN31, (i)) << 1) | \ |
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(GET_INSN_FIELD (BURSTLEN0, (i)) << 0)) |
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|
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#define SET_BURSTLEN(i, v) \ |
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do { \ |
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SET_INSN_FIELD (BURSTLEN64, (i), (v) >> 4); \ |
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SET_INSN_FIELD (BURSTLEN31, (i), (v) >> 1); \ |
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SET_INSN_FIELD (BURSTLEN0, (i), (v) >> 0); \ |
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} while (0) |
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|
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/* Miscellaneous helpers. */ |
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#define OP_MASK_XFR_OP (OP_MASK_FMT2_OP | OP_MASK_SUBOP \ |
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| OP_MASK_SUBOP_XFR | OP_MASK_XFR_S) |
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|
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#define OP_MASK_LOOP_OP (OP_MASK_FMT2_OP | OP_MASK_SUBOP \ |
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| OP_MASK_LOOP_INTERRUPTIBLE) |
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|
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/* These are the data structures we use to hold the instruction information. */ |
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extern const struct pru_opcode pru_opcodes[]; |
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extern const int bfd_pru_num_opcodes; |
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|
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/* These are the data structures used to hold the register information. */ |
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extern const struct pru_reg pru_regs[]; |
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extern const int pru_num_regs; |
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|
|||
/* Machine-independent macro for number of opcodes. */ |
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#define NUMOPCODES bfd_pru_num_opcodes |
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#define NUMREGISTERS pru_num_regs; |
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|
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/* This is made extern so that the assembler can use it to find out
|
|||
what instruction caused an error. */ |
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extern const struct pru_opcode *pru_find_opcode (unsigned long); |
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|
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#endif /* _PRU_H */ |
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Loading…
Reference in new issue