aarch64: Remove support for CSRE

This patch removes support for the CSRE extension from aarch64 gas/objdump. CSRE (FEAT_CSRE) is part of the Future Architecture Technologies program and at this time Arm is withdrawing this particular feature. The patch removes the system registers and the CSR PDEC instruction. gas/ChangeLog * NEWS: Remove CSRE. * config/tc-aarch64.c (parse_csr_operand): Delete. (parse_operands): Delete handling of AARCH64_OPND_CSRE_CSR. (aarch64_features): Remove csre. * doc/c-aarch64.texi: Remove CSRE. * testsuite/gas/aarch64/csre.d: Delete. * testsuite/gas/aarch64/csre-invalid.s: Likewise. * testsuite/gas/aarch64/csre-invalid.d: Likewise. * testsuite/gas/aarch64/csre_csr.s: Likewise. * testsuite/gas/aarch64/csre_csr.d: Likewise. * testsuite/gas/aarch64/csre_csr-invalid.s: Likewise. * testsuite/gas/aarch64/csre_csr-invalid.l: Likewise. * testsuite/gas/aarch64/csre_csr-invalid.d: Likewise. include/ChangeLog * opcode/aarch64.h (AARCH64_FEATURE_CSRE): Delete. (aarch64_opnd): Delete AARCH64_OPND_CSRE_CSR. opcodes/ChangeLog * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Likewise. * aarch64-opc-2.c: Likewise. * aarch64-opc.c (aarch64_print_operand): Delete handling of AARCH64_OPND_CSRE_CSR. * aarch64-tbl.h (aarch64_feature_csre): Delete. (CSRE): Likewise. (_CSRE_INSN): Likewise. (aarch64_opcode_table): Delete csr.
5 years ago · 82c70b08df
20 changed files with 1457 additions and 1535 deletions
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@ -1,3 +1,20 @@
+2021-10-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	* NEWS: Remove CSRE.
+	* config/tc-aarch64.c (parse_csr_operand): Delete.
+	(parse_operands): Delete handling of
+	AARCH64_OPND_CSRE_CSR.
+	(aarch64_features): Remove csre.
+	* doc/c-aarch64.texi: Remove CSRE.
+	* testsuite/gas/aarch64/csre.d: Delete.
+	* testsuite/gas/aarch64/csre-invalid.s: Likewise.
+	* testsuite/gas/aarch64/csre-invalid.d: Likewise.
+	* testsuite/gas/aarch64/csre_csr.s: Likewise.
+	* testsuite/gas/aarch64/csre_csr.d: Likewise.
+	* testsuite/gas/aarch64/csre_csr-invalid.s: Likewise.
+	* testsuite/gas/aarch64/csre_csr-invalid.l: Likewise.
+	* testsuite/gas/aarch64/csre_csr-invalid.d: Likewise.
+
 2021-01-11  Nick Clifton  <nickc@redhat.com>

 	* po/uk.po: Updated Ukranian translation.
--- a/gas/NEWS
+++ b/gas/NEWS
@ -18,18 +18,14 @@ Changes in 2.36:
  Add support for Cortex-R82, Neoverse V1, and Neoverse N2 for ARM.

 * Add support for ETMv4 (Embedded Trace Macrocell), ETE (Embedded Trace
-  Extension), TRBE (Trace Buffer Extension), CSRE (Call Stack Recorder
-  Extension) and BRBE (Branch Record Buffer Extension) system registers for
-  AArch64.
+  Extension), TRBE (Trace Buffer Extension)and BRBE (Branch Record Buffer
+  Extension) system registers for AArch64.

 * Add support for Armv8-R and Armv8.7-A AArch64.

 * Add support for DSB memory nXS barrier, WFET and WFIT instruction for Armv8.7
  AArch64.

-* Add support for +csre feature for -march. Add CSR PDEC instruction for CSRE
-  feature in AArch64.
-
 * Add support for +flagm feature for -march in Armv8.4 AArch64.

 * Add support for +ls64 feature for -march in Armv8.7 AArch64. Add atomic
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@ -4036,29 +4036,6 @@ parse_barrier_psb (char **str,
  return 0;
 }

-/* Parse an operand for CSR (CSRE instruction).  */
-
-static int
-parse_csr_operand (char **str)
-{
-  char *p, *q;
-
-  p = q = *str;
-  while (ISALPHA (*q))
-    q++;
-
-  /* Instruction has only one operand PDEC which encodes Rt field of the
-     operation to 0b11111.  */
-  if (strcasecmp(p, "pdec"))
-  {
-    set_syntax_error (_("CSR instruction accepts only PDEC"));
-    return PARSE_FAIL;
-  }
-
-  *str = q;
-  return 0;
-}
-
 /* Parse an operand for BTI.  Set *HINT_OPT to the hint-option record
   return 0 if successful.  Otherwise return PARSE_FAIL.  */

@ -6793,12 +6770,6 @@ parse_operands (char *str, const aarch64_opcode *opcode)
 	    goto failure;
 	  break;

-	case AARCH64_OPND_CSRE_CSR:
-	  val = parse_csr_operand (&str);
-	  if (val == PARSE_FAIL)
-	    goto failure;
-	  break;
-
 	default:
 	  as_fatal (_("unhandled operand code %d"), operands[i]);
 	}
@ -9230,8 +9201,6 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
 			AARCH64_FEATURE (AARCH64_FEATURE_SVE, 0)},
  {"f64mm",		AARCH64_FEATURE (AARCH64_FEATURE_F64MM, 0),
 			AARCH64_FEATURE (AARCH64_FEATURE_SVE, 0)},
-  {"csre",		AARCH64_FEATURE (AARCH64_FEATURE_CSRE, 0),
-			AARCH64_ARCH_NONE},
  {"ls64",		AARCH64_FEATURE (AARCH64_FEATURE_LS64, 0),
 			AARCH64_ARCH_NONE},
  {"flagm",		AARCH64_FEATURE (AARCH64_FEATURE_FLAGM, 0),
--- a/gas/doc/c-aarch64.texi
+++ b/gas/doc/c-aarch64.texi
@ -229,8 +229,6 @@ automatically cause those extensions to be disabled.
 @tab Enable SVE2 SHA3 Extension.
@item @code{flagm} @tab ARMv8-A @tab ARMv8.4-A or later
 @tab Enable Flag Manipulation instructions.
-@item @code{csre} @tab ARMv8-A @tab No
- @tab Enable Call Stack Recorder Extension.
@item @code{ls64} @tab ARMv8.6-A @tab ARMv8.7-A or later
 @tab Enable 64 Byte Loads/Stores.
@item @code{pauth} @tab ARMv8-A @tab No
--- a/gas/testsuite/gas/aarch64/csre-invalid.d
+++ b/gas/testsuite/gas/aarch64/csre-invalid.d
@ -1,3 +0,0 @@
-#name: Invalid CSRE System registers usage
-#source: csre-invalid.s
-#warning_output: csre-invalid.l
--- a/gas/testsuite/gas/aarch64/csre-invalid.s
+++ b/gas/testsuite/gas/aarch64/csre-invalid.s
@ -1,6 +0,0 @@
-/* Write to read-only CSRE system registers.  */
-
-msr csridr_el0 ,x0
-msr csrptridx_el0 ,x0
-msr csrptridx_el1 ,x0
-msr csrptridx_el2 ,x0
--- a/gas/testsuite/gas/aarch64/csre.d
+++ b/gas/testsuite/gas/aarch64/csre.d
@ -1,29 +0,0 @@
-#name: CSRE System registers
-#objdump: -dr
-
-.*:     file format .*
-
-
-Disassembly of section \.text:
-
-0+ <.*>:
-[^:]+:	d5338000 	mrs	x0, csrcr_el0
-[^:]+:	d5338020 	mrs	x0, csrptr_el0
-[^:]+:	d5338040 	mrs	x0, csridr_el0
-[^:]+:	d5338060 	mrs	x0, csrptridx_el0
-[^:]+:	d5308000 	mrs	x0, csrcr_el1
-[^:]+:	d5358000 	mrs	x0, csrcr_el12
-[^:]+:	d5308020 	mrs	x0, csrptr_el1
-[^:]+:	d5358020 	mrs	x0, csrptr_el12
-[^:]+:	d5308060 	mrs	x0, csrptridx_el1
-[^:]+:	d5348000 	mrs	x0, csrcr_el2
-[^:]+:	d5348020 	mrs	x0, csrptr_el2
-[^:]+:	d5348060 	mrs	x0, csrptridx_el2
-[^:]+:	d5138000 	msr	csrcr_el0, x0
-[^:]+:	d5138020 	msr	csrptr_el0, x0
-[^:]+:	d5108000 	msr	csrcr_el1, x0
-[^:]+:	d5158000 	msr	csrcr_el12, x0
-[^:]+:	d5108020 	msr	csrptr_el1, x0
-[^:]+:	d5158020 	msr	csrptr_el12, x0
-[^:]+:	d5148000 	msr	csrcr_el2, x0
-[^:]+:	d5148020 	msr	csrptr_el2, x0
--- a/gas/testsuite/gas/aarch64/csre_csr-invalid.d
+++ b/gas/testsuite/gas/aarch64/csre_csr-invalid.d
@ -1,3 +0,0 @@
-#name: CSR PDEC instruction
-#source: csre_csr-invalid.s
-#error_output: csre_csr-invalid.l
--- a/gas/testsuite/gas/aarch64/csre_csr-invalid.l
+++ b/gas/testsuite/gas/aarch64/csre_csr-invalid.l
@ -1,2 +0,0 @@
-.*: Assembler messages:
-.*: Error: selected processor does not support `csr pdec'
--- a/gas/testsuite/gas/aarch64/csre_csr-invalid.s
+++ b/gas/testsuite/gas/aarch64/csre_csr-invalid.s
@ -1,4 +0,0 @@
-/* CSR PDEC requires +csre for -march= command line option.   */
-.arch armv8-a
-
-    csr pdec
--- a/gas/testsuite/gas/aarch64/csre_csr.d
+++ b/gas/testsuite/gas/aarch64/csre_csr.d
@ -1,10 +0,0 @@
-#name: CSRE extension CSR PDEC instruction
-#objdump: -dr
-
-.*:     file format .*
-
-Disassembly of section \.text:
-
-0+ <.*>:
-.*:	d50b721f 	csr	pdec
-.*:	d50b721f 	csr	pdec
--- a/gas/testsuite/gas/aarch64/csre_csr.s
+++ b/gas/testsuite/gas/aarch64/csre_csr.s
@ -1,4 +0,0 @@
-.arch armv8-a+csre
-
-    csr pdec
-    CSR PDEC
--- a/include/ChangeLog
+++ b/include/ChangeLog
@ -1,3 +1,8 @@
+2021-01-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	* opcode/aarch64.h (AARCH64_FEATURE_CSRE): Delete.
+	(aarch64_opnd): Delete AARCH64_OPND_CSRE_CSR.
+
 2021-01-09  Nick Clifton  <nickc@redhat.com>

 	* 2.36 release branch crated.
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@ -51,7 +51,6 @@ typedef uint32_t aarch64_insn;
 #define AARCH64_FEATURE_V8_4	     (1ULL << 11) /* ARMv8.4 processors.  */
 #define AARCH64_FEATURE_V8_R	     (1ULL << 12) /* Armv8-R processors.  */
 #define AARCH64_FEATURE_V8_7	     (1ULL << 13) /* Armv8.7 processors.  */
-#define AARCH64_FEATURE_CSRE	     (1ULL << 14) /* CSRE feature.  */
 #define AARCH64_FEATURE_LS64	     (1ULL << 15) /* Atomic 64-byte load/store.  */
 #define AARCH64_FEATURE_PAC	     (1ULL << 16) /* v8.3 Pointer Authentication.  */
 #define AARCH64_FEATURE_FP	     (1ULL << 17) /* FP instructions.  */
@ -440,7 +439,6 @@ enum aarch64_opnd
  AARCH64_OPND_SVE_ZtxN,	/* SVE vector register list in Zt.  */
  AARCH64_OPND_TME_UIMM16,	/* TME unsigned 16-bit immediate.  */
  AARCH64_OPND_SM3_IMM2,	/* SM3 encodes lane in bits [13, 14].  */
-  AARCH64_OPND_CSRE_CSR,	/* CSRE CSR instruction Rt field.  */
 };

 /* Qualifier constrains an operand.  It either specifies a variant of an
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@ -1,3 +1,15 @@
+2021-01-11  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+	* aarch64-asm-2.c: Regenerate.
+	* aarch64-dis-2.c: Likewise.
+	* aarch64-opc-2.c: Likewise.
+	* aarch64-opc.c (aarch64_print_operand):
+	Delete handling of AARCH64_OPND_CSRE_CSR.
+	* aarch64-tbl.h (aarch64_feature_csre): Delete.
+	(CSRE): Likewise.
+	(_CSRE_INSN): Likewise.
+	(aarch64_opcode_table): Delete csr.
+
 2021-01-11  Nick Clifton  <nickc@redhat.com>

 	* po/de.po: Updated German translation.
--- a/opcodes/aarch64-asm-2.c
+++ b/opcodes/aarch64-asm-2.c
@ -426,177 +426,177 @@ aarch64_find_real_opcode (const aarch64_opcode *opcode)
    case 1188:	/* movz */
      value = 1188;	/* --> movz.  */
      break;
-    case 1247:	/* autibsp */
-    case 1246:	/* autibz */
-    case 1245:	/* autiasp */
-    case 1244:	/* autiaz */
-    case 1243:	/* pacibsp */
-    case 1242:	/* pacibz */
-    case 1241:	/* paciasp */
-    case 1240:	/* paciaz */
-    case 1216:	/* tsb */
-    case 1215:	/* psb */
-    case 1214:	/* esb */
-    case 1213:	/* autib1716 */
-    case 1212:	/* autia1716 */
-    case 1211:	/* pacib1716 */
-    case 1210:	/* pacia1716 */
-    case 1209:	/* xpaclri */
-    case 1207:	/* sevl */
-    case 1206:	/* sev */
-    case 1205:	/* wfi */
-    case 1204:	/* wfe */
-    case 1203:	/* yield */
-    case 1202:	/* bti */
-    case 1201:	/* csdb */
-    case 1200:	/* nop */
-    case 1199:	/* hint */
-      value = 1199;	/* --> hint.  */
-      break;
-    case 1222:	/* pssbb */
-    case 1221:	/* ssbb */
-    case 1220:	/* dfb */
+    case 1246:	/* autibsp */
+    case 1245:	/* autibz */
+    case 1244:	/* autiasp */
+    case 1243:	/* autiaz */
+    case 1242:	/* pacibsp */
+    case 1241:	/* pacibz */
+    case 1240:	/* paciasp */
+    case 1239:	/* paciaz */
+    case 1215:	/* tsb */
+    case 1214:	/* psb */
+    case 1213:	/* esb */
+    case 1212:	/* autib1716 */
+    case 1211:	/* autia1716 */
+    case 1210:	/* pacib1716 */
+    case 1209:	/* pacia1716 */
+    case 1208:	/* xpaclri */
+    case 1206:	/* sevl */
+    case 1205:	/* sev */
+    case 1204:	/* wfi */
+    case 1203:	/* wfe */
+    case 1202:	/* yield */
+    case 1201:	/* bti */
+    case 1200:	/* csdb */
+    case 1199:	/* nop */
+    case 1198:	/* hint */
+      value = 1198;	/* --> hint.  */
+      break;
+    case 1221:	/* pssbb */
+    case 1220:	/* ssbb */
+    case 1219:	/* dfb */
+    case 1217:	/* dsb */
+      value = 1217;	/* --> dsb.  */
+      break;
    case 1218:	/* dsb */
      value = 1218;	/* --> dsb.  */
      break;
-    case 1219:	/* dsb */
-      value = 1219;	/* --> dsb.  */
+    case 1234:	/* cpp */
+    case 1233:	/* dvp */
+    case 1232:	/* cfp */
+    case 1229:	/* tlbi */
+    case 1228:	/* ic */
+    case 1227:	/* dc */
+    case 1226:	/* at */
+    case 1225:	/* sys */
+      value = 1225;	/* --> sys.  */
      break;
-    case 1235:	/* cpp */
-    case 1234:	/* dvp */
-    case 1233:	/* cfp */
-    case 1230:	/* tlbi */
-    case 1229:	/* ic */
-    case 1228:	/* dc */
-    case 1227:	/* at */
-    case 1226:	/* sys */
-      value = 1226;	/* --> sys.  */
+    case 1230:	/* wfet */
+      value = 1230;	/* --> wfet.  */
      break;
-    case 1231:	/* wfet */
-      value = 1231;	/* --> wfet.  */
+    case 1231:	/* wfit */
+      value = 1231;	/* --> wfit.  */
      break;
-    case 1232:	/* wfit */
-      value = 1232;	/* --> wfit.  */
+    case 2044:	/* bic */
+    case 1294:	/* and */
+      value = 1294;	/* --> and.  */
      break;
-    case 2045:	/* bic */
-    case 1295:	/* and */
-      value = 1295;	/* --> and.  */
+    case 1277:	/* mov */
+    case 1296:	/* and */
+      value = 1296;	/* --> and.  */
      break;
-    case 1278:	/* mov */
-    case 1297:	/* and */
-      value = 1297;	/* --> and.  */
+    case 1281:	/* movs */
+    case 1297:	/* ands */
+      value = 1297;	/* --> ands.  */
      break;
-    case 1282:	/* movs */
-    case 1298:	/* ands */
-      value = 1298;	/* --> ands.  */
+    case 2045:	/* cmple */
+    case 1332:	/* cmpge */
+      value = 1332;	/* --> cmpge.  */
      break;
-    case 2046:	/* cmple */
-    case 1333:	/* cmpge */
-      value = 1333;	/* --> cmpge.  */
+    case 2048:	/* cmplt */
+    case 1335:	/* cmpgt */
+      value = 1335;	/* --> cmpgt.  */
      break;
-    case 2049:	/* cmplt */
-    case 1336:	/* cmpgt */
-      value = 1336;	/* --> cmpgt.  */
+    case 2046:	/* cmplo */
+    case 1337:	/* cmphi */
+      value = 1337;	/* --> cmphi.  */
      break;
-    case 2047:	/* cmplo */
-    case 1338:	/* cmphi */
-      value = 1338;	/* --> cmphi.  */
+    case 2047:	/* cmpls */
+    case 1340:	/* cmphs */
+      value = 1340;	/* --> cmphs.  */
      break;
-    case 2048:	/* cmpls */
-    case 1341:	/* cmphs */
-      value = 1341;	/* --> cmphs.  */
+    case 1274:	/* mov */
+    case 1362:	/* cpy */
+      value = 1362;	/* --> cpy.  */
      break;
-    case 1275:	/* mov */
+    case 1276:	/* mov */
    case 1363:	/* cpy */
      value = 1363;	/* --> cpy.  */
      break;
-    case 1277:	/* mov */
+    case 2055:	/* fmov */
+    case 1279:	/* mov */
    case 1364:	/* cpy */
      value = 1364;	/* --> cpy.  */
      break;
-    case 2056:	/* fmov */
-    case 1280:	/* mov */
-    case 1365:	/* cpy */
-      value = 1365;	/* --> cpy.  */
+    case 1269:	/* mov */
+    case 1376:	/* dup */
+      value = 1376;	/* --> dup.  */
      break;
-    case 1270:	/* mov */
+    case 1271:	/* mov */
+    case 1268:	/* mov */
    case 1377:	/* dup */
      value = 1377;	/* --> dup.  */
      break;
-    case 1272:	/* mov */
-    case 1269:	/* mov */
+    case 2054:	/* fmov */
+    case 1273:	/* mov */
    case 1378:	/* dup */
      value = 1378;	/* --> dup.  */
      break;
-    case 2055:	/* fmov */
-    case 1274:	/* mov */
-    case 1379:	/* dup */
-      value = 1379;	/* --> dup.  */
+    case 1272:	/* mov */
+    case 1379:	/* dupm */
+      value = 1379;	/* --> dupm.  */
      break;
-    case 1273:	/* mov */
-    case 1380:	/* dupm */
-      value = 1380;	/* --> dupm.  */
+    case 2049:	/* eon */
+    case 1381:	/* eor */
+      value = 1381;	/* --> eor.  */
      break;
-    case 2050:	/* eon */
-    case 1382:	/* eor */
-      value = 1382;	/* --> eor.  */
+    case 1282:	/* not */
+    case 1383:	/* eor */
+      value = 1383;	/* --> eor.  */
      break;
-    case 1283:	/* not */
-    case 1384:	/* eor */
-      value = 1384;	/* --> eor.  */
+    case 1283:	/* nots */
+    case 1384:	/* eors */
+      value = 1384;	/* --> eors.  */
      break;
-    case 1284:	/* nots */
-    case 1385:	/* eors */
-      value = 1385;	/* --> eors.  */
+    case 2050:	/* facle */
+    case 1389:	/* facge */
+      value = 1389;	/* --> facge.  */
      break;
-    case 2051:	/* facle */
-    case 1390:	/* facge */
-      value = 1390;	/* --> facge.  */
+    case 2051:	/* faclt */
+    case 1390:	/* facgt */
+      value = 1390;	/* --> facgt.  */
      break;
-    case 2052:	/* faclt */
-    case 1391:	/* facgt */
-      value = 1391;	/* --> facgt.  */
+    case 2052:	/* fcmle */
+    case 1403:	/* fcmge */
+      value = 1403;	/* --> fcmge.  */
      break;
-    case 2053:	/* fcmle */
-    case 1404:	/* fcmge */
-      value = 1404;	/* --> fcmge.  */
+    case 2053:	/* fcmlt */
+    case 1405:	/* fcmgt */
+      value = 1405;	/* --> fcmgt.  */
      break;
-    case 2054:	/* fcmlt */
-    case 1406:	/* fcmgt */
-      value = 1406;	/* --> fcmgt.  */
+    case 1266:	/* fmov */
+    case 1411:	/* fcpy */
+      value = 1411;	/* --> fcpy.  */
      break;
-    case 1267:	/* fmov */
-    case 1412:	/* fcpy */
-      value = 1412;	/* --> fcpy.  */
+    case 1265:	/* fmov */
+    case 1434:	/* fdup */
+      value = 1434;	/* --> fdup.  */
      break;
-    case 1266:	/* fmov */
-    case 1435:	/* fdup */
-      value = 1435;	/* --> fdup.  */
+    case 1267:	/* mov */
+    case 1765:	/* orr */
+      value = 1765;	/* --> orr.  */
      break;
-    case 1268:	/* mov */
+    case 2056:	/* orn */
    case 1766:	/* orr */
      value = 1766;	/* --> orr.  */
      break;
-    case 2057:	/* orn */
-    case 1767:	/* orr */
-      value = 1767;	/* --> orr.  */
+    case 1270:	/* mov */
+    case 1768:	/* orr */
+      value = 1768;	/* --> orr.  */
      break;
-    case 1271:	/* mov */
-    case 1769:	/* orr */
-      value = 1769;	/* --> orr.  */
+    case 1280:	/* movs */
+    case 1769:	/* orrs */
+      value = 1769;	/* --> orrs.  */
      break;
-    case 1281:	/* movs */
-    case 1770:	/* orrs */
-      value = 1770;	/* --> orrs.  */
+    case 1275:	/* mov */
+    case 1831:	/* sel */
+      value = 1831;	/* --> sel.  */
      break;
-    case 1276:	/* mov */
+    case 1278:	/* mov */
    case 1832:	/* sel */
      value = 1832;	/* --> sel.  */
      break;
-    case 1279:	/* mov */
-    case 1833:	/* sel */
-      value = 1833;	/* --> sel.  */
-      break;
    default: return NULL;
    }

--- a/opcodes/aarch64-dis-2.c
+++ b/opcodes/aarch64-dis-2.c
--- a/opcodes/aarch64-opc-2.c
+++ b/opcodes/aarch64-opc-2.c
@ -312,17 +312,17 @@ static const unsigned op_enum_table [] =
  391,
  413,
  415,
-  1271,
-  1276,
-  1269,
+  1270,
+  1275,
  1268,
-  1272,
-  1279,
-  1281,
-  1282,
+  1267,
+  1271,
  1278,
-  1284,
+  1280,
+  1281,
+  1277,
  1283,
+  1282,
  131,
 };

--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@ -3788,10 +3788,6 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
 	snprintf (buf, size, "%s", opnd->hint_option->name);
      break;

-    case AARCH64_OPND_CSRE_CSR:
-      snprintf (buf, size, "pdec");
-      break;
-
    default:
      assert (0);
    }
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@ -2418,8 +2418,6 @@ static const aarch64_feature_set aarch64_feature_f64mm_sve =
       | AARCH64_FEATURE_SVE, 0);
 static const aarch64_feature_set aarch64_feature_v8_r =
  AARCH64_FEATURE (AARCH64_FEATURE_V8_R, 0);
-static const aarch64_feature_set aarch64_feature_csre =
-  AARCH64_FEATURE (AARCH64_FEATURE_CSRE, 0);
 static const aarch64_feature_set aarch64_feature_ls64 =
  AARCH64_FEATURE (AARCH64_FEATURE_V8_6 | AARCH64_FEATURE_LS64, 0);
 static const aarch64_feature_set aarch64_feature_flagm =
@ -2470,7 +2468,6 @@ static const aarch64_feature_set aarch64_feature_flagm =
 #define I8MM      &aarch64_feature_i8mm
 #define ARMV8_R	  &aarch64_feature_v8_r
 #define ARMV8_7	  &aarch64_feature_v8_7
-#define CSRE	  &aarch64_feature_csre
 #define LS64	  &aarch64_feature_ls64
 #define FLAGM	  &aarch64_feature_flagm

@ -2582,8 +2579,6 @@ static const aarch64_feature_set aarch64_feature_flagm =
  { NAME, OPCODE, MASK, CLASS, 0, ARMV8_R, OPS, QUALS, FLAGS, 0, 0, NULL }
 #define V8_7_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
  { NAME, OPCODE, MASK, CLASS, 0, ARMV8_7, OPS, QUALS, FLAGS, 0, 0, NULL }
-#define _CSRE_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
-  { NAME, OPCODE, MASK, CLASS, 0, CSRE, OPS, QUALS, FLAGS, 0, 0, NULL }
 #define _LS64_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
  { NAME, OPCODE, MASK, CLASS, 0, LS64, OPS, QUALS, FLAGS, 0, 0, NULL }
 #define FLAGM_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
@ -3863,8 +3858,6 @@ struct aarch64_opcode aarch64_opcode_table[] =
  _TME_INSN ("tcommit", 0xd503307f, 0xffffffff, 0, 0, OP0 (), {}, 0),
  _TME_INSN ("ttest", 0xd5233160, 0xffffffe0, 0, 0, OP1 (Rd), QL_I1X, 0),
  _TME_INSN ("tcancel", 0xd4600000, 0xffe0001f, 0, 0, OP1 (TME_UIMM16), QL_IMM_NIL, 0),
-  /* CSRE Instructions.  */
-  _CSRE_INSN ("csr", 0xd50b721f, 0xffffffff, 0, OP1 (CSRE_CSR), {}, 0),
  /* System.  */
  CORE_INSN ("msr", 0xd500401f, 0xfff8f01f, ic_system, 0, OP2 (PSTATEFIELD, UIMM4), {}, F_SYS_WRITE),
  CORE_INSN ("hint",0xd503201f, 0xfffff01f, ic_system, 0, OP1 (UIMM7), {}, F_HAS_ALIAS),